CN102820290B - 封装集成电路的连接件设计 - Google Patents

封装集成电路的连接件设计 Download PDF

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Publication number
CN102820290B
CN102820290B CN201210159141.9A CN201210159141A CN102820290B CN 102820290 B CN102820290 B CN 102820290B CN 201210159141 A CN201210159141 A CN 201210159141A CN 102820290 B CN102820290 B CN 102820290B
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crown cap
metal column
wetting
connector
integrated circuit
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CN102820290A (zh
Inventor
余振华
郑心圃
侯上勇
谢政杰
许国经
施应庆
蔡柏豪
高金福
黄震麟
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及封装集成电路的连接件设计,其中涉及一种器件,该器件包括具有顶面的顶部介电层。金属柱具有位于顶部介电层的顶面上方的部分。非润湿的层形成在金属柱的侧壁上,其中,非润湿的层不可被熔化的焊料湿润。焊料区域被设置在金属柱上方并且与其电连接。

Description

封装集成电路的连接件设计
相关申请的交叉参考
本申请要求以下于2011年5月30日在先提交的第61/491,301号美国专利申请“3DICPackagingStructuresandMethods”的益处,该专利申请通过引证结合在此。
技术领域
本发明涉及半导体领域,更具体地,涉及封装集成电路的连接件设计。
背景技术
在形成半导体晶圆时,首先在半导体衬底的表面上形成集成电路器件,诸如,晶体管。然后在半导体衬底和集成器件上方形成互连结构。在半导体晶圆的表面上形成了连接件,以便能够访问集成电路器件。半导体晶圆被切割成多个半导体芯片。
可以通过回焊工艺来执行半导体芯片的封装,其中,对位于半导体芯片连接件之间的焊料区域进行回焊,从而将半导体芯片与其他封装部件(诸如,器件管芯、中介层、封装衬底等)相接合。在回焊工艺中,焊料区域被熔化,并且很难控制熔化的焊料区域的形状和轮廓。这导致以下问题,诸如,桥接,并且由此导致接合质量退化或产量减少。
发明内容
为解决上述问题,本发明提供了一种器件,包括:顶部介电层,具有顶面;金属柱,包括位于顶部介电层的顶面上方的部分;金属盖,位于金属柱上方,其中,金属盖的部分与金属柱相对齐,以及其中,金属盖的横向尺寸大于金属柱的横向尺寸;以及焊料区域,位于金属盖上方并且与金属盖电连接。
该器件进一步包括第一非润湿层,位于金属柱的侧壁上,其中,第一非润湿层不可被熔化的焊料湿润,以及其中,第一非润湿层包括用于形成金属柱的材料以及选自于基本上由氮、氧、及其组合所构成的组中的元素。
其中,金属盖和金属柱包括不同的材料,以及其中,第一非润湿层不在金属盖和金属柱之间延伸。
该器件进一步包括第二非润湿层,位于金属盖的侧壁上,其中,第二非润湿层不可被熔化的焊料湿润,以及其中,第二非润湿层不在金属盖和焊料区域之间延伸。
其中,第二不可湿润层包括金属盖的材料以及选自于基本上由氮、氧、及其组合所构成的组中的元素。
其中,顶部介电层和金属柱被包括在器件管芯中,其中,器件进一步包括通过焊料区域与器件管芯相接合的封装部件。
该器件进一步包括:金属焊盘;钝化层,位于金属焊盘上方;以及凸块底部金属(UBM),位于钝化层上方并且延伸进入到钝化层的开口中,从而与金属焊盘电连接,其中,UBM位于金属柱下方并且与金属柱相接触。
此外,还提供了一种器件,包括:聚合物层,具有顶面;含铜金属柱,具有位于聚合物层的顶面上方的部分;第一非润湿层,位于含铜金属柱的侧壁上,其中,第一非润湿层包括选自于基本上由氮化铜、氧化铜、以及氮氧化铜所构成的组中的材料;含镍金属盖,位于含铜金属柱上方,其中,含镍金属盖包括延伸超过含铜金属柱的相应侧壁的边缘部分;第二非润湿层,位于含镍金属盖的侧壁上,其中,第二非润湿层包括选自于基本上由氮化镍、氧化镍、以及氮氧化镍所构成的组中的材料;以及焊料区域,位于含镍金属盖上方。
其中,第一非润湿层不在含铜金属柱和含镍金属盖之间延伸。
其中,第二非润湿层不在含镍金属盖和焊料区域之间延伸。
其中,含镍金属盖的横向尺寸比含铜金属柱的横向尺寸更大。
其中,第二非润湿层延伸至与含镍金属盖的底面相接触,底面属于含镍金属盖延伸超过含铜金属柱的相应侧壁的边缘部分。
其中,含镍金属盖的边缘部分远离聚合物层弯曲。
其中,含镍金属盖的边缘部分朝向聚合物层弯曲。
聚合物层、含铜金属柱、以及含镍金属盖被包括在第一器件管芯中,其中,器件进一步包括通过焊料区域与第一器件管芯相接合的封装部件,以及其中,封装部件选自于基本上由第二器件管芯、中介层、封装衬底、及其组合所构成的组。
此外,还提供了一种方法,包括:形成第一封装部件的顶部介电层;形成在顶部介电层的顶面上方延伸的金属柱;形成位于金属柱上方的金属盖,其中,金属盖包括延伸超过金属柱的相应侧壁的边缘部分;以及形成位于金属盖上方的焊料区域。
该方法进一步包括对金属柱的侧壁表面进行处理,从而形成不可湿润的表层,其中,通过在工艺气体中处理金属柱的侧壁表面来执行处理,工艺气体选自于基本上由氮气(N2)、氧气(O2)、及其组合所构成的组。
其中,在处理期间,金属盖的侧壁表面被处理以形成额外的不可湿润的表层。
该方法进一步包括,在形成金属盖和焊料区域的步骤之后,执行蚀刻步骤来蚀刻金属柱,而金属盖不受到蚀刻,以及其中,对金属柱直接位于金属盖的边缘部分下方的部分进行蚀刻。
该方法进一步包括将第二封装部件与第一封装部件相接合,其中,接合的步骤包括回焊焊料区域。
附图说明
为了更全面地理解实施例及其优势,现将结合附图所进行的描述作为参考,其中:
图1至图6C是根据实施例制造封装部件的中间阶段的截面图;以及
图7A至图7E示出了根据多个实施例与另一个封装部件相接合的封装部件的截面图。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是说明性的,而不用于限制本发明的范围。
根据多个实施例提供了一种形成封装部件的连接件的方法。示出了根据实施例制造连接件的中间阶段。论述了实施例的变型。在各个视图和示例性实施例中,类似的参考标号被用于表示类似的元件。
参考图1,提供了包括有衬底10的晶圆2。在一个实施例中,衬底10是半导体衬底,诸如,硅衬底,然而可以由其他半导体材料形成该衬底,诸如,硅锗、硅碳、砷化镓等。可以在衬底10的表面上形成半导体器件14,该半导体器件可以包括晶体管、二极管、电阻器等。在衬底10上方形成了互连结构12,该互连结构包括有形成在其中并且与半导体器件14电连接的金属线和通孔(未示出)。该金属线和通孔可以由铜或铜合金形成,并且可以使用镶嵌工艺形成。互连结构12可以包括层间电介质(ILD)和金属间电介质(IMD)。
在可选的实施例中,晶圆2是中介层晶圆或封装衬底的晶圆,并且大体上不受包括了晶体管的有源器件以及无源器件(诸如,电阻器、电容器、电感器和/或类似的)的影响。在这些实施例中,衬底10可以由半导体材料或介电材料形成,并且连接件可以形成在衬底10的反面上,并且彼此电连接。
金属焊盘28形成在互连结构12上方。金属焊盘28可以包括铝(Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、其合金、和/或其多层。在示例性的实施例中,金属焊盘28由铜铝形成。金属焊盘28可以例如,通过下面的互连结构12与半导体器件14电连接。可以形成钝化层30来覆盖金属焊盘28的边缘部分。在示例性实施例中,钝化层30由聚酰亚胺或其他介电材料(诸如,氧化硅、氮化硅、以及其多层)形成。
参考图2,形成了凸块底部金属(UBM)层46。在实施例中,UBM层46包括有阻挡层40和位于阻挡层40上方的晶种层42。阻挡层40延伸到钝化层30的开口中并且与金属焊盘28电连接并且可以与其物理接触。阻挡层40可以是钛层、氮化钛层、钽层、或氮化钽层、或由钛合金或钽合金所形成的层。晶种层42的材料可以包括铜或铜合金,并且晶种层42由此可选地在下文中被称为铜晶种层。然而,也可以包括其他金属,诸如,银、金、铝、铂、镍、镍合金、钨合金、铬、铬合金、以及其组合。在实施例中,使用物理汽相沉积(PVD)或其他可应用的方法来形成阻挡层40和晶种层42。阻挡层40可以具有约在之间的厚度。晶种层42可以具有约在之间的厚度,然而也可以使用不同的厚度。
图3示出了掩模48的形成,该掩模可以由例如光刻胶或干膜形成。图案化掩模48,并且通过掩模48中的开口45暴露出UBM层46的一部分。然后,形成金属柱50。在实施例中,晶圆2被放置在电镀液中(未示出),并且执行喷镀步骤来在UBM层46和开口45中形成金属柱50。该喷镀可以是电镀、化学镀、浸镀等。在示例性的实施例中,金属柱50包括纯铜、基本纯的铜、或铜合金。
参考图4A,金属盖52形成在金属柱50上。金属盖52用作形成金属间化合物(IMC)的阻挡层。在实施例中,金属盖52包括镍。在可选的实施例中,金属盖52包括其他材料,诸如,锡、铂、或其合金。金属盖52也可以是复合层,该复合层包括多个层,诸如,镍层、铂层,等。然后,在金属盖52上形成焊料盖54,该焊料盖可以包括Sn-Ag、Sn-Cu、Sn-Ag-Cu等。例如,可以使用电镀,利用掩模48作为电镀掩模来电镀金属盖52和焊料盖54两者。因此,金属盖52和焊料盖54的边缘要与金属柱50的相应的边缘对齐。
图4B示出了可选的实施例,其中,没有形成金属盖52,而焊料盖54则直接形成在含铜金属柱50上并且与其物理接触。类似地,例如,可以使用电镀,利用掩模48作为电镀掩模来电镀焊料盖54。因此,焊料盖54的边缘要与金属柱50的相应的边缘对齐。
图5A和图5B示出了去除掩模48以及被掩模48所覆盖着的部分UBM层46。例如,可以使用蚀刻来执行该去除。在分别与图4A和图4B中的结构对应的图5A和图5B所示的所得到的结构中,金属盖52的侧壁52A和金属柱50的侧壁50A被露出。侧壁52A和侧壁50A可被(熔化的)焊料润湿。
任选地,如图5C所示,在去除了UBM层46之后,可以将金属柱50的横向尺寸D1减小到小于金属盖52的横向尺寸D2。这可以通过在去除了掩模48之后进一步蚀刻金属柱50来实现。可以使用蚀刻剂来执行该蚀刻,该蚀刻剂攻击金属柱50,但不攻击金属盖52和焊料区域54。在一个实施例中,金属盖52的边缘52A以距离ΔD延伸超过金属柱50的相应边缘50A,该距离ΔD可以例如大于大约1μm,或大于大约2μm。在可选的实施例中,可以通过形成第一光刻胶(未示出)从而形成金属柱50来形成大于金属柱50的金属盖52。第一光刻胶的图案基本上与掩模48的图案相同。金属柱50的顶面可以与第一光刻胶的顶面大体上齐平。然后,在不去除第一光刻胶的情况下,可以形成并且限定出第二光刻胶(未示出),从而形成横向尺寸等于D2的开口,金属柱50被该开口暴露出来。然后,可以对位于第二光刻胶中的开口中的金属盖52进行电镀。
然后,如图6A至图6C所示,使用处理气体在晶圆2上进行处理,该处理气体包括氮(N2)、氧(O2)、或包括了氮(N2)和氧(O2)的混合气体。可以在包括了处理气体的热环境中执行该处理,其中,可以将晶圆2加热到在大约100℃和大约200℃之间的温度,该加热的持续时间在大约10分钟和大约120分钟之间。可选地,可以使用由处理气体产生的等离子体来执行该处理,其中,处理的持续时间可以在大约0.1分钟和大约15分钟之间。如图6A所示,该处理导致在金属柱50和金属盖52的侧壁表面上分别产生了非润湿的层51和53。由于非润湿的层51和53分别是由金属柱50和金属盖52转变而成的,所以非润湿的层51和53包括了金属柱50和金属盖52的相应的材料以及额外的元素,诸如,氮、氧、及其组合。例如,根据金属柱50和金属盖52的材料以及处理气体,非润湿的层53可以包括氮化物、氧化物,或氮氧化物(金属盖52中的金属的氮氧化物),诸如,NiN、NiO、或NiON。非润湿的层51可以包括氮化物、氧化物、或氮氧化物(金属柱50中的金属的氮氧化物),诸如,CuN、CuO、或CuON。非润湿的层51和53不可被(熔化的)焊料湿润,并且熔化的焊料很难附在其上。
在图6B中,没有形成金属盖52,而非润湿的层51形成在金属柱50的侧壁表面上。图6C示出了非润湿的层51和53的形成,其中,金属柱50横向地小于金属盖52。在这些实施例中,非润湿的层53可以包括形成在金属盖52的底面上的部分,该底面属于金属盖52延伸超过金属柱50的部分。根据金属柱50和金属盖52的材料以及处理气体,图6B和图6C中的非润湿的层51和53的材料可以与图6A中的基本上相同。在用于形成非润湿的层51和53的处理之后,可以沿着虚线62将图6A、图6B、以及图6C中所示的晶圆2切割成管芯100。
图7A至图7E示出了将封装部件100与封装部件200相接合。根据一些实施例,封装部件200是器件管芯,该器件管芯可以是图形管芯、存储器管芯、磁芯器件管芯等。封装部件200在其中可以包括有源器件214,诸如,晶体管。可选地,封装部件200可以包括无源器件(也称为部件214),并且可以不受到有源器件的影响。可选地,封装部件200可以是中介层、封装衬底、印刷电路板(PCB)等。封装部件200可以包括金属柱150,并且任选地包括金属盖152,其中,如封装部件100中的相应的金属柱50和金属盖52那样,金属柱150和金属盖152可以由基本上相同的材料形成,并且具有基本上相同的性能和尺寸。为了接合封装部件100和200,执行回焊来熔化和接合焊料盖54(图6A至图6C)和封装部件200中的焊料盖(如果存在的话)。在回焊之后,形成用于接合封装部件100和200的焊料区域60。
参考图7A,由于向金属盖52施加了应力,所以金属盖52的边缘部分朝向封装部件100的衬底10弯曲,该边缘部分延伸超过了金属柱50。图7B示出,金属盖52大体上是平坦的。在图7C中,由于向金属盖52施加了应力,所以金属盖52的边缘部分远离封装部件100的衬底弯曲。该应力部分由回焊工艺产生。图7D示出了金属盖52具有与下面的金属柱50大体上相同的横向尺寸的实施例。图7E示出了没有形成金属盖52并且焊料区域60与金属柱50相接触的实施例。
在图7A至图7E的实施例中,由于层51和53是不可湿润的,所以如果形成了金属盖52的话,熔化的焊料的表面张力使焊料区域60被限制在金属盖52的顶面中,或如果没有形成金属盖52的话,则将其限制在金属柱50的顶面上。因此,焊料区域60不会流向金属柱50和金属盖52的侧壁。由此很好地控制了焊料区域60的轮廓,并且降低了在相邻的焊料区域之间出现桥接的风险。另外,具有比下面的金属柱更大的金属盖可以有效地固定焊料区域,并且同样可以减小焊料溢出的风险。
根据实施例,一种器件包括具有顶面的顶部介电层。金属柱具有位于顶部介电层的顶面上方的部分。非润湿的层形成在金属柱的侧壁上,其中,非润湿的层不可被熔化的焊料湿润。焊料区域被设置在金属柱上方并且与其电连接。
根据其他实施例,一种器件包括具有顶面的聚合物层,以及含铜金属柱,具有位于聚合物层的顶面上方的部分。第一非润湿层设置在含铜金属柱的侧壁上,其中,第一非润湿层包括选自于基本上由氮化铜、氧化铜、以及氮氧化铜所构成的组中的材料。含镍金属盖形成在含铜金属柱上方。第二非润湿的层设置在含镍金属盖的侧壁上,其中,第二非润湿层包括选自于基本上由氮化镍、氧化镍、以及氮氧化镍所构成的组中的材料。焊料区域设置在含镍金属盖上方。
根据另外其他的实施例,一种方法包括形成封装部件的顶部介电层,形成在顶部介电层的顶面上方延伸的金属柱,以及形成位于金属柱上方并且与其电连接的焊料区域。然后,对金属柱的侧壁表面进行处理,从而形成不可湿润的表层。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。

Claims (14)

1.一种封装集成电路的连接件,包括:
顶部介电层,具有顶面;
金属柱,包括位于所述顶部介电层的顶面上方的部分;
金属盖,位于所述金属柱上方,其中,所述金属盖的部分与所述金属柱相对齐,以及其中,所述金属盖的横向尺寸大于所述金属柱的横向尺寸;以及
焊料区域,位于所述金属盖上方并且与所述金属盖电连接;
第二非润湿层,位于所述金属盖的侧壁上,其中,所述第二非润湿层不可被熔化的焊料湿润,以及其中,所述第二非润湿层不在所述金属盖和所述焊料区域之间延伸;
所述第二非润湿层包括形成在所述金属盖的底面上的部分,所述底面属于所述金属盖延伸超过所述金属柱的部分,所述金属盖的边缘部分朝向封装部件的衬底弯曲,所述边缘部分延伸超过所述金属柱。
2.根据权利要求1所述的封装集成电路的连接件,进一步包括第一非润湿层,位于所述金属柱的侧壁上,其中,所述第一非润湿层不可被熔化的焊料湿润,以及其中,所述第一非润湿层包括用于形成所述金属柱的材料以及选自于由氮、氧、及其组合所构成的组中的元素。
3.根据权利要求2所述的封装集成电路的连接件,其中,所述金属盖和所述金属柱包括不同的材料,以及其中,所述第一非润湿层不在所述金属盖和所述金属柱之间延伸。
4.根据权利要求1所述的封装集成电路的连接件,其中,所述第二非湿润层包括所述金属盖的材料以及选自于由氮、氧、及其组合所构成的组中的元素。
5.根据权利要求1所述的封装集成电路的连接件,其中,所述顶部介电层和所述金属柱被包括在器件管芯中,其中,所述封装集成电路的连接件进一步包括通过所述焊料区域与所述器件管芯相接合的封装部件。
6.根据权利要求1所述的封装集成电路的连接件,进一步包括:
金属焊盘;
钝化层,位于所述金属焊盘上方;以及
凸块底部金属,位于所述钝化层上方并且延伸进入到所述钝化层的开口中,从而与所述金属焊盘电连接,其中,所述凸块底部金属位于所述金属柱下方并且与所述金属柱相接触。
7.一种封装集成电路的连接件,包括:
聚合物层,具有顶面;
含铜金属柱,具有位于所述聚合物层的顶面上方的部分;
第一非润湿层,位于所述含铜金属柱的侧壁上,其中,所述第一非润湿层包括选自于由氮化铜、氧化铜、以及氮氧化铜所构成的组中的材料;
含镍金属盖,位于所述含铜金属柱上方,其中,所述含镍金属盖包括延伸超过所述含铜金属柱的相应侧壁的边缘部分;
第二非润湿层,位于所述含镍金属盖的侧壁上,其中,所述第二非润湿层包括选自于由氮化镍、氧化镍、以及氮氧化镍所构成的组中的材料;以及
焊料区域,位于所述含镍金属盖上方;
所述第二非润湿层延伸至与所述含镍金属盖的底面相接触,所述底面属于所述含镍金属盖延伸超过所述含铜金属柱的相应侧壁的边缘部分;
所述含镍金属盖的所述边缘部分朝向所述聚合物层弯曲。
8.根据权利要求7所述的封装集成电路的连接件,其中,所述第一非润湿层不在所述含铜金属柱和所述含镍金属盖之间延伸。
9.根据权利要求7所述的封装集成电路的连接件,其中,所述第二非润湿层不在所述含镍金属盖和所述焊料区域之间延伸。
10.根据权利要求7所述的封装集成电路的连接件,其中,所述含镍金属盖的横向尺寸比所述含铜金属柱的横向尺寸更大。
11.根据权利要求7所述的封装集成电路的连接件,所述聚合物层、所述含铜金属柱、以及所述含镍金属盖被包括在第一器件管芯中,其中,所述封装集成电路的连接件进一步包括通过所述焊料区域与所述第一器件管芯相接合的封装部件,以及其中,所述封装部件选自于由第二器件管芯、中介层、封装衬底、及其组合所构成的组。
12.一种形成封装部件的连接件的方法,包括:
形成第一封装部件的顶部介电层;
形成在所述顶部介电层的顶面上方延伸的金属柱;
形成位于所述金属柱上方的金属盖,其中,所述金属盖包括延伸超过所述金属柱的相应侧壁的边缘部分;以及
形成位于所述金属盖上方的焊料区域;
对所述金属柱的侧壁表面进行处理,从而形成不可湿润的表层,其中,通过在工艺气体中处理所述金属柱的侧壁表面来执行所述处理,所述工艺气体选自于由氮气(N2)、氧气(O2)、及其组合所构成的组;
在所述处理期间,所述金属盖的侧壁表面被处理以形成额外的不可湿润的表层,所述不可湿润的表层包括形成在所述金属盖的底面上的部分,所述底面属于所述金属盖延伸超过所述金属柱的部分,所述金属盖的边缘部分朝向封装部件的衬底弯曲,所述边缘部分延伸超过所述金属柱。
13.根据权利要求12所述的形成封装部件的连接件的方法,进一步包括,在形成所述金属盖和所述焊料区域的步骤之后,执行蚀刻步骤来蚀刻所述金属柱,而所述金属盖不受到蚀刻,以及其中,对所述金属柱直接位于所述金属盖的边缘部分下方的部分进行蚀刻。
14.根据权利要求12所述的形成封装部件的连接件的方法,进一步包括将第二封装部件与所述第一封装部件相接合,其中,所述接合的步骤包括回焊所述焊料区域。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8637392B2 (en) * 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
US8610285B2 (en) 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
JP6076020B2 (ja) * 2012-02-29 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
TWI527170B (zh) 2012-05-11 2016-03-21 矽品精密工業股份有限公司 半導體封裝件及其製法
KR101971279B1 (ko) * 2012-08-30 2019-04-22 에스케이하이닉스 주식회사 범프 구조물 및 그 형성 방법
US20140362550A1 (en) * 2013-06-11 2014-12-11 Nvidia Corporation Selective wetting process to increase solder joint standoff
CN103367304B (zh) * 2013-07-19 2016-12-28 日月光半导体制造股份有限公司 封装基板、覆晶式封装及其制造方法
US9355980B2 (en) * 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
GB2520952A (en) * 2013-12-04 2015-06-10 Ibm Flip-chip electronic device with carrier having heat dissipation elements free of solder mask
JP6282454B2 (ja) * 2013-12-10 2018-02-21 新光電気工業株式会社 半導体パッケージの製造方法
US9875980B2 (en) * 2014-05-23 2018-01-23 Amkor Technology, Inc. Copper pillar sidewall protection
CN105374775B (zh) * 2014-09-02 2018-05-04 中芯国际集成电路制造(上海)有限公司 焊盘、半导体器件和半导体器件的制造工艺
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
US9842819B2 (en) * 2015-08-21 2017-12-12 Invensas Corporation Tall and fine pitch interconnects
KR102458034B1 (ko) 2015-10-16 2022-10-25 삼성전자주식회사 반도체 패키지, 반도체 패키지의 제조방법, 및 반도체 모듈
US9607973B1 (en) * 2015-11-19 2017-03-28 Globalfoundries Inc. Method for establishing interconnects in packages using thin interposers
EP3185290A1 (en) * 2015-12-24 2017-06-28 IMEC vzw Method for self-aligned solder reflow bonding and devices obtained therefrom
TWI563909B (en) * 2016-01-29 2016-12-21 Delta Electronics Inc Thermo electric heat dissipation module
US10103069B2 (en) 2016-04-01 2018-10-16 X-Celeprint Limited Pressure-activated electrical interconnection by micro-transfer printing
US10222698B2 (en) 2016-07-28 2019-03-05 X-Celeprint Limited Chiplets with wicking posts
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
US10103119B2 (en) * 2017-01-31 2018-10-16 Globalfoundries Inc. Methods of forming integrated circuit structure for joining wafers and resulting structure
US10424552B2 (en) 2017-09-20 2019-09-24 Texas Instruments Incorporated Alloy diffusion barrier layer
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
EP3770962A1 (en) 2019-07-26 2021-01-27 Infineon Technologies AG Semiconductor module arrangement
US11694982B2 (en) 2021-02-25 2023-07-04 Qualcomm Incorporated Sidewall wetting barrier for conductive pillars
CN114908390A (zh) * 2022-05-11 2022-08-16 甬矽半导体(宁波)有限公司 一种布线层制作方法与半导体器件
CN114649287A (zh) * 2022-05-19 2022-06-21 甬矽半导体(宁波)有限公司 一种芯片制作方法、芯片连接方法以及芯片

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005417A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 用于铜柱结构的自对准保护层

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1491483A (en) * 1974-08-08 1977-11-09 Pilkington Brothers Ltd Glass manufacturing apparatus and process
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
FR2667724B1 (fr) * 1990-10-09 1992-11-27 Thomson Csf Procede de realisation des metallisations d'electrodes d'un transistor.
JPH06505597A (ja) * 1991-03-04 1994-06-23 モトローラ・インコーポレーテッド 非導電性電子回路パッケージ用シールド装置
JP3078646B2 (ja) 1992-05-29 2000-08-21 株式会社東芝 インジウムバンプの製造方法
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6388203B1 (en) * 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5808874A (en) * 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US6051190A (en) * 1997-06-17 2000-04-18 Corning Incorporated Method and apparatus for transferring and dispensing small volumes of liquid and method for making the apparatus
JP3654485B2 (ja) 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
JP4131595B2 (ja) 1999-02-05 2008-08-13 三洋電機株式会社 半導体装置の製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6387793B1 (en) * 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6656611B2 (en) * 2001-07-20 2003-12-02 Osram Opto Semiconductors Gmbh Structure-defining material for OLEDs
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
TW550800B (en) * 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7391112B2 (en) 2005-06-01 2008-06-24 Intel Corporation Capping copper bumps
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
DE102005029784A1 (de) 2005-06-24 2007-01-11 Siemens Ag Elektronikbaugruppe und Verfahren zur Herstellung einer Elektronikbaugruppe
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7498119B2 (en) * 2006-01-20 2009-03-03 Palo Alto Research Center Incorporated Process for forming a feature by undercutting a printed mask
US7510939B2 (en) * 2006-01-31 2009-03-31 International Business Machines Corporation Microelectronic structure by selective deposition
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US7687311B1 (en) 2008-11-13 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing stackable dies
KR20100060968A (ko) 2008-11-28 2010-06-07 삼성전기주식회사 메탈 포스트를 구비한 기판 및 그 제조방법
DE102008063401A1 (de) * 2008-12-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem kosteneffizienten Chipgehäuse, das auf der Grundlage von Metallsäuren angeschlossen ist
US8159070B2 (en) * 2009-03-31 2012-04-17 Megica Corporation Chip packages
US7919406B2 (en) * 2009-07-08 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming pillar bump structure having sidewall protection
US8637392B2 (en) * 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8232193B2 (en) * 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US8405199B2 (en) * 2010-07-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar for semiconductor substrate and method of manufacture
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8242011B2 (en) * 2011-01-11 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal pillar

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005417A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 用于铜柱结构的自对准保护层

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