TWI498978B - 在半導體封裝中有內部中心柱的焊接凸塊 - Google Patents

在半導體封裝中有內部中心柱的焊接凸塊 Download PDF

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Publication number
TWI498978B
TWI498978B TW097128551A TW97128551A TWI498978B TW I498978 B TWI498978 B TW I498978B TW 097128551 A TW097128551 A TW 097128551A TW 97128551 A TW97128551 A TW 97128551A TW I498978 B TWI498978 B TW I498978B
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Taiwan
Prior art keywords
layer
inner center
bump
substrate
semiconductor package
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TW097128551A
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English (en)
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TW200915455A (en
Inventor
Yaojian Lin
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Stats Chippac Ltd
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Publication of TW200915455A publication Critical patent/TW200915455A/zh
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Publication of TWI498978B publication Critical patent/TWI498978B/zh

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Description

在半導體封裝中有內部中心柱的焊接凸塊
一般來說，本發明有關於半導體封裝，而更特別的是有關於半導體元件的覆晶封裝中之焊接凸塊結構。
半導體元件存在於現代社會所使用的諸多產品中。半導體提供消費性商品之應用，諸如娛樂、通訊、網路、電腦、以及居家用品市場。在工業或商業市場中，半導體存在於軍事、航空、汽車工業、工業控制器、以及辦公室設備。
半導體元件之製造涵蓋具有複數晶粒的晶圓之形成。每個晶粒皆包含執行種種電氣功能之數百或者數千個電晶體以及其他主動與被動元件。就一個所給定的晶圓而言，晶圓的每個晶粒典型皆執行相同的電氣功能。前端製造通常指稱半導體元件於晶圓上之形成。已完成的晶圓具有一裝容著電晶體與其他主動之主動側及被動構件。後端製造指稱裁剪或切割該已完成晶圓成為個別之晶粒，並且之後針對結構支撐及/或環境絕緣來封裝其晶粒。
半導體製造的其中之一目標為產生一種在較低成本下適於較快速、可靠、較小、以及較高密度的積體電路(IC)之封裝。覆晶封裝或者晶圓級封裝(WLP)理想上適於需要高速、高密度、以及較多接腳數之IC。覆晶形態之封裝涵蓋將晶粒的主動側架置朝下而面向於晶片載體基板或者印 刷電路板(PCB)。透過包含大量傳導性焊接凸塊或球體之焊接凸塊結構，來實現晶粒上的主動元件與載體基板上的傳導軌跡之間的電氣與機械相互連接。藉由施加至半導體基板上所配置的接觸墊之重熔製程來形成焊接凸塊。之後將焊接凸塊焊接至載體基板。覆晶半導體封裝提供一種從晶粒上的主動元件至載體基板之短電氣傳導路徑，藉以減少訊號之傳播、降低電容、以及實現整體較佳的電路效能。
對產品的測試、製造產量、以及壽命、乃至服務而言，焊接凸塊的可靠度與整體性具有其重要性。元件的可靠度為每個焊接凸塊相互連接的材料與結構整體性、以及其電氣相互連接的有效性之函數。諸多習知技術之元件已經試圖修改焊接凸塊的基本結構，包含將第一凸塊封入第二凸塊之內，如美國專利第6077765號與美國專利申請案第20040266066號中所說明的。然而，已知這些習知技術的焊接凸塊結構會呈現出軟弱的焊接接合點，特別是對細微節距之應用場合而言。此外，某些習知技術的凸塊結構仍舊具有高接合點電阻，此會增加電力的消耗以及熱的散逸。焊接凸塊結構目前所存在的需求為增強強度與可靠度、以及較低接合點之電阻。
在某一實施例中，本發明為一種覆晶半導體封裝，其包含一具有形成於其上的複數個主動元件之基板。以電氣接觸於複數個主動元件，將一接觸墊形成於基板上。以電 氣接觸於接觸墊，將一中間傳導層配置於基板之上。一內部中心柱形成於中間傳導層之上。一第一阻障層與濕潤層形成於內部中心柱之上。藉由電鍍其焊接材料與重熔該焊接材料，以形成焊接凸塊，而將一焊接凸塊形成於第一阻障層與濕潤層以及內部中心柱周圍。焊接凸塊電氣接觸於中間傳導層。內部中心柱以焊接凸塊三分之二的高度而延伸於焊接凸塊之中。
在另一實施例中，本發明為一種半導體封裝，其包含一具有形成於其上的複數個主動元件之基板。以電氣接觸於複數個主動元件，將一接觸墊形成於基板上。以電氣接觸於接觸墊，將一中間傳導層配置於基板之上。一內部中心柱形成於中間傳導層之上。一第一阻障層與濕潤層形成於內部中心柱之上。藉由電鍍其焊接材料與重熔該焊接材料，以形成焊接凸塊，而將焊接凸塊形成於第一阻障層與濕潤層以及內部中心柱周圍。
在另一實施例中，本發明為一種半導體封裝，其包含一具有形成於其上的複數個主動元件之基板。以電氣接觸於複數個主動元件，將一接觸墊形成於基板上。一內部中心柱形成於接觸墊之上。藉由電鍍其焊接材料與重熔該焊接材料，以形成焊接凸塊，而將焊接凸塊形成於內部中心柱周圍。
在另一實施例中，本發明為一種製作半導體封裝之方法，所包含的步驟為提供一具有形成於其上的複數個主動元件之基板、以電氣接觸於複數個主動元件而將一接觸墊 形成於基板之上、將一中間傳導層以電氣接觸於接觸墊而配置於基板之上、將一內部中心柱形成於中間傳導層之周圍、以及藉由電鍍其焊接材料與重熔該焊接材料以形成焊接凸塊而將焊接凸塊形成於內部中心柱周圍。
本發明說明於以下參照圖示的一個或者多個實施例中，其中相似的數字代表相同的或者相似的組件。本發明雖是按照為達到本發明目的之最佳模式所說明，然對於熟諳本項技藝之人士而言，應即瞭解此是欲以涵蓋可納入在由後載申請專利範圍(及其如後述揭文和圖式所支援的等同項)所加定義之本發明精神和範圍內的替代、修改與等同項目。
半導體元件的製造涵蓋具有複數個晶粒的晶圓之形成。每個晶粒皆包含執行一種或多種電氣功能之數百或者數千個電晶體以及其他主動與被動元件。就一個所給定的晶圓而言，晶圓的每個晶粒典型皆執行相同的電氣功能。前端製造通常指稱半導體元件於晶圓上之形成。已完成的晶圓具有一裝容著電晶體與其他主動與被動構件之主動側。而後端製造則是指將該所獲晶圓切割或單劃為個別晶粒，然後封裝該晶粒以供結構支撐及/或環境隔離。
半導體晶圓通常包含一具有配置於其上的半導體元件之主動前側表面、以及一以諸如矽的整塊半導體材料所形成之背側表面。主動前側表面裝容著複數個的半導體晶 粒。藉由種種半導體製程來形成其主動表面，包含疊層、繪製圖案、摻雜、以及熱處理。在疊層製程中，藉由涵蓋熱氧化、氮化、化學氣相沈積、蒸發、以及噴濺之技術，半導體材料會生成或者沈積於基板上。繪製圖案包含使用光蝕刻微影技術，藉以遮蔽表面區域，並且蝕刻掉所不需要的材料，藉以形成特定之結構。摻雜製程會藉由熱擴散或者離子灌輸來注射摻雜物材料之濃度。就諸如焊墊之電氣相互連接而言，主動表面質實為平面的且均勻的。
覆晶半導體封裝以及晶圓級封裝(WLP)一般用以需要高速、高密度、以及較多接腳數之積體電路(IC)。覆晶形態之封裝10包含將晶粒14的主動區域12架置朝下而面向於一晶片載體基板或者印刷電路板(PCB)16，如圖1所示。根據晶粒的電氣設計，主動區域12裝容著主動與被動元件、傳導層、以及介電層。透過包含大量個別傳導性焊接凸塊或球體22之焊接凸塊結構20來實現電氣與機械之相互連接。焊接凸塊形成於凸塊墊24上，此凸塊墊24則配置於主動區域12上。在本範例中，凸塊墊24具有細微的節距，例如於150微米(μm)之層級。凸塊墊24藉由主動區域12中的傳導軌跡而連接至主動電路。藉由焊接之重熔製程，將焊接凸塊22電氣與機械式連接至載體基板16上的接觸墊26。覆晶半導體封裝提供從晶粒14上的主動元件至載體基板16上的傳導軌跡之短電氣連接，藉以減少訊號之傳播、降低電容、以及實現整體較佳的電路效能。
圖2a－2d闡述焊接凸塊支撐結構的形成之剖面圖。所要加註的是，就圖2－4而言，以主動表面朝上，來決定晶圓之方位。在圖2a中，金屬接觸墊32形成於矽基板34之上。接觸墊32由鋁(Al)、銅(Cu)、或者鋁/銅合金所製作。透過形成於基板34上的傳導軌跡或疊層，將接觸墊32電氣連接至主動與被動元件。之後形成焊接凸塊，以連接至金屬接觸墊。第一鈍化層36形成於基板34之上，具有一開孔以顯露出金屬接觸墊32。透過一種蝕刻製程所定義的光阻遮罩，藉由移除一部份的鈍化層36來實現該開孔。能夠以氮化矽(SiN)、二氧化矽(SiO2 )、氮氧化矽(SiON)、聚亞醯胺、苯并環丁烯(BCB)、聚苯并噁唑(PBO)、或者其他絕緣材料來製作第一鈍化層36。第二鈍化層38形成於鈍化層36之上。能夠使用相似於鈍化層36所說明的材料來製作鈍化層38。再者，藉由移除一部份的鈍化層38，來形成一個開孔，藉以顯露出金屬接觸墊32。在另一實施例中，藉由重新鈍化來形成鈍化層36－38。底部凸塊金屬化(UBM)使用黏合層40、隨選阻障層42、以及種子層44。黏合層40形成於鈍化層38之上，以接合於阻障層42。黏合層40可以是鈦(Ti)、鋁(Al)、鈦鎢(TiW)、以及鉻(Cr)。阻障層42會限制Cu之擴散於晶粒的主動區域。能夠以鎳(Ni)、Ni－合金、鉑(Pt)、鈀(Pd)、TiW、以及鉻銅(CrCu)來製作阻障層42。種子層44形成於阻障層42之上。能夠以Cu、Ni、鎳釩(NiV)、Cu、金(Au)、或者Al來製作種子層44。種子層44會跟隨鈍化層36－38與接觸墊32之輪廓線， 並且充當形成於金屬接觸墊32與焊接凸塊之間的一種中間傳導層。種子層44電氣連接至接觸墊32。
在圖2b中，對光阻層50進行塗佈、曝光、顯像、以及蝕刻，藉以形成第一開孔或具有寬度之圓柱圓柱，此寬度則小於接觸墊32之寬度。第一開孔位於接觸墊32約略中心部分。藉由一種無電電鍍或電解電鍍製程，將內部中心柱52沈積於光阻層50之間的第一開孔中。以Cu、Ni、Al、或者其他適合的金屬來製作中心柱52。藉由範例，內部中心柱52能夠具有矩形或者圓柱形之形狀因數，儘管也預期著其他形狀。內部中心柱52的高度大約為光阻層50厚度的三分之二，或者在某一實施例中，高度大約為50μm，而直徑大約為50μm。
在圖2c中，再次將光阻層50曝光、顯像、以及蝕刻，而不將該層完全剝離，藉以在第一開孔之上，形成第二開孔或圓柱。第二開孔具有大於接觸墊32寬度之寬度。從光阻層50中的第二開孔邊緣至中心柱52之距離小於光阻層50之厚度。阻障層54形成於種子層44與中心柱52之上，以為金屬(Cu)擴散隔離之用。以Ni、Pt、或者其他適合的金屬來製作阻障層54。濕潤層56形成於阻障層54之上。以Cu、Au、或者Ag來製作濕潤層56。在另一實施例中，能夠交換其順序，亦即阻障層54能夠形成於濕潤層56之上。
透過電解電鍍或無電電鍍製程，將傳導性材料電氣沈積於濕潤層56之上，來形成焊接層58。焊接材料能夠是 任何一種金屬，例如，錫(Sn)、鉛(Pb)、Ni、Au、銀(Ag)、Cu、鉍(Bi)、以及其合金、或者其他傳導性材料之混合物。在某一實施例中，焊接材料為63%重量百分比的Sn以及37%重量百分比的Pb。焊接層58與種子層44之間的阻障層以及濕潤層會增強凸塊支撐結構的可靠度。
在圖2d中，將光阻層50任何一個剩餘部分剝離。蝕刻製程會移除位於焊接凸塊結構的區域外部任何一部份的種子層44、黏合層42、以及阻障層40，例如在UBM層會持續延伸於鄰接焊接凸塊之間的應用中。藉由將傳導性材料加熱至其熔點之上，對焊接層58進行重熔處理，藉以在半導體基板34之上形成圓球體或者凸塊60。在某一實施例中，焊接凸塊60高度大約為75μm，而直徑則大約為80μm。焊接凸塊60電氣接觸著中心柱52、種子層44、以及金屬接觸墊32。
如本發明之特徵，藉由電鍍其焊接材料，並且之後重熔該焊接材料，以形成焊接凸塊，而將焊接凸塊形成於阻障層54、濕潤層56、以及內部中心柱52之周圍。在某一實施例中，內部中心柱52會以至少焊接凸塊三分之二的高度而延伸於焊接凸塊之中。中心柱的高度典型小於凸塊結構20中的鄰接焊接凸塊之間的節距。中心柱的寬度典型大約為凸塊直徑的40%至60%。從焊接底部邊緣至中心柱邊緣的距離大約為凸塊直徑的20%至30%。這些特徵會降低焊接接合點的電阻，並且改善凸塊支撐結構之強度與可靠度。
覆晶封裝的替代實施例顯示於圖3a。如以上所說明，金屬接觸墊32形成於基板34之上。接觸墊32透過形成於基板34上的傳導層而電氣連接至主動與被動元件。鈍化層36形成於基板34之上，其中的開孔會露出金屬接觸墊32。黏合層40形成於鈍化層36之上，以為接合至阻障層42之用。阻障層42會限制Cu擴散於晶粒的主動區域之中。種子層44形成於阻障層42之上。種子層44為一種中間傳導層，形成於金屬接觸墊32與焊接凸塊之間。種子層44電氣連接至接觸墊32。
首先將光阻層50塗佈、曝光、顯像、以及蝕刻，藉以形成第一開孔或圓柱，如圖2b中所說明的，其所具有的寬度小於接觸墊32之寬度。第一開孔位於接觸墊32約略中心部分。藉由一種無電電鍍或電解電鍍製程，將內部中心柱52沈積於光阻層50之間的第一開孔中。內部中心柱52的高度大約為光阻層50厚度的三分之二。再次將光阻層50曝光、顯像、以及蝕刻，而不將該層完全剝離，藉以在第一開孔之上，形成第二開孔或圓柱。第二開孔具有大於接觸墊32寬度之寬度，如圖3a所示。從光阻層50中的第二開孔邊緣至中心柱52之距離小於光阻層50之厚度。阻障層54形成於種子層44與中心柱52之上，以為金屬(Cu)擴散隔離之用。濕潤層56形成於阻障層54之上。
透過網板印刷製程，將傳導性材料電氣沈積於濕潤層56之上，藉以形成焊接層58。焊接材料能夠是任何一種金屬，例如，Sn、Pb、Ni、Au、Ag、Cu、Bi、以及其合 金、或者其他傳導性材料之混合物。在某一實施例中，焊接材料為63%重量百分比的Sn以及37%重量百分比的Pb。在電鍍之後，對焊接層進行重熔，藉以在光阻層50之間形成球體或凸塊64。
在圖3b中，將光阻層50任何一個剩餘部分剝離。蝕刻製程會移除位於焊接凸塊結構的區域外部任何一部份的種子層44、黏合層42、以及阻障層40。藉由將傳導性材料加熱至其熔點之上，第二次對焊接凸塊64進行重熔處理，藉以形成圓球體或者凸塊66，配置於半導體基板34之上。焊接凸塊66電氣接觸著中心柱52、種子層44、以及金屬接觸墊32。
藉由電鍍焊接材料並且之後重熔該焊接材料兩次藉，以形成焊接凸塊而將焊接凸塊形成於內部中心柱52周圍之製程會降低焊接接合點的電阻，並且改善凸塊支撐結構的強度與可靠度。內部中心柱52會以至少焊接凸塊三分之二的高度延伸於焊接凸塊之中。此外，形成於內部中心柱之上的阻障層54與濕潤層56同樣也會增強凸塊支撐結構的強度與可靠度。
覆晶封裝的另一實施例顯示於圖4a。如以上所說明，金屬接觸墊32形成於基板34之上。接觸墊32透過形成於基板34上的傳導層而電氣連接至主動與被動元件。鈍化層36形成於基板34之上，其中的開孔會露出金屬接觸墊32。黏合層40形成於鈍化層36之上，以為接合至阻障層42之用。阻障層42會限制Cu擴散於晶粒的主動區域 之中。種子層44形成於阻障層42之上。種子層44為一種中間傳導層，形成於金屬接觸墊32與焊接凸塊之間。種子層44電氣連接至接觸墊32。
首先將光阻層50塗佈、曝光、顯像、以及蝕刻，藉以形成第一開孔或圓柱，所具有的寬度小於接觸墊32之寬度。光阻層中的第一開孔具有圓柱形式，其內部裝容著光阻材料。藉由無電電鍍或電解電鍍製程，將內部中心柱70沈積於光阻層之間的第一開孔中。由於第一開孔之形成，內部中心柱70具有中空內部的圓柱形狀，如圖4b中所示，其為凸塊76與支撐結構以直線4b－4b所得的上視圖。在另一實施例中，內部中心柱可以是環面形狀的。內部中心柱70的高度大約為光阻層厚度的三分之二。再次將光阻層曝光、顯像、以及蝕刻，而不將該層完全剝離，藉以在第一開孔之上，形成第二開孔或圓柱。第二開孔具有大於接觸墊32寬度之寬度。從光阻層中的第二開孔邊緣至中心柱70之距離小於光阻層之厚度。阻障層72形成於種子層44與中心柱70之上，以為金屬(Cu)擴散隔離之用。濕潤層74形成於阻障層72之上。
藉由在濕潤層72上的無電電鍍、電解電鍍或網版印刷製程，將傳導性材料電氣沈積，藉以形成一焊接層。焊接材料能夠是任何一種金屬，例如，Sn、Pb、Ni、Au、Ag、Cu、Bi、以及其合金、或者其他傳導性材料之混合物。在某一實施例中，焊接材料為63%重量百分比的Sn以及37%重量百分比的Pb。
將光阻層任何一個剩餘部分剝離。蝕刻製程會移除位於焊接凸塊結構的區域外部任何一部份的種子層44、黏合層42、以及阻障層40。藉由將傳導性材料加熱至其熔點之上，對焊接凸塊64進行重熔處理，藉以形成圓球體或者凸塊76，配置於半導體基板34之上。焊接凸塊76電氣接觸著中心柱70、種子層44、以及金屬接觸墊32。
總之，藉由電鍍焊接材料並且之後重熔該焊接材料一次或者多次藉以形成焊接凸塊而將焊接凸塊形成於內部中心柱52周圍，其製程會降低焊接接合點的電阻，並且改善凸塊支撐結構的強度與可靠度。內部中心柱會以至少焊接凸塊三分之二的高度而延伸於焊接凸塊之中。此外，形成於內部中心柱之上的阻障層與濕潤層同樣也會增強凸塊支撐結構的強度與可靠度。
儘管已經詳細闡述了本發明其中之一或更多之實施例，然而熟知該項技術者將會察知可以實施這些實施例的修改與變體，而不違反以下申請專利範圍中所提及的本發明之範疇。
10‧‧‧覆晶封裝
12‧‧‧主動區域
14‧‧‧晶粒
16‧‧‧載體基板
20‧‧‧焊接凸塊結構
22‧‧‧焊接凸塊/球體
24‧‧‧凸塊墊
26‧‧‧接觸墊
32‧‧‧(金屬)接觸墊
34‧‧‧基板
36‧‧‧第一鈍化層
38‧‧‧第二鈍化層
40‧‧‧黏合層
42‧‧‧阻障層
44‧‧‧種子層
50‧‧‧光阻層
52‧‧‧內部中心柱
54‧‧‧阻障層
56‧‧‧濕潤層
58‧‧‧焊接層
60‧‧‧焊接圓球體或者凸塊
64‧‧‧焊接球體或者凸塊
66‧‧‧焊接圓球體或者凸塊
70‧‧‧內部中心柱
72‧‧‧阻障層
74‧‧‧濕潤層
76‧‧‧凸塊
圖1為一種具有焊接凸塊之覆晶半導體封裝，其焊接凸塊則是提供晶粒的主動區域與晶片載體基板之間的電氣相互連接；圖2a－2d闡述焊接凸塊中與支撐結構的內部中心柱之形成； 圖3a－3d闡述使用網版印刷焊接的焊接凸塊內部中心柱之形成；以及圖4a－4b闡述焊接凸塊與支撐結構的中空圓柱形內部中心柱之形成。
32‧‧‧(金屬)接觸墊
34‧‧‧基板
36‧‧‧第一鈍化層
40‧‧‧黏合層
42‧‧‧阻障層
44‧‧‧種子層
52‧‧‧內部中心柱
54‧‧‧阻障層
56‧‧‧濕潤層
60‧‧‧焊接圓球體或者凸塊

Claims (21)

  1. 一種覆晶半導體封裝，包含：一基板，其具有形成於其上的複數個主動或被動元件；一接觸墊，其以電氣接觸於複數個主動或被動元件而形成於基板上；一傳導層，其以電氣接觸於接觸墊而配置於基板之上；一內部中心柱，其包含一中空內部且形成於傳導層之上；一第一阻障層與濕潤層，其形成於內部中心柱之上以及在該內部中心柱的該中空內部之內；以及一凸塊，其藉由電鍍凸塊材料與重熔該凸塊材料，以形成該凸塊於第一阻障層與濕潤層周圍以及該內部中心柱的該中空內部之內，內部中心柱以凸塊至少三分之二的高度而延伸於凸塊之中。
  2. 如申請專利範圍第1項之覆晶半導體封裝，其中的內部中心柱由銅、鎳、或者其他金屬所製成。
  3. 如申請專利範圍第1項之覆晶半導體封裝，進一步包含：一鈍化層，其形成於基板之上；一第二阻障層，其形成於鈍化層之上；以及一黏合層，其形成於第二阻障層之上，並且接觸著傳導層。
  4. 如申請專利範圍第1項之覆晶半導體封裝，其中的內部中心柱具有一從矩形、圓柱形以及環面形的群組中所選 擇的形狀因數。
  5. 一種半導體封裝，包含：一基板，其具有形成於其上的複數個主動元件；一接觸墊，其以電氣接觸於複數個主動元件而形成於基板上；一中間傳導層，其以電氣接觸於接觸墊而配置於基板之上；一內部中心柱，其形成於中間傳導層之上；一第一阻障層與濕潤層，其形成於內部中心柱之上；以及一焊接凸塊，其藉由電鍍焊接材料與重熔該焊接材料多次，藉以形成焊接凸塊於第一阻障層與濕潤層以及內部中心柱周圍。
  6. 如申請專利範圍第5項之半導體封裝，其中的內部中心柱以焊接凸塊至少三分之二的高度而延伸於焊接凸塊之中。
  7. 如申請專利範圍第5項之半導體封裝，其中的內部中心柱由銅、鎳、或者其他金屬所製成。
  8. 如申請專利範圍第5項之半導體封裝，其中的第一阻障層形成於內部中心柱之上，而濕潤層則形成於該阻障層之上。
  9. 如申請專利範圍第5項之半導體封裝，進一步包含：一鈍化層，其形成於基板之上；一第二阻障層，其形成於鈍化層之上；以及 一黏合層，其形成於第二阻障層之上，並且接觸著中間傳導層。
  10. 如申請專利範圍第5項之半導體封裝，進一步包含：一第一孔穴，其形成於焊接凸塊以及中間傳導層之間，以提供電氣連接之用；以及一第二孔穴，其形成於中間傳導層以及接觸墊之間，以為提供電氣連接之用。
  11. 如申請專利範圍第5項之半導體封裝，其中的內部中心柱具有一從矩形、圓柱形、環面形、以及中空圓柱形的群組中所選擇的形狀因數。
  12. 一種半導體封裝，包含：一基板；一接觸墊，其形成於基板上；一內部中心柱，其包含一中空內部且形成於該接觸墊之上；以及一凸塊，其藉由電鍍凸塊材料與重熔該凸塊材料，以形成凸塊於內部中心柱周圍以及該內部中心柱的該中空內部之內。
  13. 如申請專利範圍第12項之半導體封裝，進一步包含一形成於內部中心柱之上的第一阻障層與濕潤層。
  14. 如申請專利範圍第12項之半導體封裝，進一步包含一以電氣接觸著接觸墊而配置於基板之上的傳導層。
  15. 如申請專利範圍第12項之半導體封裝，進一步包含： 一鈍化層，其形成於基板之上；一第二阻障層，其形成於鈍化層之上；以及一黏合層，其形成於第二阻障層之上。
  16. 一種製作半導體封裝之方法，包含：提供一具有形成於其上的複數個主動元件之基板；以電氣接觸於複數個主動元件，將一接觸墊形成於基板之上；將一中間傳導層以電氣接觸於接觸墊而形成於基板之上；將一內部中心柱形成於中間傳導層周圍，其係藉由(a)形成一光阻層，(b)在光阻層中形成一第一開孔，(c)在第一開孔中電鍍內部中心柱；以及將凸塊形成於內部中心柱周圍，其係藉由(a)於第一開孔之上，在光阻層中形成一第二開孔，其第二開孔較大於第一開孔，(b)在第二開孔中電鍍凸塊材料，(c)移除光阻層，以及(d)重熔凸塊材料，藉以形成凸塊。
  17. 如申請專利範圍第16項之方法，進一步包含一形成於內部中心柱之上的第一阻障層與濕潤層。
  18. 如申請專利範圍第16項之方法，其中的內部中心柱由銅、鎳、或者其他金屬所製成。
  19. 如申請專利範圍第16項之方法，其中的內部中心柱 具有一從矩形、圓柱形、環面形、以及中空圓柱形的群組中所選擇的形狀因數。
  20. 如申請專利範圍第16項之方法，進一步包含：形成一第一阻障層於內部中心柱之上；以及形成一濕潤層於第一阻障層之上。
  21. 如申請專利範圍第16項之方法，進一步包含：形成一濕潤層於內部中心柱之上；以及形成一第一阻障層於濕潤層之上。
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Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US9598772B2 (en) * 2010-04-16 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating bump structure without UBM undercut
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8970036B2 (en) * 2010-09-28 2015-03-03 Georgia Tech Research Corporation Stress relieving second level interconnect structures and methods of making the same
US8227333B2 (en) * 2010-11-17 2012-07-24 International Business Machines Corporation Ni plating of a BLM edge for Pb-free C4 undercut control
CN102487049B (zh) * 2010-12-02 2014-10-15 矽品精密工业股份有限公司 半导体基板及其制法
US8669137B2 (en) * 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
FR2977383A1 (fr) * 2011-06-30 2013-01-04 St Microelectronics Grenoble 2 Plot de reception d'un fil de cuivre
US10833033B2 (en) * 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US9905524B2 (en) 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8558229B2 (en) * 2011-12-07 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation layer for packaged chip
US9230932B2 (en) * 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
TWI497669B (zh) * 2012-03-22 2015-08-21 矽品精密工業股份有限公司 形成於半導體基板上之導電凸塊及其製法
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
DE102013103581B4 (de) 2012-05-30 2022-01-13 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauteil und entsprechendes Herstellungsverfahren
US8772946B2 (en) 2012-06-08 2014-07-08 Invensas Corporation Reduced stress TSV and interposer structures
US9355978B2 (en) * 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
CN103579149B (zh) * 2012-08-01 2016-08-03 颀邦科技股份有限公司 半导体结构及其制造工艺
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
EP2711977B1 (en) 2012-09-19 2018-06-13 ATOTECH Deutschland GmbH Manufacture of coated copper pillars
CN102931097B (zh) * 2012-11-08 2016-11-23 南通富士通微电子股份有限公司 半导体封装结构的形成方法
US9589815B2 (en) * 2012-11-08 2017-03-07 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor IC packaging methods and structures
CN102945836B (zh) * 2012-11-08 2016-03-16 南通富士通微电子股份有限公司 半导体封装结构
US9293338B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor packaging structure and method
US9620468B2 (en) * 2012-11-08 2017-04-11 Tongfu Microelectronics Co., Ltd. Semiconductor packaging structure and method for forming the same
JP2014116367A (ja) * 2012-12-06 2014-06-26 Fujitsu Ltd 電子部品、電子装置の製造方法及び電子装置
TWI488274B (zh) * 2012-12-06 2015-06-11 Powertech Technology Inc 中空柱狀凸塊製程
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
JP6150534B2 (ja) * 2013-01-25 2017-06-21 キヤノン株式会社 半導体チップの製造方法
US9773724B2 (en) 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9196529B2 (en) 2013-09-27 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor devices
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
JP6282454B2 (ja) * 2013-12-10 2018-02-21 新光電気工業株式会社 半導体パッケージの製造方法
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9343420B2 (en) 2014-02-14 2016-05-17 Globalfoundries Inc. Universal solder joints for 3D packaging
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
KR102307062B1 (ko) * 2014-11-10 2021-10-05 삼성전자주식회사 반도체 소자, 반도체 소자 패키지 및 조명 장치
KR20160066972A (ko) * 2014-12-03 2016-06-13 삼성전자주식회사 반도체 발광 소자 및 이를 구비한 반도체 발광 장치
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US20160315040A1 (en) * 2015-04-23 2016-10-27 Mk Electron Co., Ltd. Core for reverse reflow, semiconductor package, and method of fabricating semiconductor package
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
CN105006437B (zh) * 2015-07-28 2018-06-26 江阴长电先进封装有限公司 一种高密度凸块结构的制造方法
US9806052B2 (en) * 2015-09-15 2017-10-31 Qualcomm Incorporated Semiconductor package interconnect
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9793232B1 (en) * 2016-01-05 2017-10-17 International Business Machines Corporation All intermetallic compound with stand off feature and method to make
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
JP2019087693A (ja) * 2017-11-09 2019-06-06 株式会社デンソー 半導体装置
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
JP2020047775A (ja) * 2018-09-19 2020-03-26 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置
EP3703129B1 (en) * 2019-02-28 2021-10-20 Detection Technology Oy Radiation sensor element and corresponding method
US11824025B2 (en) * 2021-08-20 2023-11-21 Micron Technology, Inc. Apparatus including integrated pads and methods of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020068425A1 (en) * 2000-12-01 2002-06-06 Taiwan Semiconductor Manufacturing Co., Ltd Method for bumping and backlapping a semiconductor wafer
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JP3008768B2 (ja) 1994-01-11 2000-02-14 松下電器産業株式会社 バンプの形成方法
JP2751912B2 (ja) * 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
JPH10125685A (ja) 1996-10-16 1998-05-15 Casio Comput Co Ltd 突起電極およびその形成方法
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
JP3420203B2 (ja) * 2000-10-27 2003-06-23 Ｎｅｃエレクトロニクス株式会社 ハンダバンプの形成方法
US20040099441A1 (en) * 2001-04-24 2004-05-27 Akira Ichiryu Printed circuit board,its manufacturing method and csp manufacturing method
US6638638B2 (en) * 2001-09-18 2003-10-28 Samsung Electronics Co., Ltd. Hollow solder structure having improved reliability and method of manufacturing same
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
JP3863171B2 (ja) * 2003-01-30 2006-12-27 株式会社フジクラ 半導体圧力センサ及びその製造方法
TW589727B (en) 2003-06-30 2004-06-01 Advanced Semiconductor Eng Bumping structure and fabrication process thereof
US7276801B2 (en) * 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
US6927493B2 (en) * 2003-10-03 2005-08-09 Texas Instruments Incorporated Sealing and protecting integrated circuit bonding pads
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
KR100568006B1 (ko) 2003-12-12 2006-04-07 삼성전자주식회사 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
JP4327657B2 (ja) * 2004-05-20 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
TWI262347B (en) * 2004-08-02 2006-09-21 Hannstar Display Corp Electrical conducting structure and liquid crystal display device comprising the same
JP4050732B2 (ja) * 2004-08-30 2008-02-20 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3918842B2 (ja) * 2004-09-03 2007-05-23 ヤマハ株式会社 半導体素子及びそれを備えたワイヤボンディング・チップサイズ・パッケージ
TWI259572B (en) * 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
US7622309B2 (en) * 2005-06-28 2009-11-24 Freescale Semiconductor, Inc. Mechanical integrity evaluation of low-k devices with bump shear
US20070045840A1 (en) * 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
WO2007085988A1 (en) * 2006-01-24 2007-08-02 Nxp B.V. Stress buffering package for a semiconductor component
KR101328551B1 (ko) * 2006-10-02 2013-11-13 삼성전자주식회사 반도체 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020068425A1 (en) * 2000-12-01 2002-06-06 Taiwan Semiconductor Manufacturing Co., Ltd Method for bumping and backlapping a semiconductor wafer
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface

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