TWI463573B - 半導體裝置及使用犧牲載體形成該裝置之方法 - Google Patents

半導體裝置及使用犧牲載體形成該裝置之方法 Download PDF

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Publication number
TWI463573B
TWI463573B TW097140574A TW97140574A TWI463573B TW I463573 B TWI463573 B TW I463573B TW 097140574 A TW097140574 A TW 097140574A TW 97140574 A TW97140574 A TW 97140574A TW I463573 B TWI463573 B TW I463573B
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Taiwan
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conductive layer
forming
layer
insulating layer
conductive
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TW097140574A
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English (en)
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TW200929388A (en
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Il Kwon Shim
Yaojian Lin
Seng Guan Chow
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Stats Chippac Ltd
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Description

半導體裝置及使用犧牲載體形成該裝置之方法
本發明基本上是關於半導體裝置，特別是一種半導體裝置及使用犧牲載體形成該裝置之方法。
半導體裝置發現於娛樂、通信、網路、電腦及家用市場領域內之許多產品之中。半導體裝置亦發現於軍事、航空、汽車、工業控制器及辦公室設備中。此半導體裝置執行每一上述應用所須之各種電性功能。
半導體裝置之製造需要具有複數個晶粒之晶圓形成。每一半導體晶粒包含數百個或數千個電晶體以及執行各種電性功能之其他主動式和被動式裝置。就一給定晶圓而言，該晶圓上的每一晶粒通常是執行相同之電性功能。前端製造通常是指晶圓上半導體裝置之形成。該完成之晶圓具有一主動側，該主動側包含上述之電晶體及其他主動式和被動式元件。後端製造是指對該完成之晶圓切割或單一化成個別之晶粒，而後封裝該晶粒作為結構之支撐與環境之隔絕。
半導體製造的目標之一是以較低成本生產一適合於更快速、更可靠、更小型及更高密度積體電路(IC)之封裝。覆晶封裝或晶圓級晶片尺寸封裝(WLCSP)理論上適於要求高速、高密度及更多接腳數之IC。覆晶式封裝包含架置一朝下面對著一晶片載體基板或印刷電路板(PCB)之晶粒的主動側。晶粒上之主動裝置和載體基板上之導電軌跡間 之電性和機械互連是透過一包含大量導電焊接凸塊或球體之焊接凸塊結構達成。此等焊錫凸塊是由施加至焊接材料之回焊製程所形成，該焊接材料是沉積於配置在半導體基板上之接觸墊上。此焊接凸塊接著焊接至載體基板。覆晶半導體封裝提供從晶粒上之主動裝置到載體基板之一極短電性傳導路徑，以減少信號遞衍、較低之電容及達成整體上較佳之電路效能。
在許多應用中，其需要疊堆晶圓級晶片尺寸封裝。其必須提供適當之電性互連以完整元件整合。此互連通常包括重分布層(RDL)及其他導線和軌跡之形成。由於蝕刻處理，這些金屬線具有有限的寬度及線間距。將晶粒貼附至晶圓載體作為後續之封裝及進一步之RDL構建處理時，其互連架構之形成需要高度之對齊準確性。
當滿足前述互連對齊之需求時，需要形成用於晶圓級晶片尺寸封裝之互連架構。
在某一實施例中，本發明是一種製造半導體裝置之方法，其包含如下之步驟：提供一犧牲載體、於該犧牲載體上形成複數個接觸墊、固定第一半導體晶粒以電連接至該接觸墊、以模封化合物封裝該第一半導體晶粒、移除該犧牲載體、於該模封化合物上形成第一導電層並電接觸該接觸墊、於該第一導電層上形成第一絕緣層、移除部份該第一絕緣層以露出該第一導電層、沉積焊接材料並電接觸該第一導電層以及回焊該焊接材料以形成一焊接凸塊。
在另一實施例中，本發明是一種製造半導體裝置之方法，其包含如下之步驟：提供一犧牲載體、於該犧牲載體上形成複數個接觸墊、固定第一半導體晶粒以電連接至該接觸墊、以模封化合物封裝該第一半導體晶粒、於該模封混合物上形成第一導電層並電接觸該接觸墊、於該第一導電層上形成第一絕緣層以及移除部份該第一絕緣層以露出該第一導電層。
在另一實施例中，本發明是一種製造半導體封裝之方法，其包含如下之步驟：提供一犧牲載體、於該犧牲載體上形成複數個接觸墊、固定第一半導體晶粒以電連接至該接觸墊、以模封化合物封裝該第一半導體晶粒以及於該模封化合物上形成一互連架構並電接觸該接觸墊。
以下描述配合圖式以一或多個實施例闡述本發明，其中相同之數字編號代表相同或類似之元素。雖然其是透過達成本發明目的之最佳模式來闡述本發明，然習於此技藝之人士了解，其意指涵蓋由後附申請專利範圍所界定之本發明之精神和範疇內所包含之替代、修改及等效物，以及以下揭示和圖式所支持之等效物。
半導體裝置之製造需要一包含複數個晶粒之晶圓形成。每一晶粒包含數百個或數千個電晶體以及執行一或多個電性功能之其他主動式和被動式裝置。就一給定晶圓而言，該晶圓上的每一晶粒通常是執行相同之電性功能。前端製造通常是指晶圓上半導體裝置之形成。該完成之晶圓 具有一主動側，該主動側包含上述之電晶體及其他主動式和被動式組件。後端製造是指對該完成之晶圓切割或單一化成個別之晶粒，而後封裝該晶粒作為結構上之支撐及/或環境之隔絕。
半導體晶圓一般包含一具有半導體裝置配置其上之主動表面，以及一以諸如矽之大塊半導體材料形成之背側表面。主動側表面包含複數個半導體晶粒。該主動表面是由各種半導體製程所形成，包含層疊化、圖案化、摻雜以及熱處理。在層疊化製程中，半導體材料藉由包括熱氧化、氮化、化學氣相沉積、蒸鍍以及濺鍍等方法成長或沉積於基板之上。光學微影術包含表面區域之遮罩並蝕刻不需要之材料以形成特定之結構。摻雜製程藉由熱擴散或離子佈植注入濃縮之掺雜材料。
覆晶半導體封裝和晶圓級封裝(WLP)通常是使用於要求高速度、高密度及更多接腳數之積體電路(IC)。覆晶式半導體裝置10包含架置一朝下面對著一晶片載體基板或印刷電路板(PCB)16之晶粒14的主動區域12，如圖1所示。取決於晶粒之電設計，主動區域12包含主動式及被動式裝置、導電層以及介電層。類比電路可以藉由在主動區域12內形成之一或多個被動式裝置之組合而建立，且可以電性互連。舉例而言，一類比電路可以包含一或多個電感、電容及電阻形成於主動區域12內。其電性和機械互連是透過一包含大量個別導電焊接凸塊或球體22之焊接凸塊結構20達成。焊接凸塊是形成於凸塊墊或互連點24上， 其配置於主動區域12。凸塊墊24經由主動區域12內之導電軌跡連接至主動電路。焊接凸塊22在電性上及機械上均藉由一焊接回焊製程連接至載體基板16上之接觸墊或互連點26。覆晶半導體裝置提供從晶粒14之主動裝置到載體基板16之一極短電性傳導路徑，以減少信號遞衍、較低之電容及達成整體上較佳之電路效能。
依據半導體裝置10形成半導體封裝之進一步細節顯示於圖2a至2f。在圖2a中，其顯示一虛擬或犧牲金屬載體30。金屬載體30是由銅、鋁或其他剛硬材料所製成。載體30亦可以是具彈性之捲帶。一光阻層32沉積於金屬載體30上。藉由一光圖案化製程形成複數個開孔以界定選擇性鍍覆之區域。接觸墊34接著選擇性地鍍覆於光阻所界定之開孔區域。接觸墊34可以由銅、錫、鎳、金或銀製成。金屬載體30是做為一支持構件以及用於電鍍製程之鍍覆電流路徑以在金屬載體上形成可濕性的金屬接觸墊34。部分或全部之光阻32藉由一抗蝕清除劑移除。或者，其可以遺留一層光阻32於接觸墊34之間。
在圖2b之中，半導體晶粒36及40分別透過焊接凸塊38及42固定於金屬載體30上之接觸墊34。或者，分離之組件或其他半導體封裝可以固定於接觸墊34上。一選擇性的底部填充材料可以形成於半導體晶粒36及40下方。一模封化合物44形成於半導體晶粒36及40周圍以封裝該晶粒、互連以及接觸墊。金屬載體藉由一蝕刻製程移除以顯露出接觸墊34，如圖2c所示。
在圖2d中，半導體晶粒被翻轉以使得接觸墊34面朝上。一選擇性的製程載體50利用黏著層48固定於該半導體晶粒之背側以支撐該封裝。上述之黏著層可使用以熱能或紫外線(UV)可移除之暫時性黏著劑製成，其通常具有一至少150℃之玻璃轉移溫度(Tg)。導電層46使用一諸如鈦之黏著層濺鍍及圖案化或選擇性地鍍覆於化合物材料44之一表面上。導電層46是由銅、鋁、金或其合金製成。導電層46依據半導體晶粒36及40之電性功能和互連需求電連接至接觸墊34。
在圖2e之中，一絕緣層51形成於模封化合物44及導電層46上。絕緣層51可以由單層或多層感光聚合物材料或其他具有低固化溫度，例如小於200℃，之介電材料所構成。部分絕緣層51是藉由諸如光圖案化或化學蝕刻之蝕刻製程移除，以形成開孔並顯露出導電層46。一導電層52形成於絕緣層51上以電接觸導電層46。一絕緣層54形成於導電層52及絕緣層51上。絕緣層54可以由單層或多層感光聚合物材料或其他具有低固化溫度，例如小於200℃，之介電材料所構成。部分絕緣層54是藉由諸如光圖案化或化學蝕刻之蝕刻製程移除，以形成開孔並顯露出導電層52。導電層46與52以及絕緣層51與54構建一部分連結架構，該互連架構將電性信號繞送於半導體晶粒36與40之間，也是封裝之外部。額外之絕緣層及導電層可以使用於此互連架構之中。
在圖2f中，一電性傳導焊接材料經由一蒸鍍、電鍍、 無極鍍覆、球滴法或網印製程以沉積於導電層52上。此焊接材料可以是任何金屬或電性傳導材料，例如，錫、鉛、鎳、金、銀、銅、鉍及其合金。焊接材料藉由加熱導電材料至其熔點上，以回焊形成圓球或凸塊56。在某些應用之中，焊接凸塊56被二次回焊以增進對導電層52之電接觸。一額外之凸塊下金屬化層可以選擇性地形成於焊接凸塊56下方。此互連可以是焊接凸塊或連結導線。
製程載體50及黏著層48被移除。或者，製程載體50及黏著層48可以維持附著於半導體裝置上並作為用於散熱之熱下降或電磁干擾(EMI)之屏障。
圖3說明圖2a至2f之半導體裝置，其中半導體裝置58電連接至焊接凸塊56。此外，導線連結60電連接至導電層52。連結導線62自導線連結60延伸至其他半導體裝置或外部電連接。焊接凸塊56及連結導線62提供半導體晶粒36及40之電性互連。
製造半導體裝置之初始階段之另一實施例顯示於圖4a至4c。在圖4a中，其顯示一虛擬或犧牲金屬載體70。金屬載體或箔片70可以是圓形或長方形且由銅或鋁構成。一製程載體72經由黏著層74固定至載體70。一光阻層76沉積於金屬載體70上。其藉由一光圖案化製程形成複數個開孔以界定選擇性鍍覆之區域。接觸墊78接著選擇性地鍍覆於光阻所界定之開孔區域。接觸墊78可以由銅、錫、鎳、金或銀所構成。金屬載體70是做為一支持構件以及用於電鍍製程之鍍覆電流路徑以在金屬載體上形成可濕性的金屬接 觸墊78。光阻76是藉由一抗蝕清除劑移除。
在圖4b中，半導體晶粒80及84分別透過焊接凸塊82及86固定於金屬載體70上之接觸墊78。或者，分離之組件或其他半導體封裝可以附著於接觸墊78上。一選擇性的底部填充材料可以形成於半導體晶粒80及84下方。一模封化合物88形成於半導體晶粒80及84周圍以封裝該晶粒、互連以及接觸墊。製程載體72及黏著層74先被移除，接著金屬載體70藉由一蝕刻製程移除以顯露出接觸墊78，如圖4c所示。
接著利用圖2d至2f所述之步驟形成互連架構。更具體言之，一類似46之第一導電層使用一諸如鈦之黏著層濺鍍及圖案化或選擇性地鍍覆於模封化合物88之一表面上。此第一導電層依據半導體晶粒80及84之電性功能和互連需求電連接至接觸墊78。一類似51之第一絕緣層形成於模封化合物88及第一導電層之上。第一絕緣層可以由單層或多層感光聚合物材料或其他具有低固化溫度，例如小於200℃，之介電材料所構成。部分第一絕緣層是藉由一蝕刻製程移除，以形成開孔並顯露出第一導電層。一類似52之第二導電層形成於第一絕緣層上以電接觸第一導電層。一類似54之第二絕緣層形成於第一導電層及第一絕緣層上。第二絕緣層可以由單層或多層感光聚合物材料或其他具有低固化溫度，例如小於200℃，之介電材料所構成。部分第二絕緣層是藉由一蝕刻製程移除，以形成開孔並顯露出第二導電層。類似56之焊接凸塊可以形成於露出之第二導電 層上。第一和第二導電層以及第一和第二絕緣層構建出部分之互連架構，其將電性信號繞送於半導體晶粒80與84之間，並也是封裝之外部。額外之絕緣層及導電層可以使用於此互連架構中。
圖5說明此半導體裝置之某一實施例。其利用如圖2a所述之虛擬或犧牲金屬載體以形成接觸墊94。半導體晶粒90及98分別透過導線連結96及100固定於金屬載體上之接觸墊94。一模封化合物101形成於半導體晶粒90及98周圍以封裝該晶粒、導線連結以及接觸墊，類似圖2b。金屬載體藉由一蝕刻製程移除以顯露出接觸墊94，與圖2c所描述之方式相同。
一製程載體利用一黏著層被附著於半導體晶粒之背側以支撐該封裝。導電層102使用一諸如鈦之黏著層被選擇性地鍍覆於模封化合物101之一表面上。導電層102依據半導體晶粒90及98之電性功能和互連需求電連接至接觸墊94。
絕緣層103形成於模封化合物101及導電層102之上。絕緣層103可以由具有介電性質之材料所構成。部分絕緣層103是藉由一蝕刻製程移除，以形成開孔並顯露出導電層102。一導電層104形成於絕緣層103上並以電接觸導電層102。一絕緣層106形成於導電層104及絕緣層103上。絕緣層106可以由具有介電性質之材料所構成。部分絕緣層106是藉由一蝕刻製程移除，以形成開孔並顯露出導電層104。導電層104與106以及絕緣層103與106構建出部 分之互連架構，其將電性信號繞送於半導體晶粒90與98之間，並也是封裝結構之外部。額外之絕緣層及導電層可以使用於此互連架構中。
一電性傳導焊接材料經由一蒸鍍、電鍍、無極鍍覆、球滴法或網印製程以沉積於導電層104上。此焊接材料可以是任何金屬或電性傳導材料，例如，錫、鉛、鎳、金、銀、銅、鉍及其合金。焊接材料藉由加熱導電材料至其熔點上，以回焊形成圓球或凸塊108。在某些應用中，焊接凸塊108被二次回焊以增進對導電層104之電接觸。一額外之凸塊下金屬化層可以選擇性地形成於焊接凸塊108下方。此互連可以是焊接凸塊或連結導線。
圖6a至6b利用一前側及背側製程載體說明此半導體裝置之某一實施例。在圖6a中，其利用如圖2a所述之虛擬或犧牲金屬載體以形成接觸墊124。半導體晶粒120及126分別透過焊接凸塊122及128固定於金屬載體上之接觸墊124。一模封化合物130形成於半導體晶粒120及126周圍以封裝該晶粒、互連以及接觸墊，類似圖2b。該金屬載體藉由一蝕刻製程移除以顯露出接觸墊124，與圖2c所描述之方式相同。
一製程載體利用一黏著層附著於半導體晶粒之背側以支撐該封裝。導電層136使用一諸如鈦之黏著層選擇性地鍍覆於模封化合物130之一表面上。導電層136依據半導體晶粒120及126之電性功能和互連需求電連接至接觸墊124。
絕緣層138形成於模封化合物130及導電層136上。絕緣層138可以由具有介電性質之材料所構成。部分絕緣層138是藉由一蝕刻製程移除，以形成開孔並顯露出導電層136。一導電層140形成於絕緣層138上以電接觸導電層136。一絕緣層142形成於導電層140及絕緣層138上。絕緣層142可以由具有介電性質之材料所構成。部分絕緣層142是藉由一蝕刻製程移除，以形成開孔並顯露出導電層140。導電層136與140以及絕緣層138與142構建部分之前側互連架構，該互連架構將電性信號繞送於半導體晶粒120與126之間，並也是封裝之外部。額外之絕緣層及導電層可以使用於此前側互連架構中。
一前側製程載體146利用黏著層144固定至導電層140及絕緣層142。黏著層144可使用以熱能或紫外線可移除之暫時性黏著劑製成，其通常具有一至少150℃之玻璃轉移溫度(Tg)。前側製程載體可以是一彈性捲帶或剛硬之材料。背側製程載體被移除。其利用雷射鑚孔或深度反應離子蝕刻(DRIE)經由模封化合物130形成穿孔。此穿孔使接觸墊124顯露出來。導電材料148沉積於穿孔中並電連接至接觸墊124。絕緣層150形成於導電層148及模封化合物130上。絕緣層150可以由具有介電性質之材料所構成。部分絕緣層150是藉由一蝕刻製程移除，以形成開孔並顯露出導電層148。導電層148以及絕緣層150構建出部分之背側連結架構，其將電性信號繞送於半導體晶粒120與126之間，並也是封裝之外部。額外之絕緣層及導電層可以使 用於此背側互連架構之中。
在圖6b中，一電性傳導焊接材料經由一蒸鍍、電鍍、無極鍍覆、球滴法或網印製程以沉積於導電層140上。此焊接材料可以是任何金屬或電性傳導材料，例如，錫、鉛、鎳、金、銀、銅、鉍及其合金。焊接材料藉由加熱導電材料至其熔點上，以回焊形成圓球或凸塊152。在某些應用中，焊接凸塊152二次回焊以增進對導電層140之電接觸。一額外之凸塊下金屬化層可以選擇性地形成於焊接凸塊152下方。對於背側互連，焊接凸塊或導線連結形成於導電層148或最外側疊層上。
圖7中之半導體裝置遵循圖6a至6b所述之類似架構，除了金屬柱狀物154是以接觸墊124做為蝕刻遮罩並藉由選擇性蝕刻而形成。柱狀物154是由銅、鋁或其合金所構成。由於此架高之互連架構，金屬柱狀物154促進半導體晶粒120及126下方之模封底部填充材料沉積。因為穿孔深度可以被減少，金屬柱狀物154更藉由雷射鑽孔或DRIE製程促進穿孔之形成。半導體裝置藉此較高之互連架構承受較低之熱應力或熱應變。
圖8顯示圖7之半導體裝置，其接觸墊124及半導體晶粒120藉由金屬柱狀物154架高。半導體晶粒158以晶粒貼附黏著劑160固定至絕緣層138，並以導線連結162電連接至接觸墊124及金屬柱狀物154。上述之晶粒貼附黏著劑160可以用環氧樹脂式或薄膜式黏著劑製成。
在圖9中，圖6b之半導體裝置具有底部填充材料164。 此底部填充材料可以由具有適當之流變及介電特性之樹脂所構成。
在圖10中，圖6b之半導體裝置具有實際固定並電連結至焊接凸塊152之半導體晶粒166。半導體晶粒168以晶粒貼附黏著劑170實際固定至絕緣層142，並以導線連結172電連接至導電層140。模封化合物174應用於半導體晶粒166和168以及相關之互連架構上。
圖11顯示圖2f之半導體裝置，具有製程載體176及黏著層178作為散熱之熱下降或EMI屏障。
圖12顯示圖2f之半導體裝置，具有一層光阻180保留於接觸墊124之間。
總結，上述之半導體裝置利用銅質薄板做為虛擬或犧牲載體。複數個可濕性接觸墊圖案化於該犧牲載體之上。該個別半導體晶粒固定至該犧牲載體並電連接至該接觸墊。該半導體晶粒及接觸墊被以一模封化合物封裝。移除犧牲載體以顯露出金屬墊。一互連構建層形成於接觸墊上。可濕性接觸墊選擇性地鍍覆於犧牲金屬載體上，以依據半導體晶粒之電性功能對用於電性互連之連結墊位置提供高度精確之對齊。藉由在犧牲載體上形成接觸墊，對於後續形成之必需互連架構可以達到精確的配置及對齊。因此，該半導體封裝具有較大之互連密度以及對個別軌跡之較低線距。
雖然本發明已以一個或多個實施例之方式詳細說明，但習於此技藝者應能理解，可以在未脫離本發明之範疇下 達成此等實施例之修改及調整，該範疇界定於以下之申請專利範圍。
10‧‧‧半導體裝置
12‧‧‧主動區域
14‧‧‧半導體晶粒
16‧‧‧晶片載體基板/印刷電路板
20‧‧‧焊接凸塊結構
22‧‧‧焊接凸塊/錫球
24‧‧‧凸塊墊
26‧‧‧載體基板接觸墊
30‧‧‧犧牲金屬載體
32‧‧‧光阻層
34‧‧‧接觸墊
36/40‧‧‧半導體晶粒
38/42‧‧‧焊接凸塊
44‧‧‧模封化合物
46/52‧‧‧導電層
48‧‧‧黏著層
50‧‧‧製程載體
51/54‧‧‧絕緣層
56‧‧‧焊接凸塊
58‧‧‧半導體裝置
60‧‧‧導線連結
62‧‧‧連結導線
70‧‧‧犧牲金屬載體
72‧‧‧製程載體
74‧‧‧黏著層
76‧‧‧光阻層
78‧‧‧接觸墊
80/84‧‧‧半導體晶粒
82/86‧‧‧焊接凸塊
88‧‧‧模封化合物
90/98‧‧‧半導體晶粒
94‧‧‧接觸墊
96/100‧‧‧導線連結
101‧‧‧模封化合物
102/104‧‧‧導電層
103/106‧‧‧絕緣層
108‧‧‧焊接凸塊
120/126‧‧‧半導體晶粒
122/128‧‧‧焊接凸塊
124‧‧‧接觸墊
130‧‧‧模封化合物
136/140/148‧‧‧導電層
138/142/150‧‧‧絕緣層
144‧‧‧黏著層
146‧‧‧製程載體
152‧‧‧焊接凸塊
154‧‧‧柱狀物
158‧‧‧半導體晶粒
160‧‧‧晶粒貼附黏著劑
162‧‧‧導線連結
164‧‧‧底部填充材料
166/168‧‧‧半導體晶粒
170‧‧‧晶粒貼附黏著劑
172‧‧‧導線連結
174‧‧‧模封化合物
176‧‧‧製程載體
178‧‧‧黏著層
180‧‧‧光阻
圖1是一覆晶半導體裝置，其具有在晶粒之一主動區域及一晶片載體基板間提供電性互連之焊接凸塊；圖2a至2f說明使用一犧牲載體之半導體封裝之形成；圖3說明具有焊接凸塊及導線連結之半導體封裝；圖4a至4c說明利用一犧牲載體之半導體封裝之另一種形成；圖5說明具有互連至半導體晶粒之導線連結之半導體封裝；圖6a至6b說明具有前側及背側互連之半導體封裝；圖7說明在接觸墊下具有柱狀物之半導體封裝；圖8說明具有連結至晶粒之焊接凸塊及導線連結之半導體封裝；圖9說明在半導體晶粒下具有底部填充材料之半導體封裝；圖10說明具有固定至前側互連之次要晶粒之半導體封裝；圖11說明具有完整無缺之殘留犧牲載體作為散熱之半導體封裝；以及圖12說明其接觸墊間完整無缺之光阻劑殘留之半導體封裝。
34‧‧‧接觸墊
36/40‧‧‧半導體晶粒
38/42‧‧‧焊接凸塊
44‧‧‧模封化合物
46/52‧‧‧導電層
51/54‧‧‧絕緣層
56‧‧‧凸塊

Claims (21)

  1. 一種製造半導體裝置之方法，包含：提供一犧牲載體；於該犧牲載體上形成複數個選擇性鍍覆的接觸墊，其使用該犧牲載體作為電鍍電流路徑以形成該選擇性鍍覆的接觸墊；直接地固定第一半導體晶粒至包括複數個凸塊的該選擇性鍍覆的接觸墊，以對齊與該選擇性鍍覆的接觸墊有關的該第一半導體晶粒；以模封化合物封裝該第一半導體晶粒；移除該犧牲載體以顯露出該選擇性鍍覆的接觸墊；在移除該犧牲載體之後，形成第一導電層於該模封化合物和該選擇性鍍覆的接觸墊上；形成第一絕緣層於該第一導電層上；移除部分該第一絕緣層以顯露出該第一導電層；沉積與該第一導電層電接觸之導電材料；以及回焊該導電材料以形成一導電凸塊。
  2. 如申請專利範圍第1項所述之方法，更包含形成一導線連結，該導線連結電連接至複數個該選擇性鍍覆的接觸墊中之一個。
  3. 如申請專利範圍第1項所述之方法，更包含：形成穿過該模封化合物至該選擇性鍍覆的接觸墊之穿孔；於該穿孔中形成第二導電層以電連接至該選擇性鍍覆 的接觸墊；形成第二絕緣層於該第二導電層上；以及移除部分的該第二絕緣層以顯露出該第一導電層。
  4. 如申請專利範圍第1項所述之方法，更包含在複數個該選擇性鍍覆的接觸墊之每一個下方形成一柱狀物。
  5. 如申請專利範圍第1項所述之方法，更包含：固定第二半導體晶粒至該導電凸塊；以及以模封化合物封裝該第二半導體晶粒。
  6. 如申請專利範圍第1項所述之方法，其中複數個該選擇性鍍覆的接觸墊是藉光阻材料分隔。
  7. 一種製造半導體裝置之方法，包含：提供一犧牲載體；於該犧牲載體上形成複數個接觸墊；固定第一半導體晶粒至該接觸墊；以模封化合物封裝該第一半導體晶粒；移除該犧牲載體以顯露出該接觸墊；形成第一導電層於該模封化合物和被顯露出的該接觸墊之上；形成第一絕緣層於該第一導電層上；以及移除部分該第一絕緣層以顯露出該第一導電層。
  8. 如申請專利範圍第7項所述之方法，更包含：沉積導電材料於該第一導電層上；以及回焊該導電材料以形成一凸塊。
  9. 如申請專利範圍第8項所述之方法，更包含： 固定第二半導體晶粒至該凸塊；以及以模封化合物封裝該第二半導體晶粒。
  10. 如申請專利範圍第7項所述之方法，更包含移除該犧牲載體。
  11. 如申請專利範圍第7項所述之方法，其中該第一半導體晶粒透過凸塊或導線連結電連接至該接觸墊。
  12. 如申請專利範圍第7項所述之方法，更包含：形成第二導電層於該第一絕緣層上並電連接至該第一導電層；形成第二絕緣層於該第二導電層上；以及移除部分該第二絕緣層以顯露出該第二導電層。
  13. 如申請專利範圍第12項所述之方法，更包含以一黏著層固定一前側製程載體至該第二絕緣層。
  14. 一種製造半導體封裝結構之方法，包含：提供一犧牲載體；於該犧牲載體上形成複數個選擇性鍍覆的接觸墊；直接地固定第一半導體晶粒至該選擇性鍍覆的接觸墊；以模封化合物封裝該第一半導體晶粒；以及形成一互連架構於該模封化合物上並電連接至該選擇性鍍覆的接觸墊。
  15. 如申請專利範圍第14項所述之方法，其中形成該互連架構包含：形成第一導電層於該模封化合物上並電連接至該選擇 性鍍覆的接觸墊；形成第一絕緣層於該第一導電層上；以及移除部分該第一絕緣層以顯露出該第一導電層。
  16. 如申請專利範圍第15項所述之方法，更包含：形成第二導電層於該第一絕緣層上並電連接至該第一導電層；形成第二絕緣層於該第二導電層上；以及移除部分該第二絕緣層以顯露出該第二導電層。
  17. 如申請專利範圍第16項所述之方法，更包含以一黏著層固定一前側製程載體至該第二絕緣層。
  18. 如申請專利範圍第15項所述之方法，更包含：沉積導電材料於該第一導電層上；以及回焊該導電材料以形成一凸塊。
  19. 如申請專利範圍第14項所述之方法，更包含移除該犧牲載體。
  20. 如申請專利範圍第14項所述之方法，其中該第一半導體晶粒透過凸塊或導線連結電連接至該接觸墊。
  21. 如申請專利範圍第14項所述之方法，更包含在複數個該選擇性鍍覆的接觸墊之每一個下方形成一柱狀物。
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