KR100857727B1 - 구리 집적 회로에서의 상호 접속 - Google Patents
구리 집적 회로에서의 상호 접속 Download PDFInfo
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- KR100857727B1 KR100857727B1 KR1020010018579A KR20010018579A KR100857727B1 KR 100857727 B1 KR100857727 B1 KR 100857727B1 KR 1020010018579 A KR1020010018579 A KR 1020010018579A KR 20010018579 A KR20010018579 A KR 20010018579A KR 100857727 B1 KR100857727 B1 KR 100857727B1
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Abstract
본 명세서는 반도체 집적 회로에서 구리 금속화 상에 배리어층을 형성하는 공정에 대해서 기술한다. 상기 배리어층은 배선 접착 및 솔더 범프 상호 접속부들 모두에 효과적이다. 상기 배리어층은 구리 상에 형성된 Ti/Ni 이다. 알루미늄 접착 패드들이 배선 접착 상호 접속부들을 위해 상기 배리어층 상에 형성되고, 구리 접착 패드들이 솔더 범프 상호 접속부들을 위해 상기 배리어층 상에 형성된다.
구리, 금속화, 배리어, 배선 접착, 솔더 범프
Description
도1 및 도2는 배선 접착 또는 솔더 범프 접착에 적응된 구리 금속화된 IC칩의 접착 패드를 도시한 도면.
도3a, 도4a, 도5a, 도6a는 배선 접착 상호 접속부를 위해 사용된 도2의 IC 칩 접착 패드의 대표적인 개략도.
도3b, 도4b, 도5b, 도6b는 솔더 범프 상호 접속부를 위해 사용된 도2의 IC 칩 접착 패드의 대표적인 개략도.
* 도면의 주요부분에 대한 부호의 설명
11 : 실리콘 기판 13 : 구리 접촉 패드
31 : 배선 접착 위치 32 : 솔더 접착 위치
42 : 솔더 범프
본 발명은 구리 금속화(metallization) 및 배선 접착(wire bond) 또는 솔더 범프 접착(solder bump bond) 상호 접속부들을 가지는 집적 회로 패키지들에 관련된 것이다.
IC 기술의 시초부터 배선 접착은 집적 회로 패키지에 사용되어져 왔다. 배선 접착 기술 및 배선 접착 기기들은 배선 접착이 상대적으로 저렴하고 높은 견고성을 가지는 가에 주안점을 두고 발전해 왔다. 그러나, 특히 배선 접착들은 다수의 패키지 기술에서 이용 가능한 것보다 큰 피치(pitch)를 요구하기 때문에 배선 접착들은 더 진보된 패키지 기술에 의해 빠르게 대체되고 있다.
일반적인 IC 상호 접속 방법은 많은 핀 수를 갖는 IC 칩을 인쇄 배선 보드에 플립-칩 접착하거나 또는 IC 칩을 실리콘 중간 상호 접속 기판(silicon intermediate interconnect substrate)에 플립-칩 접착하는, 플립-칩(flip-chip) 접착이며, 상기 실리콘 중간 상호 접속 기판은 인쇄 배선 보드에 볼(ball) 접착 또는 플립-칩 접착된다. 많은 경우에 있어서 이러한 패키지들은 오목한 칩 배열들을 사용하여 패키지의 외형을 감소시킨다.
이러한 진보한 패키징 방법들에 있어서, 상호 접속 피치들은 매우 작을 수 있다. 배선 접착의 이전의 기술은 현재의 IC 칩의 고밀도의 I/O가 배선 접착의 기술의 능력에 도전하는 다수의 애플리케이션들에 대해 대체되고 있다. 그러나 IC 칩 기술의 고밀도의 I/O 로 인해, 진보된 패키징 기술들을 사용하는 패키징의 수율이 손해를 볼 수 있으며, 패키징 공정의 복잡성이 증가된다. 그 결과로, 접착당 총비용이 상대적으로 높아진다. 배선 접착의 낮은 비용 및 높은 신뢰성은, 고밀도 I/O 칩들의 패키징에 배선 접착을 적응시키는 방법들이 발견될 수 있다면 매력적인 것이 될것이다.
상호 접속 기술은 반도체 IC 장치들의 구리 금속화의 도입과 함께 새로운 도전에 당면해 있다. 구리는 낮은 비용 및 높은 전도성 때문에 오랜 기간 매력적인 후보 재료였다. 그러나, 구리는 전기 화학적으로 활성이며, 전기적 환경에서 마이그레이션(migration) 현상이 발생한다. 이는 또한 IC들에서 사용된 재료들과 함께 원하지 않는 합금을 형성한다. 이러한 예상되는 결점들은 IC 제조의 구리 금속화의 도입을 제한해 왔다. 그러나, 구리가 나타내는 전도성의 장점은 고주파 장치 상에서 매우 주목할만하여 구리는 IC 칩 상호 접속부들에서 알루미늄을 대체할 새로운 경향을 보이게 되었다.
알루미늄을 구리로 대체함에 있어, 특히나 다음 보드 레벨(board level) 상호 접속부에 칩을 인터페이스하는 마지막 상호 접속 레벨에서, 상호 접속부를 위한 새로운 고려가 발생한다. 알루미늄 칩 상호 접속들에 비하여, 배선 접착은 꾸준히 개발되어온 것이며 상대적으로 수월한 것이나, 알루미늄에 대한 솔더 범프 접착은 그러하지 않다. 솔더 범프 접착은 알루미늄에 직접 솔더링하기 어려운 이유로 인해 알루미늄 패드들을 위한 특별한 UBM(Under Bump Metallizaton)을 요구하였다. 구리로 알루미늄을 대체하면, 상기 상황은 다소 반전된다. 이론상, 솔더링의 관점에서는, 솔더 범프 접착들은 직접 구리 금속화 레벨의 최상에 직접 이뤄질수 있다. 그러나, 구리 IC 칩 금속화에 대한 직접적인 솔더 범프 접착은 구리의 마이그레이션 문제를 극복할수 없는 걸로 인식되고 있다. 따라서, 구리 금속화 상에 솔더 범프들을 위한 효과적인 UBM 기술들이 연구되었다. 이 UBM의 주요한 기능은, 알루미늄 금속화를 사용한 UBM과는 달리, 구리의 마이그레이션에 대한 배리어를 형성하는 것에 있다.
그리고, IC 생산 기술에 대한 구리 금속화의 도입은 배선 접착에 대한 새로운 접근법이 요구된다. 용이한 해법은 최상 구리 금속화 레벨 상에 직접 알루미늄 배선 접착 패드들을 형성하는 것이다. 그러나, 이 접근법은 다시 구리의 마이그레이션 문제를 제어하는 것에 실패한다.
상기 설명한 바와 같이, 배선 접착 상호 접속부와 솔더 범프 상호 접속부 모두를 구리 금속화될 IC 장치들에 이용하는 것이 바람직하게 여겨지기 때문에, 상기 두가지 상호 접속 전략들에 양립하는 구리 마이그레이션 문제의 해법을 개발하는 것은 유용하고 효과적인 것이 된다.
본 발명자는 구리 금속화에 대한 배선 접착과 솔더 범프 접착하는 것 모두를 위해 효과적으로 사용할 수 있는 상호 접속 야금(metallurgy)을 개발하였다. 그것은 금속 표면위에 초기 Ti/Ni 스택에 주요하게 의존한다. 배선 접착 애플리케이션을 위해, 알루미늄층이 Ti/Ni/Al 스택을 형성하는 Ni 층 상에 증착(deposit)된다. 솔더 범프 접착을 위해, 구리층이 Ti/Ni/Cu 스택을 형성하는 Ni 층 상에 증착된다. 유익한 전략은 모든 웨이퍼를 초기 Ti/Ni 스택으로 처리하는 것이다. 배선 접착될 웨이퍼들은 최후의 스퍼터링되는 층을 위해 알루미늄 타겟을 이용하여 처리되고, 솔더 범퍼 접착될 웨이퍼들은 최후이 스퍼터링되는 층을 위해 구리 타겟을 이용하여 처리된다. 일부 애플리케이션들을 위해, 스택의 초기층으로서 티타늄 대신 크롬으로 치환하는 것도 효과적이다.
도1을 참조하면, 실리콘 기판(11)은 더 큰 실리콘 웨이퍼의 부분을 표시하게 위해 부분적으로 잘려나간 것이 도시된다. 이 도면은 축적비율에 맞춘것이 아니고, 설명의 편이를 위해 몇몇 특징들을 과장하여 보여주는 것이 이해될 것이다. 도1에서, 증착된 유전체는 12로 도시되며 구리 접촉 패드는 13으로 도시된다. 폴리이미드(polyimide)의 캡핑층(capping layer) 또는 SINCAPS는 14로 도시된다. 상기층의 목적중 하나는 UBM로서 기능을 하는 구조로 그리고 두번째로는 금 배선 접착을 위한 접착 패드로서 기능하는 구조로 구리 접촉 패드(13)를 덮는 것이다. 상기 두가지 애플리케이션들을 제공하는 상기 층을 이룬 구조는, 본 명세서에서는 공통 복합층으로 인용될 것이며, 도2에서 6까지 관련되어 도시된다. 공통 복합층은 도시된 순서에 따라 증착 또는 다층 스퍼터링으로 형성된다. 일반적으로 스퍼터링이 이 단계에서 선호된다.
공통 복합층의 구조는 도2에서 보여진다. 바람직한 실시예에서, 층들은, 형성되는 층들의 금속들의 다중 타겟들을 포함하는 스퍼터링 장치에서 스퍼터링 된다. 스퍼터링 기술은 잘 알려져 있으며 그 세부사항은 본 설명에서 필요하지는 않다. 금속층들을 증착하는 다른 기술은, 예컨데 증발 또는 화학 기상 증착(chemical vapor deposition)이 사용될 수도 있다.
제 1 층(21)은 100-1500 옹스트롬의 두께의 크롬이나 티타늄이다. 크롬과 티타늄 모두 구리 접촉부(13)에 잘 부착되며 또한 구조에 존재하는 유전층들과 부착된다. 이 재료들은 또한 내화성이 있고 구리 접촉부와 부식 저항 인터페이스를 형성한다. 섭씨 300-450도에서, 200-500 옹스트롬 범위의 두께의 층으로 티타늄층을 스퍼터링하는 것이 추천된다. 상대적으로 높은 스퍼터링 온도는 접착과 안티-일렉트로마이그레이션(anti-electromigration) 시간을 향상시키는 Cu-Ti 전환층을 형성하는 것을 돕는다. 일부 애플리케이션에서는, 특히 현저하게 높은 온도의 처리나 인화 테스팅을 요구하는 애플리케이션들에 대해, 산소 배리어(oxygen barrier)로서 양호한 수행 때문에 크롬이 선호된다. 또한 더 효과적인 산소 배리어 특성을 위한 질화 크롬층을 생성하기 위하여 주위 질소 온도가 섭씨 25-300도에서 크롬층을 스퍼터링하는 것이 선호된다. 추천되는 질화 크롬층의 두께는 400-1500 옹스트롬의 범위이다.
제 2 층(22)은 니켈을 포함하는 배리어층으로, 2,000-20,000 옹스트롬 범위의 두께를 갖는다. 니켈층은 스퍼터링되며 그 스퍼터링 타겟은 스퍼터링을 돕기 위해 0.5-10%V를 포함하는 것이 바람직하다. 상기 층은 강인한 고형 용액을 제공하기 위해 0.5-2.0%의 크롬, 몰리브덴, 텅스텐, 탄탈, 지르코늄, 니오븀 또는 보론으로 도핑될 수도 있다. 상기 층(22)은 적어도 99%의 니켈을 포함하는 것이 바람직하다. 이 층의 스퍼터링은 니켈과 바나듐 타겟 모두를 가진 장치에서 수행될 수 있으며, 선택된 다른 어떤 도펀트(dopant)의 적절한 타겟, 또는 더 전형적으로, 예컨데 니켈(7%V) 의 합성물 타겟으로부터 스퍼터링될 수 있다. 앞선 대체물은 두께를 가진 증착된 층의 합성의 변화를 생성하는 타겟들 간에 전환의 선택을 제공한다.
참착된 층의 구조는 증착 주기동안의 온도의 변화에 의해 두께가 전환될 수도 있다. 예를 들어, 온도가 증착 시작에 섭씨 25도이고, 증착 종료시에 섭씨 300도 까지 올라가면, 상기층은 바닥 인터페이스에서 무결정의 구조로 증착하며, 양호한 Ti/Ni 인터페이스 특성을 갖고, 층의 최상부에서는 최적의 Ni/Al 인터페이스 특성을 위한 결정 성질을 갖는다.
공통 복합층 스택은 , 또한 이하 설명할 층의 상단부는, 진공상태를 유지하는, 동일한 증착 장치로 증착된다. 이 방법은 본 발명에 따라 실제적으로 또다른 선택적인 스택 구조를 만들게 된다. 특별히 효과적인 배리어 특성을 제공하는 이 선택은 Ti/Ni 층들을, 예컨데 Ti/Ni/Ti/Ni을 생성하는 것으로 대체하는 것이다. 이 대체된 층들은 원하는 경우 증가될 수도 있다.
스택의 마지막 층의 합성물은 사용될 상호 접속 기술에 따른다. 배선 접착될 웨이퍼들에 대해, 최상층은 알루미늄으로 하고, 예컨데 1-2 미크론의 두께를 가지며, 섭씨 25-200도에서 바람직하게 증착된다. 이 알루미늄층은 0.5-2.0%의 구리로 도핑될 수 있다. 솔더 범프 위치들을 위해, 마지막 층은 0.5-1.0 미크론의 구리가 된다.
이 대체물들은 도3a 내지 도3b 내지 도6a 내지 도6b에 도시되며 도3a 내지 도6a는 도면 상에 배선 접착 위치를 도시하고 있으며 도3b 내지 도6b는 도면 상에 솔더 범프 위치를 도시하고 있다.
도3a를 참조하면, 다층 스택의 마지막 또는 최상층은 알루미늄층(31)이다. 상기 알루미늄층은 전형적인 금선으로 배선 접착될 수 있다. 도3b를 참조하면, 다층 스택의 최상층은 구리층(32)이다. 상기 구리층은 솔더 범프에 일반적으로 이용되는 솔더 재료를 적실 수 있다(wettable). 대부분의 주석 솔더의 구리 공정의 녹는점은 비교적 낮으며, 솔더링 온도에서 구리층의 표면은 물리적 및 전기적으로 견고한 접착을 형성하는 솔더 범프에서 녹게된다. 구리층(32)은 구리 표면의 산화를 막기 위하여 구리층의 표면에 적용된 선택적인 금(gold)층이 제공될 수 있다. 선택적인 금층은 200-2000 옹스트롬의 두께를 가질 수 있으며, 200-1000 옹스트롬정도가 바람직하다.
다층 스택의 증착이 완료되었으면, 도4a 및 도4b에 도시된 바와 같이 접착 위치들은 에치 마스크(etch mask)(33)로 마스크된다. 에치 마스크는 종래의 포토레지스트가 바람직하며, 층 표면층 상에 포토레지스트를 회전 가공하고 적절한 화학선 복사(actinic radiation)로 포토레지스트를 패터닝(patterning)함으로써 형성된다. 예컨데, 산화 하드마스크(oxide hardmask)와 같은 대체적인 마스킹 기술도 사용 가능하다.
스택 구조들은 예컨데 습식 에칭(wet etching) 또는 RIE와 같은 종래 에칭에 의해 정의된다. 금층이 존재한다면, 금층과 구리층(32)은 종래 에칭 방법을 사용하여 에칭된다. 금 부식액(etchants)은 시안화/페리시안화 칼륨 용액, 요오드화/요오드 용액, 왕수(aqua regia)를 포함한다. 구리는 예컨데 철 염화물 또는 황산과 크롬산 칼륨을 가지고 에칭한다.
알루미늄층(31)은 KOH 또는 다른 적절한 부식액을 이용하여 에칭될 수 있다. 니켈층(22)은 HCL을 이용하여 에칭될 수 있다. 티타늄층(21)은 완충된 HF로 에칭될 수 있다. 층(21)이 크롬인 경우, 수산화나트륨과 페리시안화 칼륨의 기본적인 크롬 에칭 용액을 사용하여 에칭이 가능하다.
다층의 에칭과 에치 마스크를 제거하고 난 후, 구조는 도5a와 도5b와 같이 도시된다. 배선 접착될 접착 위치(31)는 도6에서 금선 접착(41) 부착되어 도시된다. 배선은 견고성을 위해 금, 또는 Au-Be와 같은 소량의 금속 첨가물을 가진 금혼합물이 바람직하다. 배선의 직경은 전형적으로 0.5-2 밀(mils)정도이며, 1-1.2 밀(mils)이 바람직하다. 알루미늄 접착 패드들의 넓이는 전형적으로 1000-40000 제곱 마이크로미터이며 5000-25000 제곱 마이크로미터가 바람직하다. 배선 접착 단계는 전형적으로 기술상 널리 사용될 수 있는 기구를 사용하는 접착을 이용하는 열압축(thermocompression) 작업이다. 접착력은 15-60 grams 범위가 될 수 있으며, 40-60 grams이 바람직하다. 초음파의 주파수는 40-200 kHz범위이며, 60-120 kHz가 바람직하고, 전력은 20-200 mW 범위이며, 50-100 mW가 바람직하다. 이 값들은 예컨데 K&S 배선 접착기를 포함하는 여러 접착 기구들에 적절하다.
솔더 접착 위치(32)는 도6b에서 솔더 범프(42)와 같이 도시된다. 이 도면은 도시 생략된 상호 접속 기판 상의 메이팅 표면(mating surface)의 개략도이다. 솔더 범프는 솔더 페이스트(solder paste), 또는 증착(evaporation)과 같은 적절한 기술에 의해 형성된다. 후자는 전형적으로 95PbSn과 같은 높은 리드 컨텐트의 솔더에 적절하다. 솔더 범프는 또한 예를 들어 합성물의 최하위층을 음극으로 하는 전기도금에 의해서도 형성할 수 있다. 이러한 일련의 공정동안 3개층의 스택은 상기에 설명한 바와 같이 증착되며, 솔더 범프 위치들이 마스크된다. 최상층 또는 층들은 음극이 되기 위한 Ti 또는 Cr 층을 남기고 제거된다. 최하위층은 전기분해 도금 과정을 솔더 범프 위치에 위치시키기 위해 마스크된다. 도금과 솔더 리플로(solder reflow)후에 최하층은 패터닝된다. 이 솔더들은 전기를 가하지 않는 도금에 의해서도 대체되어 제공될 수 있다.
전형적인 솔더의 두께는 1-10밀이다. 공정에서 성공적으로 사용되어질 수 있는 솔더 합성물의 예는 이하에 기술한다.
I II III IV
Sn 5 63 95 3.5
Pb 95 37 0 0
Sb 0 0 5 0
Ag 0 0 0 96.5
상기에 기술된 공정은 실리콘 CMOS 집적 회로를 위해 개발된 것이나 III-V 포토닉 집적 회로와 같은 다른 종류의 반도체 집적 회로에도 똑같이 적용될 수 있다. 이 집적 회로들은 전형적으로 GaAs 또는 InP 기판을 가지고 능동 장치를 형성하는 III-V 3중 및/또는 4중층의 다중 레벨을 가진다. 그러나, 몇몇 애플리케이션들에서 상호 접속부는 실리콘 IC 기술에서 사용된 것과 유사하다. 이 회로들은 또한 통상 고속으로 작동하며 그 점에서 구리 금속화는 특별히 우수하다.
오늘날 제조된 대부분의 실리콘 집적 회로는 트랜지스터 장치를 위해 다결정실리콘 게이트(polysilicon gate)를 가지고 있으며, 제1 레벨 금속은 전형적으로 게이트를 형성하고 게이트들과의 상호 접속부를 형성하기 위해 폴리실리콘이다. 제1레벨후의 금속 상호 접속 레벨들은 대개 알루미늄이며, 하나에 세개의 알루미늄 레벨인 것이 일반적이다. 이들의 하나 이상은 상기 서술한 바와 같이 구리로 대체될 것이다.
상기에 서술된 과정은 배선 접착 또는 솔더 범프 접착중 하나를 위한 개개의 웨이퍼 과정을 이용하는 것에 주목한다. 본 발명은 또한 배선, 솔더 범프 둘 다 접착된 웨이퍼에 응용가능하다. 이 경우에 있어서 하나의 웨이퍼는 본 발명의 배선 접착 패드와 솔더 범프 접착 모두를 가지게 처리된다. 이것은 가장 전형적으로 ,상기에 서술한 바와 같이, 제1 및 제2 층을, 즉 티타늄/크롬층, 가지게 하여 처리하고, 상기 층은 니켈을 포함하고, 선택적으로 구리를 솔더 접착 위치에 증착하고, 선택적으로 알루미늄을 배선 접착 위치에 증착하게 함으로써 달성될 수 있다. 후자의 두 단계는 양자 택일적으로 이뤄질 수 있다는 것은 이해될 것이다. 선택적인 증착 단계는 대용되는 방법(마스크와 에칭)을 이용하거나, 바람직하게 추가되는 방법(lift-off)을 이용하는 표준 리소그래피(lithography)에 의해 달성될 것이다. 이 층들은 특별히 접착 위치 상에 증착되어질 수 있으며, 또는 접착 위치를 가지는 덮개 영역위에 증착되어질 수 있다. 이러한 접근법은 두 가지 상호 접속 방법에 대한 구리의 마이그레이션 문제를 해결하기 위하여 공통 복합층이 가지는 다양한 능력을 완전하게 설명하고 있다.
이 공통 복합 배리어층은 또한 금 금속화에도 유용하다. 금은 포토닉 집적 회로에서 소재 간의 상호 접속에 널리 사용되고 있다. 응용의 다양성을 위한 일반적인 UBM을 가짐으로써 제공되는 다양한 능력은 해당 기술분야의 당업자에게는 자명할 것이다.
본 발명의 많은 추가적인 개조는 기술분야의 당업자에게 일어날 것이다. 진행되어온 기술을 통한 원리들과 그것들의 균등물에 따르는 본 명세서에서 특정하는 내용으로부터의 변형은 설명하고 청구하여진 본발명의 범위내에서 적절히 고려되어야 한다.
본 발명에 따르면 구리 금속화 IC에 있어 마이그레이션 현상을 개선하고 배선 접착과 솔더 범프 접착 모두를 사용가능케하여 구리 금속화 IC의 효과적인 사용을 도모할 수 있다.
Claims (20)
- 복수의 구리 접촉부들(copper contacts)을 갖는 반도체 집적 회로 제조 방법에 있어서:(a) 상기 복수의 구리 접촉부들 상에 제 1 층을 증착(deposit)하는 단계로서, 상기 제 1 층은 티타늄과 크롬으로 구성된 그룹으로부터 선택된 재료로 이루어진, 상기 제 1 층 증착 단계;(b) 상기 제 1 층 상에 니켈을 포함하는 제 2 층을 증착하는 단계;(c) 상기 제 2 층 상에 알루미늄을 포함하는 제 3 층을 증착하는 단계;(d) 접착 패드(bond pad)를 형성하기 위해 상기 제 1 층, 제 2 층, 및 제 3 층을 에칭하는 단계; 및(e) 상기 제 3 층에 도전 배선 상호 접속부(conductive wire interconnection)를 접착하는 단계를 포함하는, 반도체 집적 회로 제조 방법.
- 제 1 항에 있어서, 상기 반도체 집적 회로의 반도체는 실리콘인, 반도체 집적 회로 제조 방법.
- 제 2 항에 있어서, 상기 배선은 금(gold)을 포함하고, 열압축 접착(thermocompression bonding)을 이용하여 접착되는, 반도체 집적 회로 제조 방법.
- 제 1 항에 있어서, 단계(a)에 앞서, 상기 구리 접촉부들 상에 캡핑층(capping layer)을 증착하고, 상기 캡핑층 내에 윈도우들(windows)을 형성하고, 단계(a) 내지 단계(c)로 진행하는 단계를 더 포함하는, 반도체 집적 회로 제조 방법.
- 제 1 항에 있어서, 상기 제 1 층, 제 2 층, 및 제 3 층은 진공 상태를 유지하는 동일한 스퍼터링 장치(sputtering apparatus)에서 순차적으로 스퍼터링되는, 반도체 집적 회로 제조 방법.
- 제 1 항에 있어서, 상기 니켈층은 0.5 내지 10%의 바나듐을 가진 니켈을 포함하는, 반도체 집적 회로 제조 방법.
- 제 1 항에 있어서, 상기 제 1 층은 크롬을 포함하고, 질소 분위기에서 스퍼터링함으로써 증착되는, 반도체 집적 회로 제조 방법.
- 삭제
- 삭제
- 복수의 구리 접촉부들을 갖는 반도체 집적 회로 제조 방법에 있어서:(a) 상기 복수의 구리 접촉부들 상에 제 1 층을 증착하는 단계로서, 상기 제 1 층은 티타늄인, 상기 제 1 층 증착 단계;(b) 상기 제 1 층 상에 니켈을 포함하는 제 2 층을 증착하는 단계;(c) 상기 제 2 층 상에 구리를 포함하는 제 3 층을 증착하는 단계;(d) 접착 패드를 형성하기 위해 상기 제 1 층, 제 2 층, 및 제 3 층을 에칭하는 단계; 및(e) 상기 제 3 층에 솔더 범프 상호 접속부(solder bump interconnection)를 접착하는 단계를 포함하는, 반도체 집적 회로 제조 방법.
- 제 10 항에 있어서, 상기 반도체 집적 회로의 반도체는 실리콘인, 반도체 집적 회로 제조 방법.
- 제 10 항에 있어서, 상기 제 1 층, 제 2 층, 및 제 3 층은 진공 상태를 유지하는 동일한 스퍼터링 장치에서 순차적으로 스퍼터링되는, 반도체 집적 회로 제조 방법.
- 제 10 항에 있어서, 상기 니켈층은 0.5 내지 10%의 바나듐을 가지는 니켈을 포함하는, 반도체 집적 회로 제조 방법.
- 삭제
- 삭제
- 반도체 집적 회로 제조 방법에 있어서:(a) 반도체 기판 상에 복수의 구리 접촉부들을 형성하는 단계;(b) 상기 구리 접촉부들 상에 유전층을 증착하는 단계;(c) 상기 구리 접촉부들의 노출된 부분들을 남기도록 상기 유전층 내에 복수의 개구들(openings)을 형성하는 단계;(d) 상기 유전층과 상기 구리 접촉부들의 상기 노출된 부분들 상에 제 1 층을 스퍼터링하는 단계로서, 상기 제 1 층은 100 내지 1,500 옹스트롬의 티타늄층을 포함하는, 상기 제 1 층 스퍼터링 단계;(e) 상기 제 1 층 상에 제 2 층을 스퍼터링하는 단계로서, 상기 제 2 층은 2,000 내지 20,000 옹스트롬의 니켈/바나듐 합금층을 포함하는, 상기 제 2 층 스퍼터링 단계;(f) 상기 제 2 층 상에 제 3 층을 스퍼터링하는 단계로서, 상기 제 3 층은 대략 1 내지 2 미크론의 알루미늄층을 포함하는, 상기 제 3 층 스퍼터링 단계;(g) 접착 패드를 남기도록 상기 제 1 층, 제 2 층, 및 제 3 층의 선택된 부분들을 에칭하여 제거하는 단계;(h) 도전 배선을 상기 접착 패드에 열압축 접착하는 단계를 포함하는, 반도체 집적 회로 제조 방법.
- 제 16 항에 있어서, 상기 제 1 층은 섭씨 300 내지 450도 온도 범위에서 스퍼터링되고, 상기 제 2 층은 섭씨 25 내지 300도 온도 범위에서 스퍼터링되고, 상기 제 3 층은 섭씨 25 내지 200도 온도 범위에서 스퍼터링되는, 반도체 집적 회로 제조 방법.
- 최상 금속화 레벨(top metallization level)을 갖고, 배선 접착 상호 접속 위치들 및 솔더 범프 상호 접속 위치들이 제공되는 반도체 집적 회로 제조 방법에 있어서:(a) 상기 최상 금속화 레벨의 선택된 부분들 상에 제 1 층을 증착하는 단계로서, 상기 제 1 층은 티타늄과 크롬으로 구성된 그룹으로부터 선택된 재료로 이루어진, 상기 제 1 층 증착 단계;(b) 상기 제 1 층 상에 니켈을 포함하는 제 2 층을 증착하는 단계;(c) 상기 배선 접착 위치들 상에 알루미늄을 포함하는 제 1 접촉층을 선택적으로 증착하는 단계;(d) 상기 솔더 범프 위치들 상에 구리를 포함하는 제 2 접촉층을 선택적으로 증착하는 단계;(e) 배선 접착 패드들 및 솔더 범프 패드들을 형성하기 위해 상기 제 1 층, 제 2 층, 및 제 1 접촉층 및 제 2 접촉층을 에칭하는 단계(f) 상기 배선 접착 위치들에 도전 배선 상호 접속부들을 접착하는 단계; 및(g) 상기 솔더 범프 위치들에 솔더 범프 상호 접속부들을 접착하는 단계를 포함하는, 반도체 집적 회로 제조 방법.
- 제 18 항에 있어서, 상기 반도체 집적 회로의 최상 금속화 레벨은 구리를 포함하는, 반도체 집적 회로 제조 방법.
- 복수의 반도체 집적 회로 웨이퍼들을 제조하는 방법으로서, 상기 복수의 반도체 집적 회로 웨이퍼들의 제 1 그룹에는 배선 접착 상호 접속 위치들이 제공되고, 상기 복수의 반도체 집적 회로 웨이퍼들의 제 2 그룹에는 솔더 범프 상호 접속 위치들이 제공되고, 상기 복수의 웨이퍼들은 구리 접촉부들을 갖는, 상기 복수의 반도체 집적 회로 웨이퍼들 제조 방법에 있어서:(a) 상기 구리 접촉부들의 선택된 부분들 상에 제 1 층을 증착하는 단계로서, 상기 제 1 층은 티타늄과 크롬으로 구성된 그룹으로부터 선택된 재료로 이루어진, 상기 제 1 층 증착 단계;(b) 상기 제 1 층 상에 니켈을 포함하는 제 2 층을 증착하는 단계;(c) 상기 복수의 웨이퍼들을 제 1 그룹 및 제 2 그룹으로 분리하는 단계;(d) 상기 제 1 그룹의 상기 배선 접착 위치들 상에 알루미늄을 포함하는 제 1 접촉층 증착하는 단계;(e) 상기 제 2 그룹의 상기 솔더 범프 위치들 상에 구리를 포함하는 제 2 접촉층 증착하는 단계;(f) 상기 제 1 그룹의 배선 접착 위치들에 도전 배선 상호 접속부들을 접착하는 단계; 및(g) 상기 제 2 그룹의 솔더 범프 위치들에 솔더 범프 상호 접속부들을 접착하는 단계를 포함하는, 반도체 집적 회로 웨이퍼 제조 방법.
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TW571373B (en) * | 1996-12-04 | 2004-01-11 | Seiko Epson Corp | Semiconductor device, circuit substrate, and electronic machine |
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- 2000-04-10 US US09/546,037 patent/US6620720B1/en not_active Expired - Lifetime
-
2001
- 2001-04-09 TW TW090108450A patent/TWI223427B/zh not_active IP Right Cessation
- 2001-04-09 EP EP01303322A patent/EP1146552B1/en not_active Expired - Lifetime
- 2001-04-09 KR KR1020010018579A patent/KR100857727B1/ko active IP Right Grant
- 2001-04-09 AT AT01303322T patent/ATE527687T1/de not_active IP Right Cessation
- 2001-04-10 JP JP2001110719A patent/JP2001351940A/ja active Pending
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US4661375A (en) * | 1985-04-22 | 1987-04-28 | At&T Technologies, Inc. | Method for increasing the height of solder bumps |
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Also Published As
Publication number | Publication date |
---|---|
JP2001351940A (ja) | 2001-12-21 |
ATE527687T1 (de) | 2011-10-15 |
US6620720B1 (en) | 2003-09-16 |
TWI223427B (en) | 2004-11-01 |
EP1146552B1 (en) | 2011-10-05 |
KR20010090777A (ko) | 2001-10-19 |
EP1146552A3 (en) | 2003-04-16 |
EP1146552A2 (en) | 2001-10-17 |
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