JP2006518115A - 集積回路基板および関連する構造の選択的バンピング方法 - Google Patents
集積回路基板および関連する構造の選択的バンピング方法 Download PDFInfo
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- JP2006518115A JP2006518115A JP2006503894A JP2006503894A JP2006518115A JP 2006518115 A JP2006518115 A JP 2006518115A JP 2006503894 A JP2006503894 A JP 2006503894A JP 2006503894 A JP2006503894 A JP 2006503894A JP 2006518115 A JP2006518115 A JP 2006518115A
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Abstract
Description
本願は、2003年2月18日に出願された米国仮特許出願第60/448,096号の優先権の利益を享受し、同出願の内容全体を引用することにより、本明細書の一部をなすものとする。
過酸化水素−10〜20%
スルホサリチル酸−2〜30グラム/リットル
硫化カリウム−25〜200グラム/リットル
ベンゾトリゾール−1〜10グラム/リットル
補給水
温度:30〜70℃
pH<7
過酸化水素−10〜20%
スルホサリチル酸−2〜30グラム/リットル
硫化カリウム−25〜200グラム/リットル
ベンゾトリゾール−1〜10グラム/リットル
補給水
温度:30〜70℃
pH<7
過酸化水素−10〜20%
スルホサリチル酸−2〜30グラム/リットル
硫化カリウム−25〜200グラム/リットル
ベンゾトリゾール−1〜10グラム/リットル
補給水
温度:30〜70℃
pH<7
過酸化水素−10〜20%
スルホサリチル酸−2〜30グラム/リットル
硫化カリウム−25〜200グラム/リットル
ベンゾトリゾール−1〜10グラム/リットル
補給水
温度:30〜70℃
pH<7
Claims (49)
- 金属層を含む基板上に障壁層を形成するステップと、
前記障壁層上に伝導性バンプを形成するステップであって、前記障壁層が該伝導性バンプと前記基板との間にあり、該伝導性バンプが前記金属層からオフセットされるステップと、
前記伝導性バンプを形成した後に、前記障壁層の少なくともいくらかを前記金属層から除去することによって、前記伝導性バンプと前記基板との間に前記障壁層の一部分を維持しながら、前記金属層を露出するステップと
を含んでなる、上部に金属層を含む基板をバンピングする方法。 - 前記基板が集積回路基板を含む請求項1に記載の方法。
- 前記金属層がアルミニウム層を含む請求項1に記載の方法。
- 前記障壁層がチタンタングステン層を含む請求項1に記載の方法。
- 前記金属層と前記障壁層と前記伝導性バンプとの全てが異なる材料を含む請求項1に記載の方法。
- 前記伝導性バンプを形成するステップの前に、前記障壁層上に伝導性アンダーバンプ冶金層を形成するステップと、
前記障壁層を除去する前に、前記伝導性バンプと前記基板との間に前記伝導性アンダーバンプ冶金層の一部分を維持しながら、前記金属層とは反対の前記障壁層から前記伝導性アンダーバンプ冶金層を除去するステップと
をさらに含む請求項1に記載の方法。 - 前記伝導性アンダーバンプ冶金層が銅を含む請求項6に記載の方法。
- 前記伝導性アンダーバンプ冶金層および前記障壁層が異なる材料を含む請求項6に記載の方法。
- 前記伝導性バンプを形成するステップの前に、前記アンダーバンプ冶金層上に第2の障壁層を形成するステップをさらに含み、前記第2の障壁層および前記アンダーバンプ冶金層が異なる材料を含み、前記第2の障壁層が前記伝導性バンプと前記伝導性アンダーバンプ冶金層との間にある請求項6に記載の方法。
- 前記第2の障壁層がニッケルを含む請求項9に記載の方法。
- 前記アンダーバンプ冶金層が銅を含む請求項10に記載の方法。
- 前記第2の障壁層を形成するステップが、前記アンダーバンプ冶金層の一部分上に前記第2の障壁層を選択的に形成するステップを含み、前記第2の障壁層が前記金属層からオフセットされる請求項9に記載の方法。
- 前記伝導性バンプを形成するステップが、前記金属層からオフセットされた前記第2の障壁層上に前記伝導性バンプを選択的に形成するステップを含む請求項12に記載の方法。
- 前記第2の障壁層を形成し、前記伝導性バンプを選択的に形成するステップが、同一のマスクを用いて、前記第2の障壁層および前記伝導性バンプを選択的に形成するステップを含む請求項13に記載の方法。
- 前記伝導性バンプが、はんだ、金、および/または、銅の少なくとも1つを含む請求項1に記載の方法。
- 前記伝導性バンプを形成するステップが、前記金属層からオフセットされた前記障壁層上に前記バンプを選択的にめっきするステップを含む請求項1に記載の方法。
- 前記集積回路基板が上部に入出力パッドを含み、前記障壁層が前記金属層および前記入出力パッドを含む前記基板上に形成され、前記伝導性バンプが前記入出力パッドの反対の前記障壁層上に形成される請求項1に記載の方法。
- 前記金属層および前記バンプパッドの両方がアルミニウムを含む請求項17に記載の方法。
- 前記基板が上部に入出力パッドを含み、前記障壁層が前記金属層および前記入出力パッドを含む前記基板上に形成され、前記金属層から前記障壁層を除去した後に、前記伝導性バンプが前記入出力パッドに電気的に連結される請求項1に記載の方法。
- 前記金属層および前記入出力パッドの両方がアルミニウムを含む請求項19に記載の方法。
- 前記伝導性バンプが前記入出力パッドとは反対の前記障壁層上に形成される請求項19に記載の方法。
- 前記伝導性バンプが前記入出力パッドからオフセットされる請求項19に記載の方法。
- 前記金属層から前記障壁層を除去した後に、前記伝導性バンプに第2の基板を結合するステップをさらに含む請求項1に記載の方法。
- 上部に露出された金属層を含む基板と、
該露出された金属層からオフセットされた前記基板上にある障壁層と、
該障壁層上にある伝導性バンプであって、前記障壁層が前記伝導性バンプと前記基板との間にあり、前記伝導性バンプが前記金属層からオフセットされ、前記障壁層と前記伝導性バンプと前記金属層との全てが異なる伝導性材料を含むものである伝導性バンプと
を含んでなる電子デバイス。 - 前記電子デバイスが集積回路デバイスを含み、前記基板が集積回路基板を含む請求項24に記載の電子デバイス。
- 前記障壁層がチタンタングステンを含む請求項24に記載の電子デバイス。
- 前記露出された金属層がアルミニウムを含む請求項25に記載の電子デバイス。
- 前記伝導性バンプが、はんだ、金、および/または、銅の少なくとも1つを含む請求項25に記載の電子デバイス。
- 前記障壁層と前記伝導性バンプとの間に、伝導性アンダーバンプ冶金層をさらに含む請求項24に記載の電子デバイス。
- 前記伝導性バンプに結合された第2の基板をさらに含む請求項24に記載の電子デバイス。
- 前記集積回路基板上に入出力パッドをさらに含み、前記障壁層および前記伝導性バンプが前記入出力パッドに電気的に接続される請求項24に記載の電子デバイス。
- 前記入出力パッドおよび前記金属層の各々がアルミニウムを含む請求項31に記載の電子デバイス。
- 前記伝導性バンプが、前記入出力パッドとは反対の前記障壁層上にある請求項31に記載の電子デバイス。
- 前記伝導性バンプが、前記入出力パッドからオフセットされている請求項31に記載の電子デバイス。
- 前記障壁層と前記伝導性バンプとの間にアンダーバンプ冶金層をさらに含み、前記アンダーバンプ冶金層および前記障壁層が異なる材料を含む請求項25に記載の電子デバイス。
- 露出された金属層からオフセットされた基板上に障壁層を形成するステップと、
該障壁層上に伝導性バンプを形成するステップであって、該障壁層が該伝導性バンプと前記基板との間にあり、該伝導性バンプが前記金属層からオフセットされ、該障壁層と該伝導性バンプと前記金属層との全てが異なる伝導性材料を含むものであるステップと
を含んでなる、上部に露出された金属層を含む基板を含む電子デバイスをバンピングする方法。 - 前記電子デバイスが集積回路デバイスを含み、前記基板が集積回路基板を含む請求項36に記載の方法。
- 前記障壁層がチタンタングステンを含む請求項36に記載の方法。
- 前記露出された金属層がアルミニウムを含む請求項38に記載の方法。
- 前記伝導性バンプが、はんだ、金、および/または、銅の少なくとも1つを含む請求項38に記載の方法。
- 前記障壁層と前記伝導性バンプとの間に伝導性アンダーバンプ冶金層を形成するステップをさらに含む請求項36に記載の方法。
- 前記伝導性バンプに結合された第2の基板を結合するステップをさらに含む請求項36に記載の方法。
- 前記集積回路基板が上部に入出力パッドを含み、前記障壁層および前記伝導性バンプが前記入出力パッドに電気的に接続される請求項36に記載の方法。
- 前記入出力パッドおよび前記金属層の各々がアルミニウムを含む請求項43に記載の方法。
- 前記伝導性バンプが前記入出力パッドとは反対の前記障壁層にある請求項43に記載の方法。
- 前記伝導性バンプが前記入出力パッドからオフセットされる請求項43に記載の方法。
- 前記障壁層と前記伝導性バンプとの間にアンダーバンプ冶金層をさらに含み、前記アンダーバンプ冶金層および前記障壁層が異なる材料を含む請求項36に記載の方法。
- 金属層を含む基板上に障壁層を形成するステップと、
該障壁層上に伝導性バンプを形成するステップであって、該障壁層が該伝導性バンプと前記基板との間にあり、該伝導性バンプが前記金属層から横方向にオフセットされているステップと、
前記伝導性バンプを形成した後に、前記金属層から前記障壁層を除去することによって、前記伝導性バンプと前記基板との間に前記障壁層の一部分を維持しながら、前記金属層を露出するステップと
を含んでなる、上部に金属層を含む集積回路基板をバンピングする方法。 - 集積回路基板と、
該集積回路基板上にある露出された金属層と、
該露出された金属層から横方向にオフセットされた前記集積回路基板上にある障壁層と、
該障壁層上にある伝導性バンプであって、該障壁層が該伝導性バンプと前記基板との間にあり、前記伝導性バンプが前記金属層から離れている伝導性バンプと
を含んでなる集積回路デバイス。
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Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7244671B2 (en) * | 2003-07-25 | 2007-07-17 | Unitive International Limited | Methods of forming conductive structures including titanium-tungsten base layers and related structures |
TWI223425B (en) * | 2003-09-23 | 2004-11-01 | Advanced Semiconductor Eng | Method for mounting passive component on wafer |
WO2005034597A1 (ja) * | 2003-10-03 | 2005-04-14 | Shinko Electric Industries Co., Ltd. | 配線基板のパッド構造及び配線基板 |
US20050085062A1 (en) * | 2003-10-15 | 2005-04-21 | Semitool, Inc. | Processes and tools for forming lead-free alloy solder precursors |
US7410833B2 (en) * | 2004-03-31 | 2008-08-12 | International Business Machines Corporation | Interconnections for flip-chip using lead-free solders and having reaction barrier layers |
US7005370B2 (en) * | 2004-05-13 | 2006-02-28 | St Assembly Test Services Ltd. | Method of manufacturing different bond pads on the same substrate of an integrated circuit package |
JP2005350911A (ja) | 2004-06-09 | 2005-12-22 | Komatsu Ltd | 作業車両 |
DE102004047730B4 (de) * | 2004-09-30 | 2017-06-22 | Advanced Micro Devices, Inc. | Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen |
US7410824B2 (en) * | 2004-12-09 | 2008-08-12 | Stats Chippac Ltd. | Method for solder bumping, and solder-bumping structures produced thereby |
US20060147683A1 (en) * | 2004-12-30 | 2006-07-06 | Harima Chemicals, Inc. | Flux for soldering and circuit board |
US7241678B2 (en) | 2005-01-06 | 2007-07-10 | United Microelectronics Corp. | Integrated die bumping process |
US7381634B2 (en) * | 2005-04-13 | 2008-06-03 | Stats Chippac Ltd. | Integrated circuit system for bonding |
DE102005035772A1 (de) * | 2005-07-29 | 2007-02-01 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum effizienten Strukturieren einer Höckerunterseitenmetallisierungsschicht unter Anwendung eines Trockenätzprozesses |
US7705385B2 (en) * | 2005-09-12 | 2010-04-27 | International Business Machines Corporation | Selective deposition of germanium spacers on nitride |
KR100742376B1 (ko) * | 2005-09-30 | 2007-07-24 | 삼성에스디아이 주식회사 | 패드부 및 그 제조 방법 |
TW200733270A (en) * | 2005-10-19 | 2007-09-01 | Koninkl Philips Electronics Nv | Redistribution layer for wafer-level chip scale package and method therefor |
JP2007115957A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2007115958A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置 |
US8076779B2 (en) * | 2005-11-08 | 2011-12-13 | Lsi Corporation | Reduction of macro level stresses in copper/low-K wafers |
US7378339B2 (en) * | 2006-03-30 | 2008-05-27 | Freescale Semiconductor, Inc. | Barrier for use in 3-D integration of circuits |
US7682961B2 (en) | 2006-06-08 | 2010-03-23 | International Business Machines Corporation | Methods of forming solder connections and structure thereof |
US8440272B2 (en) * | 2006-12-04 | 2013-05-14 | Megica Corporation | Method for forming post passivation Au layer with clean surface |
US8124490B2 (en) * | 2006-12-21 | 2012-02-28 | Stats Chippac, Ltd. | Semiconductor device and method of forming passive devices |
CN101226889B (zh) * | 2007-01-15 | 2010-05-19 | 百慕达南茂科技股份有限公司 | 重配置线路结构及其制造方法 |
TWI337386B (en) * | 2007-02-16 | 2011-02-11 | Chipmos Technologies Inc | Semiconductor device and method for forming packaging conductive structure of the semiconductor device |
US7682959B2 (en) | 2007-03-21 | 2010-03-23 | Stats Chippac, Ltd. | Method of forming solder bump on high topography plated Cu |
JP5113177B2 (ja) * | 2007-09-04 | 2013-01-09 | 京セラ株式会社 | 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 |
US8293587B2 (en) * | 2007-10-11 | 2012-10-23 | International Business Machines Corporation | Multilayer pillar for reduced stress interconnect and method of making same |
US7935408B2 (en) * | 2007-10-26 | 2011-05-03 | International Business Machines Corporation | Substrate anchor structure and method |
DE102007057689A1 (de) * | 2007-11-30 | 2009-06-04 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einem Chipgebiet, das für eine aluminiumfreie Lothöckerverbindung gestaltet ist, und eine Teststruktur, die für eine aluminiumfreie Drahtverbindung gestaltet ist |
US8304909B2 (en) * | 2007-12-19 | 2012-11-06 | Intel Corporation | IC solder reflow method and materials |
DE102008026839A1 (de) * | 2007-12-20 | 2009-07-02 | Osram Opto Semiconductors Gmbh | Verfahren zum Herstellen eines optoelektronischen Bauelements in Dünnschichttechnik |
KR101479512B1 (ko) | 2008-01-22 | 2015-01-08 | 삼성전자주식회사 | 반도체 패키지의 제조방법 |
FR2931586B1 (fr) * | 2008-05-22 | 2010-08-13 | St Microelectronics Grenoble | Procede de fabrication et de test d'un circuit electronique integre |
JP5249080B2 (ja) * | 2009-02-19 | 2013-07-31 | セイコーインスツル株式会社 | 半導体装置 |
TWI478303B (zh) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構 |
US8492892B2 (en) * | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
US9905524B2 (en) * | 2011-07-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures in semiconductor device and packaging assembly |
JP5962522B2 (ja) * | 2012-03-22 | 2016-08-03 | 日亜化学工業株式会社 | 半導体レーザ装置 |
US8710656B2 (en) | 2012-07-20 | 2014-04-29 | International Business Machines Corporation | Redistribution layer (RDL) with variable offset bumps |
US9706655B2 (en) * | 2013-07-09 | 2017-07-11 | Oleson Convergent Solutions Llc | Packaging for high power integrated circuits and infrared emitter arrays |
US10236265B2 (en) | 2014-07-28 | 2019-03-19 | Infineon Technologies Ag | Semiconductor chip and method for forming a chip pad |
JP6436531B2 (ja) * | 2015-01-30 | 2018-12-12 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US9786620B2 (en) * | 2015-07-27 | 2017-10-10 | Infineon Technolgies Ag | Semiconductor device and a method for manufacturing a semiconductor device |
DE102016104788B4 (de) * | 2016-03-15 | 2019-06-19 | Infineon Technologies Ag | Halbleitervorrichtung mit einer Metalladhäsions- und Barrierestruktur und Verfahren zum Herstellen einer Halbleitervorrichtung |
US9799618B1 (en) * | 2016-10-12 | 2017-10-24 | International Business Machines Corporation | Mixed UBM and mixed pitch on a single die |
US10515874B2 (en) | 2017-11-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
CN108710011A (zh) * | 2018-08-02 | 2018-10-26 | 上海泽丰半导体科技有限公司 | 一种探针卡 |
US11508704B2 (en) * | 2019-12-17 | 2022-11-22 | Seoul Viosys Co., Ltd. | Method of repairing light emitting device and display panel having repaired light emitting device |
US11545453B2 (en) * | 2021-04-19 | 2023-01-03 | Nanya Technology Corporation | Semiconductor device with barrier layer and method for fabricating the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0494131A (ja) * | 1990-08-10 | 1992-03-26 | Fuji Xerox Co Ltd | 半導体装置のバンプ構造体の形成方法 |
JPH05129305A (ja) * | 1991-11-08 | 1993-05-25 | Fuji Electric Co Ltd | 集積回路装置用バンプ電極 |
JPH07201865A (ja) * | 1993-12-31 | 1995-08-04 | Casio Comput Co Ltd | バンプを備えた半導体装置 |
JP2001118994A (ja) * | 1999-10-20 | 2001-04-27 | Matsushita Electronics Industry Corp | 半導体装置 |
WO2001035462A1 (en) * | 1999-11-05 | 2001-05-17 | Atmel Corporation | Metal redistribution layer having solderable pads and wire bondable pads |
Family Cites Families (148)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2739053A (en) * | 1951-05-07 | 1956-03-20 | Monsanto Chemicals | Dust-free herbicidal composition and method of making same |
US3259814A (en) * | 1955-05-20 | 1966-07-05 | Rca Corp | Power semiconductor assembly including heat dispersing means |
DE1182353C2 (de) * | 1961-03-29 | 1973-01-11 | Siemens Ag | Verfahren zum Herstellen eines Halbleiter-bauelements, wie Halbleiterstromtor oder Flaechentransistor, mit einer hochohmigen n-Zone zwischen zwei p-Zonen im Halbleiter-koerper |
US3105869A (en) | 1962-03-23 | 1963-10-01 | Hughes Aircraft Co | Electrical connection of microminiature circuit wafers |
US3244947A (en) * | 1962-06-15 | 1966-04-05 | Slater Electric Inc | Semi-conductor diode and manufacture thereof |
US3274458A (en) | 1964-04-02 | 1966-09-20 | Int Rectifier Corp | Extremely high voltage silicon device |
US3458925A (en) | 1966-01-20 | 1969-08-05 | Ibm | Method of forming solder mounds on substrates |
DE1614928A1 (de) * | 1966-07-19 | 1970-12-23 | Solitron Devices | Verfahren zur Kontaktierung von Halbleiter-Bauelementen |
GB1134998A (en) * | 1967-04-04 | 1968-11-27 | Marconi Co Ltd | Improvements in or relating to insulated gate field effect transistors |
US3461357A (en) | 1967-09-15 | 1969-08-12 | Ibm | Multilevel terminal metallurgy for semiconductor devices |
FR1580815A (ja) * | 1967-10-27 | 1969-09-12 | ||
NL159822B (nl) * | 1969-01-02 | 1979-03-15 | Philips Nv | Halfgeleiderinrichting. |
US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
US3625837A (en) | 1969-09-18 | 1971-12-07 | Singer Co | Electroplating solder-bump connectors on microcircuits |
US3663184A (en) * | 1970-01-23 | 1972-05-16 | Fairchild Camera Instr Co | Solder bump metallization system using a titanium-nickel barrier layer |
DE2044494B2 (de) | 1970-09-08 | 1972-01-13 | Siemens AG, 1000 Berlin u 8000 München | Anschlussflaechen zum anloeten von halbleiterbausteinen in flip chip technik |
US3760238A (en) | 1972-02-28 | 1973-09-18 | Microsystems Int Ltd | Fabrication of beam leads |
JPS49135749U (ja) | 1973-03-24 | 1974-11-21 | ||
US4113578A (en) | 1973-05-31 | 1978-09-12 | Honeywell Inc. | Microcircuit device metallization |
US3839727A (en) | 1973-06-25 | 1974-10-01 | Ibm | Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound |
US3897871A (en) | 1973-07-26 | 1975-08-05 | Lilly Co Eli | Print album storage case insert |
US3959577A (en) * | 1974-06-10 | 1976-05-25 | Westinghouse Electric Corporation | Hermetic seals for insulating-casing structures |
US4113587A (en) | 1974-08-05 | 1978-09-12 | Agency Of Industrial Science And Technology | Method for electrochemical machining |
US3986255A (en) | 1974-11-29 | 1976-10-19 | Itek Corporation | Process for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein |
US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
US3993123A (en) | 1975-10-28 | 1976-11-23 | International Business Machines Corporation | Gas encapsulated cooling module |
US4257905A (en) * | 1977-09-06 | 1981-03-24 | The United States Of America As Represented By The United States Department Of Energy | Gaseous insulators for high voltage electrical equipment |
JPS5459080A (en) * | 1977-10-19 | 1979-05-12 | Nec Corp | Semiconductor device |
US4168480A (en) | 1978-02-13 | 1979-09-18 | Torr Laboratories, Inc. | Relay assembly |
US4266282A (en) | 1979-03-12 | 1981-05-05 | International Business Machines Corporation | Vertical semiconductor integrated circuit chip packaging |
US4268282A (en) * | 1979-11-19 | 1981-05-19 | Riverwood Enterprises & Manufacturing, Ltd. | Work bench with self-contained air cleaner |
US4273859A (en) * | 1979-12-31 | 1981-06-16 | Honeywell Information Systems Inc. | Method of forming solder bump terminals on semiconductor elements |
US4473263A (en) | 1981-01-21 | 1984-09-25 | Sunstein Drew E | Circuit board mounting device and associated components |
US4382517A (en) * | 1981-02-20 | 1983-05-10 | Metropolitan Wire Corporation | Panels for holding printed circuit boards |
US4505029A (en) * | 1981-03-23 | 1985-03-19 | General Electric Company | Semiconductor device with built-up low resistance contact |
US4449580A (en) * | 1981-06-30 | 1984-05-22 | International Business Machines Corporation | Vertical wall elevated pressure heat dissipation system |
JPS58146827A (ja) * | 1982-02-25 | 1983-09-01 | Fuji Electric Co Ltd | 半導体式圧力センサ |
CH664040A5 (de) * | 1982-07-19 | 1988-01-29 | Bbc Brown Boveri & Cie | Druckgasisolierter stromwandler. |
JPS602011A (ja) * | 1983-06-14 | 1985-01-08 | 三菱電機株式会社 | ガス絶縁電気装置 |
US4532576A (en) * | 1983-08-29 | 1985-07-30 | Gte Automatic Electric Incorporated | Printed wiring board file and method of utilizing the same |
US4545610A (en) | 1983-11-25 | 1985-10-08 | International Business Machines Corporation | Method for forming elongated solder connections between a semiconductor device and a supporting substrate |
JPS6187396A (ja) * | 1984-10-05 | 1986-05-02 | 株式会社日立製作所 | 電子回路装置とその製造方法 |
US4661375A (en) * | 1985-04-22 | 1987-04-28 | At&T Technologies, Inc. | Method for increasing the height of solder bumps |
DE3685647T2 (de) * | 1985-07-16 | 1993-01-07 | Nippon Telegraph & Telephone | Verbindungskontakte zwischen substraten und verfahren zur herstellung derselben. |
FR2588121B1 (fr) * | 1985-10-02 | 1990-02-23 | Bull Sa | Procede et dispositif de soudage d'elements sur les plots correspondants d'une plaquette telle que notamment une plaquette de circuits integres de haute densite |
US4657146A (en) * | 1985-11-06 | 1987-04-14 | Richard Walters | Adjustable printed circuit board rack for supporting printed circuit boards in a horizontal or a vertical position |
US4878611A (en) | 1986-05-30 | 1989-11-07 | American Telephone And Telegraph Company, At&T Bell Laboratories | Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate |
US4763829A (en) | 1986-06-04 | 1988-08-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Soldering of electronic components |
DE3684602D1 (de) * | 1986-10-08 | 1992-04-30 | Ibm | Verfahren zum herstellen von loetkontakten fuer ein keramisches modul ohne steckerstifte. |
US4752027A (en) * | 1987-02-20 | 1988-06-21 | Hewlett-Packard Company | Method and apparatus for solder bumping of printed circuit boards |
JP2544396B2 (ja) * | 1987-08-25 | 1996-10-16 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JPS6461934A (en) | 1987-09-02 | 1989-03-08 | Nippon Denso Co | Semiconductor device and manufacture thereof |
US4855809A (en) | 1987-11-24 | 1989-08-08 | Texas Instruments Incorporated | Orthogonal chip mount system module and method |
US4897508A (en) * | 1988-02-10 | 1990-01-30 | Olin Corporation | Metal electronic package |
JPH01214141A (ja) | 1988-02-23 | 1989-08-28 | Nec Corp | フリップチップ型半導体装置 |
US5227664A (en) * | 1988-02-26 | 1993-07-13 | Hitachi, Ltd. | Semiconductor device having particular mounting arrangement |
WO1989008926A1 (en) * | 1988-03-16 | 1989-09-21 | Plessey Overseas Limited | Vernier structure for flip chip bonded devices |
US4817850A (en) * | 1988-03-28 | 1989-04-04 | Hughes Aircraft Company | Repairable flip-chip bumping |
US4840302A (en) * | 1988-04-15 | 1989-06-20 | International Business Machines Corporation | Chromium-titanium alloy |
US4893403A (en) * | 1988-04-15 | 1990-01-16 | Hewlett-Packard Company | Chip alignment method |
US4927505A (en) * | 1988-07-05 | 1990-05-22 | Motorola Inc. | Metallization scheme providing adhesion and barrier properties |
US4950623A (en) | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
CA2002213C (en) * | 1988-11-10 | 1999-03-30 | Iwona Turlik | High performance integrated circuit chip package and method of making same |
US5024372A (en) * | 1989-01-03 | 1991-06-18 | Motorola, Inc. | Method of making high density solder bumps and a substrate socket for high density solder bumps |
US4940181A (en) * | 1989-04-06 | 1990-07-10 | Motorola, Inc. | Pad grid array for receiving a solder bumped chip carrier |
US4962058A (en) | 1989-04-14 | 1990-10-09 | International Business Machines Corporation | Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit |
US5048747A (en) | 1989-06-27 | 1991-09-17 | At&T Bell Laboratories | Solder assembly of components |
JPH0357230A (ja) | 1989-07-25 | 1991-03-12 | Mitsubishi Electric Corp | 半導体基板と支持板とのロウ付け方法 |
US5135155A (en) | 1989-08-25 | 1992-08-04 | International Business Machines Corporation | Thermocompression bonding in integrated circuit packaging |
US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
US5019943A (en) * | 1990-02-14 | 1991-05-28 | Unisys Corporation | High density chip stack having a zigzag-shaped face which accommodates connections between chips |
US5251806A (en) | 1990-06-19 | 1993-10-12 | International Business Machines Corporation | Method of forming dual height solder interconnections |
US5130779A (en) * | 1990-06-19 | 1992-07-14 | International Business Machines Corporation | Solder mass having conductive encapsulating arrangement |
FR2663784B1 (fr) | 1990-06-26 | 1997-01-31 | Commissariat Energie Atomique | Procede de realisation d'un etage d'un circuit integre. |
US5130275A (en) * | 1990-07-02 | 1992-07-14 | Digital Equipment Corp. | Post fabrication processing of semiconductor chips |
US5147084A (en) | 1990-07-18 | 1992-09-15 | International Business Machines Corporation | Interconnection structure and test method |
JPH04155835A (ja) | 1990-10-18 | 1992-05-28 | Mitsubishi Electric Corp | 集積回路装置の製造方法 |
US5154341A (en) | 1990-12-06 | 1992-10-13 | Motorola Inc. | Noncollapsing multisolder interconnection |
US5113314A (en) * | 1991-01-24 | 1992-05-12 | Hewlett-Packard Company | High-speed, high-density chip mounting |
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5152451A (en) | 1991-04-01 | 1992-10-06 | Motorola, Inc. | Controlled solder oxidation process |
US5211807A (en) * | 1991-07-02 | 1993-05-18 | Microelectronics Computer & Technology | Titanium-tungsten etching solutions |
FR2678773B1 (fr) | 1991-07-05 | 1997-03-14 | Thomson Csf | Procede de cablage entre des sorties de boitier et des elements d'hybride. |
US5160409A (en) | 1991-08-05 | 1992-11-03 | Motorola, Inc. | Solder plate reflow method for forming a solder bump on a circuit trace intersection |
US5194137A (en) * | 1991-08-05 | 1993-03-16 | Motorola Inc. | Solder plate reflow method for forming solder-bumped terminals |
CA2050174A1 (en) | 1991-08-28 | 1993-03-01 | Dwight Chizen | Storage rack for cassettes and compact discs |
US5162257A (en) * | 1991-09-13 | 1992-11-10 | Mcnc | Solder bump fabrication method |
US5239447A (en) | 1991-09-13 | 1993-08-24 | International Business Machines Corporation | Stepped electronic device package |
US5372295A (en) * | 1991-10-04 | 1994-12-13 | Ryoden Semiconductor System Engineering Corporation | Solder material, junctioning method, junction material, and semiconductor device |
JP2575566B2 (ja) * | 1992-01-24 | 1997-01-29 | 株式会社東芝 | 半導体装置 |
US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
US5289925A (en) * | 1992-03-16 | 1994-03-01 | Martin Newmark | Organizational display for compact disc jewel boxes |
JP3332456B2 (ja) * | 1992-03-24 | 2002-10-07 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
US5281684A (en) * | 1992-04-30 | 1994-01-25 | Motorola, Inc. | Solder bumping of integrated circuit die |
US5744382A (en) * | 1992-05-13 | 1998-04-28 | Matsushita Electric Industrial Co., Ltd. | Method of packaging electronic chip component and method of bonding of electrode thereof |
WO1993023873A1 (en) * | 1992-05-15 | 1993-11-25 | Irvine Sensors Corporation | Non-conductive end layer for integrated stack of ic chips |
JP2718854B2 (ja) * | 1992-06-10 | 1998-02-25 | 株式会社東芝 | 半導体装置 |
US5234149A (en) | 1992-08-28 | 1993-08-10 | At&T Bell Laboratories | Debondable metallic bonding method |
US5406701A (en) * | 1992-10-02 | 1995-04-18 | Irvine Sensors Corporation | Fabrication of dense parallel solder bump connections |
US5739053A (en) * | 1992-10-27 | 1998-04-14 | Matsushita Electric Industrial Co., Ltd. | Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step |
US5327327A (en) * | 1992-10-30 | 1994-07-05 | Texas Instruments Incorporated | Three dimensional assembly of integrated circuit chips |
US5859470A (en) * | 1992-11-12 | 1999-01-12 | International Business Machines Corporation | Interconnection of a carrier substrate and a semiconductor device |
US5347428A (en) | 1992-12-03 | 1994-09-13 | Irvine Sensors Corporation | Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip |
US5479042A (en) * | 1993-02-01 | 1995-12-26 | Brooktree Corporation | Micromachined relay and method of forming the relay |
DE69426695T2 (de) | 1993-04-23 | 2001-08-09 | Irvine Sensors Corp | Elektronisches modul mit einem stapel von ic-chips |
FR2705832B1 (fr) * | 1993-05-28 | 1995-06-30 | Commissariat Energie Atomique | Procédé de réalisation d'un cordon d'étanchéité et de tenue mécanique entre un substrat et une puce hybridée par billes sur le substrat. |
US5391514A (en) * | 1994-04-19 | 1995-02-21 | International Business Machines Corporation | Low temperature ternary C4 flip chip bonding method |
US5492235A (en) * | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
DE4442960C1 (de) * | 1994-12-02 | 1995-12-21 | Fraunhofer Ges Forschung | Lothöcker für die Flip-Chip-Montage und Verfahren zu dessen Herstellung |
ATE210895T1 (de) * | 1995-03-20 | 2001-12-15 | Unitive Int Ltd | Löthöcker-herstellungsverfahren und strukturen mit einer titan-sperrschicht |
US6388203B1 (en) * | 1995-04-04 | 2002-05-14 | Unitive International Limited | Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby |
ATE240586T1 (de) * | 1995-04-05 | 2003-05-15 | Unitive Int Ltd | Eine löthöckerstruktur für ein mikroelektronisches substrat |
US5634268A (en) * | 1995-06-07 | 1997-06-03 | International Business Machines Corporation | Method for making direct chip attach circuit card |
US6224690B1 (en) * | 1995-12-22 | 2001-05-01 | International Business Machines Corporation | Flip-Chip interconnections using lead-free solders |
US5773359A (en) * | 1995-12-26 | 1998-06-30 | Motorola, Inc. | Interconnect system and method of fabrication |
US5736456A (en) * | 1996-03-07 | 1998-04-07 | Micron Technology, Inc. | Method of forming conductive bumps on die for flip chip applications |
US5751556A (en) * | 1996-03-29 | 1998-05-12 | Intel Corporation | Method and apparatus for reducing warpage of an assembly substrate |
FI962277A0 (fi) * | 1996-05-31 | 1996-05-31 | Elcoteq Network Oy | Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar |
US6027957A (en) * | 1996-06-27 | 2000-02-22 | University Of Maryland | Controlled solder interdiffusion for high power semiconductor laser diode die bonding |
US5759437A (en) * | 1996-10-31 | 1998-06-02 | International Business Machines Corporation | Etching of Ti-W for C4 rework |
US5902686A (en) * | 1996-11-21 | 1999-05-11 | Mcnc | Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures |
TW480636B (en) * | 1996-12-04 | 2002-03-21 | Seiko Epson Corp | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
US6208018B1 (en) * | 1997-05-29 | 2001-03-27 | Micron Technology, Inc. | Piggyback multiple dice assembly |
US5891756A (en) * | 1997-06-27 | 1999-04-06 | Delco Electronics Corporation | Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
US5898574A (en) * | 1997-09-02 | 1999-04-27 | Tan; Wiling | Self aligning electrical component |
US6015505A (en) * | 1997-10-30 | 2000-01-18 | International Business Machines Corporation | Process improvements for titanium-tungsten etching in the presence of electroplated C4's |
US5886393A (en) * | 1997-11-07 | 1999-03-23 | National Semiconductor Corporation | Bonding wire inductor for use in an integrated circuit package and method |
JP3718039B2 (ja) * | 1997-12-17 | 2005-11-16 | 株式会社日立製作所 | 半導体装置およびそれを用いた電子装置 |
US6436816B1 (en) * | 1998-07-31 | 2002-08-20 | Industrial Technology Research Institute | Method of electroless plating copper on nitride barrier |
US20020000665A1 (en) * | 1999-04-05 | 2002-01-03 | Alexander L. Barr | Semiconductor device conductive bump and interconnect barrier |
US6221682B1 (en) * | 1999-05-28 | 2001-04-24 | Lockheed Martin Corporation | Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects |
US6380555B1 (en) * | 1999-12-24 | 2002-04-30 | Micron Technology, Inc. | Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components |
US6231743B1 (en) * | 2000-01-03 | 2001-05-15 | Motorola, Inc. | Method for forming a semiconductor device |
US6346469B1 (en) * | 2000-01-03 | 2002-02-12 | Motorola, Inc. | Semiconductor device and a process for forming the semiconductor device |
US6335104B1 (en) * | 2000-02-22 | 2002-01-01 | International Business Machines Corporation | Method for preparing a conductive pad for electrical connection and conductive pad formed |
US6521996B1 (en) * | 2000-06-30 | 2003-02-18 | Intel Corporation | Ball limiting metallurgy for input/outputs and methods of fabrication |
TW449813B (en) * | 2000-10-13 | 2001-08-11 | Advanced Semiconductor Eng | Semiconductor device with bump electrode |
US20020056742A1 (en) * | 2000-11-10 | 2002-05-16 | Rinne Glenn A. | Methods and systems for attaching substrates to one another using solder structures having portions with different melting points |
US6668449B2 (en) * | 2001-06-25 | 2003-12-30 | Micron Technology, Inc. | Method of making a semiconductor device having an opening in a solder mask |
US6667195B2 (en) * | 2001-08-06 | 2003-12-23 | United Microelectronics Corp. | Laser repair operation |
US6853076B2 (en) * | 2001-09-21 | 2005-02-08 | Intel Corporation | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same |
US20030107137A1 (en) * | 2001-09-24 | 2003-06-12 | Stierman Roger J. | Micromechanical device contact terminals free of particle generation |
US6762122B2 (en) * | 2001-09-27 | 2004-07-13 | Unitivie International Limited | Methods of forming metallurgy structures for wire and solder bonding |
US6749760B2 (en) * | 2001-10-26 | 2004-06-15 | Intel Corporation | Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead |
US6743660B2 (en) * | 2002-01-12 | 2004-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of making a wafer level chip scale package |
EP1351298B1 (de) * | 2002-03-28 | 2007-12-26 | Infineon Technologies AG | Method for producing a semiconductor wafer |
US6960828B2 (en) * | 2002-06-25 | 2005-11-01 | Unitive International Limited | Electronic structures including conductive shunt layers |
-
2003
- 2003-12-04 TW TW092134135A patent/TWI225899B/zh not_active IP Right Cessation
-
2004
- 2004-02-17 US US10/780,529 patent/US7081404B2/en not_active Expired - Lifetime
- 2004-02-17 KR KR1020057015113A patent/KR20050105223A/ko not_active Application Discontinuation
- 2004-02-17 JP JP2006503894A patent/JP2006518115A/ja active Pending
- 2004-02-17 WO PCT/US2004/005818 patent/WO2004075265A2/en not_active Application Discontinuation
- 2004-02-17 CN CNA2004800104255A patent/CN1784775A/zh active Pending
- 2004-02-17 EP EP04711949A patent/EP1595283A2/en not_active Withdrawn
- 2004-02-18 TW TW093103936A patent/TW200507120A/zh unknown
-
2006
- 2006-06-02 US US11/446,341 patent/US7579694B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0494131A (ja) * | 1990-08-10 | 1992-03-26 | Fuji Xerox Co Ltd | 半導体装置のバンプ構造体の形成方法 |
JPH05129305A (ja) * | 1991-11-08 | 1993-05-25 | Fuji Electric Co Ltd | 集積回路装置用バンプ電極 |
JPH07201865A (ja) * | 1993-12-31 | 1995-08-04 | Casio Comput Co Ltd | バンプを備えた半導体装置 |
JP2001118994A (ja) * | 1999-10-20 | 2001-04-27 | Matsushita Electronics Industry Corp | 半導体装置 |
WO2001035462A1 (en) * | 1999-11-05 | 2001-05-17 | Atmel Corporation | Metal redistribution layer having solderable pads and wire bondable pads |
JP2003514380A (ja) * | 1999-11-05 | 2003-04-15 | アトメル・コーポレイション | はんだ付けが可能なパッドおよびワイヤボンディングが可能なパッドを有する金属再配置層 |
Also Published As
Publication number | Publication date |
---|---|
US20060231951A1 (en) | 2006-10-19 |
KR20050105223A (ko) | 2005-11-03 |
US7081404B2 (en) | 2006-07-25 |
US20040209406A1 (en) | 2004-10-21 |
WO2004075265A3 (en) | 2004-11-04 |
EP1595283A2 (en) | 2005-11-16 |
CN1784775A (zh) | 2006-06-07 |
TW200416305A (en) | 2004-09-01 |
TWI225899B (en) | 2005-01-01 |
US7579694B2 (en) | 2009-08-25 |
TW200507120A (en) | 2005-02-16 |
WO2004075265A2 (en) | 2004-09-02 |
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