JP5113177B2 - 半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 - Google Patents
半導体素子およびその製造方法、ならびにその半導体素子を実装する実装構造体 Download PDFInfo
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- JP5113177B2 JP5113177B2 JP2009531227A JP2009531227A JP5113177B2 JP 5113177 B2 JP5113177 B2 JP 5113177B2 JP 2009531227 A JP2009531227 A JP 2009531227A JP 2009531227 A JP2009531227 A JP 2009531227A JP 5113177 B2 JP5113177 B2 JP 5113177B2
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Description
Y 実装構造体
P ハンダペースト(導電性部材)
10 半導体基板(基板)
20 導電層
30 パッシベーション層(保護層)
30A 開口部
40,41 バリアメタル層
40A リンリッチ部
42 (バリアメタル層41の)第1層
43 (バリアメタル層41の)第2層
50 ハンダバンプ(導電性バンプ)
60 金属間化合物層
70 有機被膜
80 回路基板
81 基板
82 回路パターン
83 パッド部
<第1実施形態>
図1Aは、本発明の第1実施形態に係る半導体素子X1の概略構成を示す要部断面図である。図1Bは、図1Aの一部を拡大して示す断面図である。図2は、半導体素子X1の概略構成を示す平面図である。
半導体素子X1は、半導体基板10と、導電層20と、保護層としてのパッシベーション層30と、バリアメタル層40と、ハンダバンプ50とを有している。
導電層20は、半導体基板10の領域20a上に位置している。この導電層20は、該半導体基板10の集積回路を構成する配線パターンに対して電気的に接続されている。導電層20を形成する材料としては、例えばアルミニウム(Al)、銅(Cu)、Al−Cu、Al−Si、およびAl−Si−Cuなどの金属材料が挙げられる。導電層20の形成厚さは、例えば0.2[μm]以上2.0[μm]以下に設定される。
この第1実施形態では、バリアメタル層40を形成する組成原子の各々の含有量を電解放射型オージェ電子分光法(Field Emission Auger Electron Spectroscopy;FE−AES)を用いて測定した。より具体的には、まず、半導体素子X1から半導体基板10の一部と、導電層20の一部と、パッシベーション層30の一部と、一組のバリアメタル層40およびハンダバンプ50とを取り出し、測定試料とした。次に、平面視におけるハンダバンプ50の中心を含めるようにして、この測定試料の断面を露出させた。次に、この測定試料の断面に電子線を照射して、AES法を用いて当該断面の表面分析を行い、バリアメタル層40を形成する組成原子の各々の含有量を測定した。このようにして、バリアメタル層40を形成する組成原子の各々の含有量を測定することができる。
本明細書においては、バリアメタル層40の上面40aのうち金属間化合物60を介してハンダバンプ50に接合されている部分をハンダバンプ50の形成領域という。ハンダバンプ50がバリアメタル層40の表面全体を覆う好ましい形態では、当該上面40a全体がハンダバンプ50の形成領域となる。
すなわち、半導体素子X1では、外気が相対的に浸入し難い中央部40bにおいてリンリッチ部位40Aの厚さが相対的に小さくされていることにより、バリアメタル層40とハンダバンプ50との接合部分における機械的強度を充分に確保することができる。
また、外気が相対的に侵入し易い周縁部40cにおいてリンリッチ部位40Aの厚さが相対的に大きくされていることにより、バリアメタル層40(ひいては導電層20)の耐食性も充分に確保することができる。
したがって、半導体素子X1は、機械的な信頼性および電気的な信頼性の両方を優れたものとすることができる。
半導体素子X1の製造方法では、まず、図3Aに示すように、半導体基板10上に、該半導体基板10の集積回路を構成する配線パターン(図示せず)に対して電気的に接続するようにして、導電層20を形成する。具体的には、まず、成膜技術により導電膜を成膜する。次に、該導電膜を微細加工技術によって所望のパターンに加工することで、導電層20が形成される。ここで、成膜技術としては、例えばスパッタリング法と、蒸着法とが挙げられ、微細加工技術としては、例えばフォトリソグラフィを用いる方法が挙げられる。
図3Bに示すように、半導体基板10および導電層20上に、厚み方向に貫通する開口部30Aを有するパッシベーション層30を形成する。具体的には、まず、成膜技術によって半導体基板10および導電層20の全体を覆うようにしてパッシベーション層30を形成する。次に、微細加工技術によってパッシベーション層30に開口部30Aを形成し、電極層20の一部を露出させることで、開口部30Aを有するパッシベーション層30が形成される。ここで、成膜技術としては、例えばスパッタリング法と、蒸着法とが挙げられ、微細加工技術としては、例えばフォトリソグラフィを用いる方法が挙げられる。
図3Cに示すように、導電層20およびパッシベーション層30が形成された半導体基板10に残留する無機残渣または有機残渣を、例えばウェットエッチングにより除去する。具体的には、エッチング液中に所定時間浸漬することによって、各種残渣の除去が行われる。なお、無機残渣を除去するためのエッチング液としては、例えばフッ化水素、硫酸、および塩化水素を含有する溶液が挙げられ、有機残渣を除去するための溶液としては、例えばエタノール、イソプロピルアルコール、およびアセトンなどの溶液が挙げられる。なお、有機残渣の除去は、ウェットエッチングに代えてO2アッシングなどにより行うこともできる。
図4Aに示すように、残渣除去工程を経た半導体基板10を水洗する。具体的には、残渣除去工程を経た半導体基板10を、洗浄用水の中に浸漬することによって水洗される。
図4Bに示すように、水洗工程を経た半導体基板10にジンケート処理を施す。具体的には、第1水洗工程を経た半導体基板10を、ジンケート処理液中に所定時間浸漬する。このジンケート処理液中に亜鉛が含有されており、開口部30Aにおける導電層20のアルミニウムを亜鉛と置換させ、その後に亜鉛を堆積させることによって、該導電層20の表面に亜鉛膜21を形成する。なお、ジンケート処理は、所定膜厚の亜鉛膜21が堆積するまで繰り返し行ってもよい。
図4Cに示すように、ジンケート処理が施された半導体基板10の導電層20上に、バリアメタル層40としての無電解ニッケルメッキ層を形成する。具体的には、ジンケート処理が施された半導体基板10を無電解ニッケルめっき液中に所定時間浸漬する。この無電解ニッケルめっき液中で、導電層20の表面に形成された亜鉛膜21の亜鉛と無電解ニッケルめっき液中のニッケルとを置換させ、その後にニッケルを堆積させることによって、該導電層20上に無電解ニッケルメッキ層(バリアメタル層40)が形成される。なお、無電解ニッケルめっき液としては、例えば還元剤として次亜リン酸ナトリウムなどを含有するとともに、ニッケル塩として硫酸ニッケルや塩化ニッケルなどを含有する溶液が挙げられる。この無電解ニッケルめっき液の中でも、ニッケル塩としては、半導体に対する影響を低減する観点から、硫酸ニッケルを含有する溶液が好ましい。また、無電解ニッケルめっき液の水素イオン指数(pH)の値は、無電解ニッケルめっきをより効率的に行う観点から、アンモニアなどのpH調整剤によりpHの値を4以上5以下の範囲に調整するのが好ましい。
第1水洗工程と同様にして、バリアメタル層形成工程を経た半導体基板10を水洗する。具体的には、バリアメタル層形成工程を経た半導体基板10を、洗浄用水の中に浸漬することによって水洗される。
図5Aに示すように、無電解ニッケルめっき層(バリアメタル層40)が形成された半導体基板10の該無電解ニッケルメッキ層上に、有機被膜70を形成する。具体的には、まず、無電解ニッケルめっき層(バリアメタル層40)が形成された半導体基板10を有機溶液中に所定時間浸漬する。次に、バリアメタル層40の表面に有機溶液を被着させた状態で乾燥することによって、有機被膜70が形成される。有機溶液としては、例えば、純水と脂環族酸と脂肪族アミン誘導体とを含む溶液が挙げられる。第1実施形態では、この有機溶液の蒸発温度が例えば200[℃]以上240[℃]以下に設定される。なお、有機被膜70の蒸発温度の測定は、示差走査熱量測定装置(型番:DSC−6200、セイコーインスツルメンツ製)により、昇温速度が10[℃/min]で空気雰囲気中にて行われる。
図5Bに示すように、有機被膜形成工程を経た半導体基板10の有機被膜50上に、導電性部材としてハンダペーストPを配置(もしくは塗布)する。具体的には、有機被膜形成工程を経た半導体基板10におけるバリアメタル層40上に位置する有機被膜50上に、スクリーン印刷などにより印刷することによって、ハンダペーストPが配置される。ハンダペーストPとしては、その融点が有機被膜70の蒸発温度より低いものが挙げられる。このハンダペーストPの融点温度としては、例えば160[℃]以上230[℃]以下の範囲のうち、有機被膜70の蒸発温度より低いものが用いられる。また、ハンダペーストPとしては、耐環境性の観点からSn/3.0Ag/0.5CuなどのPbフリーハンダが好ましい。なお、ハンダペーストPの融点としては、固相線温度の値を採用する。
図5Cに示すように、導電性部材配置工程を経た半導体基板10を、所定温度で加熱することによって、バリアメタル層40上にハンダバンプ50を形成する。具体的には、まず、ハンダペーストPが塗布された半導体基板10を、ヒータを備えるリフロー炉内に配置し、該ヒータにより加熱する。このリフロー炉内では、例えば245[℃]以上の温度で例えば有機被膜70の全てを揮発させるのに要する時間の加熱が行われ、略球状のハンダバンプ50が形成される。
図6Aは、本発明の第2実施形態に係る半導体素子X2の概略構成を示す要部断面図である。図6Bは、図6Aの一部を拡大して示す断面図である。
半導体素子X2は、半導体素子X1のバリアメタル層40に代えてバリアメタル層41を有する点において、半導体素子X1と異なる。半導体素子X2の他の構成については、半導体素子X1に関して上述したのと同様である。
まず、図7Aに示すように、ジンケート処理が施された半導体基板10の導電層20上にバリアメタル層41の第1層42としての無電解ニッケルメッキ層を形成する。具体的には、まず、ジンケート処理が施された半導体基板10を、第1無電解ニッケルめっき液中に所定時間浸漬する。この無電解ニッケルメッキ液中で、導電層20の表面に形成された亜鉛膜の亜鉛と無電解ニッケルめっき液中のニッケルとを置換させ、その後にニッケルを堆積させることによって、該導電層20上に無電解ニッケルメッキ層(バリアメタル層41の第1層42)が形成される。なお、第1無電解ニッケルめっき液としては、還元剤として次亜リン酸ナトリウムなどを含有するとともに、ニッケル塩として硫酸ニッケルや塩化ニッケルなどを含有する溶液などが挙げられる。この無電解ニッケルめっき液の中でもニッケル塩としては、半導体に対する影響を低減する観点から、硫酸ニッケルを含有する溶液が好ましい。また、第1無電解ニッケルめっき液の水素イオン指数(pH)の値は、無電解ニッケルめっきをより効率的に行う観点から、アンモニアなどのpH調整剤によりpHの値を4以上5以下の範囲に調整するのが好ましい。
第2実施形態に係る半導体素子X2の製造方法は、第1実施形態の半導体素子X1の製造方法と同様の効果を奏する。
図8は、本発明に係る第3実施形態の実装構造体Yの概略構成を示す要部断面図である。
この第3実施形態の実装構造体Yは、第1実施形態の半導体素子X1を回路基板80に実装したものである。この実装構造体Yは、半導体素子X1と、回路基板80とを備えている。なお、第3実施形態では、半導体素子X1を採用して例により説明するが、半導体素子X1を半導体素子X2に置き換えてもよい。
基板81は、回路パターン82およびパッド部83の支持母材として機能するものである。
回路パターン82は、図示しない機能素子に電気的に接続されており、基板81上に形成されている。回路パターン82を形成する材料としては、例えばAl、Cu、Al−Cu、Al−Si、およびAl−Si−Cuなどの金属材料が挙げられる。
パッド部83は、半導体素子X1の導電層20に電気的に接続する機能を有する部位である。このパッド部83は、回路パターン82に電気的に接続されている。このパッド部83にハンダバンプ60を介して半導体素子X1が実装されている。
実装構造体Yは、半導体素子X1を実装しているので、半導体素子X1の有する効果を享受することができる。したがって、実装構造体では、機械的な信頼性および電気的な信頼性の両方を優れたものとすることができる。
しかしながら、第1実施形態で説明した製造方法は、バリアメタル層40にリンリッチ部位を持たない半導体素子の製造に適用してもよく、その場合、金属間化合物層60の厚さを薄くできる。
<第4実施形態>
本発明に係る第4実施形態に係る半導体素子X3の製造方法は、バリアメタル層40上に有機被膜70を形成する有機被膜形成工程と、有機被膜70の蒸発温度より低い融点のハンダペーストPを有機被膜70上に配置する導電性部材配置工程と、ハンダペーストPを溶融させるとともに、有機被膜70を揮発させて、バリアメタル層40上にハンダバンプ50を形成するバンプ形成工程とを含んでいる。
図12は、第4実施形態の製造方法によって作製された半導体素子X3の概略構成を示す要部拡大断面図である。
本製造方法では、パッシベーション層30における開口部30Aの周縁部上にもバリアメタル層40を形成するので、導電層20における腐食などの発生を低減することができる。
例えば、第4実施形態の製造方法において、ハンダバンプ50に有機被膜70の揮発成分を含有させてもよい。このような製造方法においても、上述と同様の効果を奏する。また、この場合において有機被膜70の揮発成分として脂環族アミンを含むようにすると、アミンを構成するNがロジンフラックスと同様の機能を奏するため、ロジンフラックスを使用した場合と同様の効果を得ることができる。
Claims (6)
- 基板と、該基板上に設けられた導電層と、前記導電層上に設けられた開口部を有する保護層と、前記開口部において前記導電層に接合されたバリアメタル層と、該バリアメタル層上に形成された導電性バンプとを有しており、
前記バリアメタル層は、リンを含有しており、かつ該リン含有率が他の部分より大きいリンリッチ部位を含んでおり、
該リンリッチ部位は、前記導電性バンプ側の表面部に位置し、かつ前記導電性バンプの形成領域の周縁部における厚さが当該形成領域の中央部における厚さより大きいことを特徴とする半導体素子。 - 前記バリアメタル層と前記導電性バンプとの間に、前記バリアメタル層の構成材料と前記導電性バンプの構成材料とを含んでなる金属間化合物層を更に有しており、
前記バリアメタル層は、前記リンリッチ部位以外の部位が前記リンリッチ部位を貫通して前記金属間化合物層に繋がっていることを特徴とする請求項1に記載の半導体素子。 - 基板と、該基板上に設けられた導電層と、前記導電層上に設けられた開口部を有する保護層と、前記開口部において前記導電層に接合されたバリアメタル層と、該バリアメタル層上に形成された導電性バンプとを有しており、
前記バリアメタル層は、リンを含有しており、該リン含有率が他の部分より大きいリンリッチ部位を含んでおり、
該リンリッチ部位は、前記導電性バンプ側の表面部に位置し、かつ前記導電性バンプの形成領域の周縁部のみに位置することを特徴とする半導体素子。 - 前記バリアメタル層は、前記開口部周縁の前記保護層上にも形成されていることを特徴とする請求項1から3のいずれかに記載の半導体素子。
- 前記バリアメタル層のリンリッチ部位以外の部位は、前記リンリッチ部位に比べてリン含有率が小さい、第1部位と、第2部位とを含んでおり、
前記第1部位は、前記第2部位に比べてリン含有率が小さく、前記導電層側の表面部に位置していることを特徴とする請求項1から4のいずれかに記載の半導体素子。 - 請求項1から5のいずれかに記載の半導体素子と、配線電極を有する基体とを有し、
前記基体上には、前記配線電極に電気的に接続されたパッド部を備え、
該パッド部と、前記半導体素子の前記導電性バンプとが接合されていることを特徴とする実装構造体。
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