CN101796622B - 半导体元件、其制造方法及实装其的实装构造体 - Google Patents

半导体元件、其制造方法及实装其的实装构造体 Download PDF

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CN101796622B
CN101796622B CN2008801056350A CN200880105635A CN101796622B CN 101796622 B CN101796622 B CN 101796622B CN 2008801056350 A CN2008801056350 A CN 2008801056350A CN 200880105635 A CN200880105635 A CN 200880105635A CN 101796622 B CN101796622 B CN 101796622B
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metal screen
layer
screen layer
semiconductor element
forms
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CN101796622A (zh
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加藤谦一
下赤善男
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Kyocera Corp
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Kyocera Corp
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Abstract

本发明提供一种在机械可靠性及电可靠性两方面均优越的半导体元件及该半导体元件的实装结构体。该半导体元件具有：基板；设于基板上的导电层；设于导电层上且具有开口部的保护层；在开口部与导电层接合的金属屏蔽层；形成于金属屏蔽层上的导电性凸起。该金属屏蔽层含有磷，且具有含磷率大于其它部分的富磷部位。该富磷部位位于导电性凸起侧的表面部，且导电性凸起的形成区域的周缘部的厚度大于该形成区域的中央部的厚度。

Description

半导体元件、其制造方法及实装其的实装构造体
技术区域
本发明涉及一种具有焊锡凸起等的导电性凸起的半导体元件、其制造方法及实装该半导体元件的实装结构体。
背景技术
近年来，由于要求半导体封装的高密度实装，故已从采用丝焊的COB(chip on Board)实装法向采用倒焊的倒装芯片实装法转移。
作为通过这样的倒装芯片实装法实装于配线基板的半导体芯片包括具有半导体基板、电极、钝化层、金属屏蔽层及焊锡凸起者。该电极位于半导体基板上。该钝化层位于电极上，且具有沿厚度方向贯通的开口部。该金属屏蔽层在钝化层的开口部的下方位于电极上，且含有磷(P)。该焊锡凸起形成于金属屏蔽层上。
通常，在这样构成的半导体芯片的金属屏蔽层中，在其焊锡凸起侧的表面部具有富磷部位。该富磷部位是指含磷率相对较大的部位。然而，富磷部位的机械性强度比起其它部位相对较低。因此，若金属屏蔽层的富磷部位的厚度增大，则焊锡凸起与金属屏蔽层的接合部分的机械性强度会降低。由此，例如热应力反复作用在实装半导体芯片的配线基板时，会有该接合部分产生裂痕，进而使焊锡凸起剥离的情况产生。为了改善所述问题，用以整体地限制富磷部位的厚度的技术已在专利文献1中公开。
具体而言，根据专利文献1，可如下述所示地制造出半导体芯片。首先，在半导体基板上形成电极垫。该电极垫为由例如铝等导电性材料形成。接着，以覆盖半导体基板的电极垫形成面中未由该电极垫覆盖的部位及该电极垫的外周部的方式形成钝化膜。然后，通过非电解镀镍，在电极垫上的未由钝化膜覆盖的部位形成镍层。接着，通过非电解镀金，在镍层上形成金层。然后，通过在金层上配设焊锡并加热来形成焊锡凸起。这样，制造出具有凸起的半导体芯片。另外，镍层与金层作为焊锡凸起的基底的金属屏蔽层而发挥作用。
若通过专利文献1记载的制造方法制造半导体芯片，在形成焊锡凸起时，可通过金层减少构成镍层的镍向焊锡凸起内扩散的情况。由此，可减少相对较脆的金属互化物层厚厚地形成在镍与焊锡的界面的情况，从而可提高可靠性。
专利文献1：日本特开2004-273959号公报
然而，在所述半导体芯片中，若整体地缩小富磷层的厚度，则会有半导体芯片的耐腐蚀性降低的情况产生。这是因为磷偏析的区域(富P层)比起镍层的其它部位具有高耐腐蚀性的缘故。尤其是，在钝化膜的开口部附近，外部空气容易从该钝化层与镍层之间侵入，故会有容易产生腐蚀的倾向。
发明内容
本发明为在这种情况下所想出的，其目的在于提供一种在机械可靠性及电可靠性两方面均优越的半导体元件、其制造方法及该半导体元件的实装结构体。
本发明的第一半导体元件具有基板、导电层、保护层、金属屏蔽层、导电性凸起。该导电层设于基板上。该保护层设于导电层上且具有开口部。该金属屏蔽层在所述开口部与导电层接合。该导电性凸起形成于金属屏蔽层上。另外，所述金属屏蔽层含有磷，且包含所述含磷率大于其它部分的富磷部位。该富磷部位位于导电性凸起侧的表面部，且导电性凸起的形成区域的周缘部的厚度大于该形成区域的中央部的厚度。
本发明的第二半导体元件具有基板、导电层、保护层、金属屏蔽层、导电性凸起。该导电层设于基板上。该保护层设于导电层上且具有开口部。该金属屏蔽层在所述开口部与导电层接合。该导电性凸起形成于金属屏蔽层上。另外，所述金属屏蔽层含有磷，且包含所述含磷率大于其它部分的富磷部位。该富磷部位位于导电性凸起侧的表面部，且仅位于导电性凸起的形成区域的周缘部。
本发明的实装结构体具有本发明的半导体元件及具有配线电极的基体。在该基体上设有与所述配线电极电连接的衬垫部。该衬垫部与本发明的半导体元件的导电性凸起接合。
本发明的半导体元件的制造方法具有导电层形成工序、保护层形成工序、金属屏蔽层形成工序、有机覆盖膜形成工序、导电性构件配置工序、凸起形成工序。在该导电层形成工序中，在基板的主面形成导电层。在该保护层形成工序中，形成覆盖导电层且在导电层上具有开口部的保护层。在该金属屏蔽层形成工序中，形成在开口部与导电层接合的金属屏蔽层。在该有机覆盖膜形成工序中，在金属屏蔽层上形成有机覆盖膜。在该导电性构件配置工序中，在有机覆盖膜上配置导电性构件。该导电性构件的熔点低于有机覆盖膜的蒸发温度。在该凸起形成工序中，使导电性构件熔融并且使有机覆盖膜挥发，从而在金属屏蔽层上形成导电性凸起。
本发明的半导体元件、其制造方法及实装结构体能够在机械可靠性及电可靠性两方面均优越。
附图说明
图1为表示本发明的第一实施方式的半导体元件的概略构造的主要部分截面图。
图1B为放大表示图1A的一部分的截面图。
图2为表示图1A所示的半导体元件的概略构造的俯视图。
图3A为表示图1A所示的半导体元件的制造过程的一工序的主要部分截面图。
图3B为表示图3A的下一工序的主要部分截面图。
图3C为表示图3B的下一工序的主要部分截面图。
图4A为表示图3C的下一工序的主要部分截面图。
图4B为表示图4A的下一工序的主要部分截面图。
图4C为表示图4B的下一工序的主要部分截面图。
图5A为表示图4C的下一工序的主要部分截面图。
图5B为表示图5A的下一工序的主要部分截面图。
图5C为表示图5B的下一工序的主要部分截面图。
图6A为表示本发明的第二实施方式的半导体元件的概略构造的主要部分截面图。
图6B为放大表示图6A的一部分的截面图。
图7A为表示图6A所示的半导体元件的制造过程的一工序的主要部分截面图。
图7B为表示图7A的下一工序的主要部分截面图。
图8为表示本发明的第三实施方式的实装结构体的概略构造的主要部分截面图。
图9A为表示本发明的第一实施方式的半导体元件的变形例的主要部分截面图。
图9B为放大表示图9A的一部分的截面图。
图10A为表示本发明的第一实施方式的半导体元件的另一变形例的主要部分截面图。
图10B为放大表示图10A的一部分的截面图。
图11为表示本发明的第一实施方式的半导体元件的又一变形例的主要部分截面图。
图12为表示通过本发明的第四实施方式的制造方法制作的半导体元件的概略构造的主要部分放大截面图。
附图标号说明
X1、X2、X3、X1A、X1B、X1C半导体元件
Y实装结构体
P焊锡膏(导电性构件)
10半导体基板(基板)
20导电层
30钝化层(保护层)
30A开口部
40、41金属屏蔽层
40A富磷部位
42(金属屏蔽层41的)第一层
43(金属屏蔽层41的)第二层
50焊锡凸起(导电性凸起)
60金属互化物层
70有机覆盖膜
80电路基板
81基板
82电路图案
83衬垫部
具体实施方式
以下，参照附图说明本发明的实施方式。
<第一实施方式>
图1A为表示本发明第一实施方式的半导体元件X1的概略构造的主要部分截面图。图1B为放大表示图1A的一部分的截面图。图2为表示半导体元件X1的概略构造的平面图。
半导体元件X1具有半导体基板10、导电层20、作为保护层的钝化层30、金属屏蔽层40、焊锡凸起50。
半导体基板10为通过例如硅(Si)等半导体材料形成。该半导体基板10在其表面及内部形成有集成电路(未图示)。另外，半导体基板10不仅限于单层结构，也可为多层的层叠结构。
导电层20位于半导体基板10的区域20a上。该导电层20相对于构成该半导体基板10的集成电路的配线图案电连接。形成导电层20的材料可举例如：铝(Al)、铜(Cu)、Al-Cu、Al-Si、及Al-Si-Cu等金属材料。导电层20的形成厚度设定为例如0.2[μm]以上2.0[μm]以下。
钝化层30发挥作为降低半导体元件X1的腐蚀的保护层的功能。该钝化层30除了位于导电层20的形成区域20a上的开口部30A以外，几乎遍及整个表面。该开口部30A沿厚度方向贯通钝化层30。该开口部30A的俯视情况下形状，就缓和应力的观点来看可为大致圆形状，而就制造成本的观点来看则可为n边形状(n为4以上的自然数)。形成钝化层30的材料可举例如：氮化硅、氧化硅、及聚酰亚胺等电绝缘材料。在第一实施方式中，钝化层30形成为也可覆盖导电层20的一部分(外周区域)。
金属屏蔽层40设于导电层20上。该金属屏蔽层40经由开口部30A与导电层20电连接。第一实施方式的金属屏蔽层40为含有磷的镍(Ni)的单层结构。该金属屏蔽层40构成为，其上表面40a位于比钝化层30的上表面30a更靠上方的位置。另外，第一实施方式的金属屏蔽层40也向开口部30A周缘的钝化层30上延伸。在该金属屏蔽层40中，相对于钝化层30的上表面30a的厚度，为从俯视情况下的周端朝向中央增大。另外，金属屏蔽层40的含磷率为5[wt％]以上10[wt％]以下(即所谓的中磷镍)。该范围的金属屏蔽层40的硬度在例如维氏硬度中为500[HV]以上600[HV]以下。该维氏硬度为JIS规格Z2244：2003所规定，且该规格为以ISO规格6507-1：1997为基准。
另外，第一实施方式的金属屏蔽层40构成为，使富磷部位40A(含磷率为10[wt％]以上的部位)少量存在于其焊锡凸起50侧的表面部，且该富磷部位40A通过构成该金属屏蔽层40的镍的一部分向焊锡凸起50一侧扩散而产生。该富磷部位40A的厚度形成为，焊锡凸起50的形成区域(金属屏蔽层40的上表面40a与焊锡凸起50相对的区域)的周缘部40c的厚度大于焊锡凸起50的形成区域的中央部40b的厚度。例如，在该富磷部位40A中，中央部40b的厚度平均值设定为10[nm]以上150[nm]以下，且周缘部40c的厚度平均值设定为300[nm]以上800[nm]以下。另外，该富磷部位40A的俯视情况下的周端40Aa也向开口部30A周缘的钝化层30上延伸。作为该焊锡凸起50的形成区域的中央部40b可举出，在金属屏蔽层40的上表面40a的与焊锡凸起50相对的区域中包含俯视情况下的金属屏蔽层40的中心且金属屏蔽层40相对于导电层20的厚度T40大致一定的部位的上表面40a。在此，大致一定是指，相对于在俯视情况下位于钝化层30的开口部30A内侧的金属屏蔽层40的厚度T40的平均值，厚度T40的值在80％以上120％以下的范围内。作为该焊锡凸起50的形成区域的周缘部40c，在金属屏蔽层40的上表面40a的与焊锡凸起50相对的区域中，位于从周端40Aa到钝化层30的开口部30A的内周侧附近之间的部位。作为该周缘部40c的位置可举，从周端40Aa朝向钝化层30的开口部30A的中心侧移动2.5[μm]以下的区域。该富磷部位40A与金属屏蔽层40相比含有更多的磷，所以电阻率增大，因此，当以例如电子扫描型显微镜(SEM)观察时，存在观察出明度不同的情况。另外，就更提高对外部环境的耐腐蚀性的观点来看，优选在该富磷部位40A的厚度中，位于钝化层30的上表面30a的部位的厚度大于位于开口部30A上的部位的厚度。另外，在本发明的金属屏蔽层40中，也会存在例如含磷率虽比其它部位相对较大但含磷率却不到10[wt％]，使得富磷部位40A实质上不存在的情况、或局部薄薄地形成富磷部位40A的情况。
在第一实施方式中，使用场致发射型俄歇电子能谱学(Field EmissionAuger Electron Spectroscopy；FE-AES)测定形成金属屏蔽层40的组成原子的各自的含量。更具体而言，首先，从半导体元件X1取出部分半导体基板10、部分导电层20、部分钝化层30、一组金属屏蔽层40及焊锡凸起50，来作为测定试样。接着，以包含俯视情况下的焊锡凸起50的中心的方式，使该测定试样的截面露出。然后，对该测定试样的截面照射电子束，并使用AES法进行该截面的表面分析，来测定形成金属屏蔽层40的组成原子的各自的含量。这样，可以测出形成金属屏蔽层40的组成原子的各自的含量。
焊锡凸起50位于金属屏蔽层40上。该焊锡凸起50相对于金属屏蔽层40电连接。该焊锡凸起50形成为覆盖金属屏蔽层40的表面整体。就导电性及对金属屏蔽层40的密接性的观点来看，形成焊锡凸起50的材料可举例如：Pb-Sn(锡)系焊锡等的含铅焊锡；含有Sn、Ag、Cu、Bi(铋)、In(铟)、Zn(锌)、Ni、Ge(锗)及Au等任一种金属而成的无铅焊锡；银焊料；铜焊料；磷铜焊料；黄铜焊料；铝焊料；镍焊料。就接合强度或耐环境性的观点来看，在这些形成焊锡凸起50的材料中，特别优选无铅焊锡。在此，无铅焊锡是指，含铅量为0.10[wt％]以下的焊锡，且该数值为JIS规格Z3282：2006或ISO/TC44/SC12所规定。该焊锡凸起50的尺寸可举例如，在俯视情况下的直径为25[μm]以上85[μm]以下的范围内。
另外，在第一实施方式的金属屏蔽层40与焊锡凸起50之间设有金属互化物层60。该金属互化物层60通过形成金属屏蔽层40的镍与形成焊锡凸起50的焊锡扩散而形成。该金属互化物层60的厚度为，在可确保适当接合的范围内例如为4.0[μm]以下，从而形成相当小的厚度。另外，作为形成金属互化物层60的材料，例如在采用含磷的Ni作为金属屏蔽层40且采用含铜的无铅焊锡作为焊锡凸起50的情况下，可举出(Cu、Ni)6Sn5。
在本说明书中，将金属屏蔽层40的上表面40a中经由金属互化物层60接合于焊锡凸起50的部分称为焊锡凸起50的形成区域。在焊锡凸起50覆盖金属屏蔽层40的表面整体的理想状态下，该上表面40a整体成为焊锡凸起50的形成区域。
半导体元件X1具有半导体基板10、位于半导体基板10的主面上的导电层20、设于导电层20上并且具有沿厚度方向贯通的开口部30A的钝化层30、设置成用以堵塞开口部30A并且经由开口部30A与导电层接合20的金属屏蔽层40、形成于金属屏蔽层40上的焊锡凸起50。
在此，尤其是在第一实施方式中，金属屏蔽层40位于焊锡凸起50侧的表面部，且含有含磷率相对较大的富磷部位40A。在该富磷部位40A中，焊锡凸起50的形成区域的周缘部40c的厚度大于该形成区域的中央部40b的厚度，从而具有以下所述的特有效果。
即，在半导体元件X1中，通过相对减小富磷部位40A在外部空气相对较难侵入的中央部40b的厚度，可充分确保金属屏蔽层40与焊锡凸起50的接合部分的机械性强度。
另外，通过相对增大富磷部位40A在外部空气相对较易侵入的周缘部40c的厚度，也可充分确保金属屏蔽层40(甚至是导电层20)的耐腐蚀性。
因此，半导体元件X1可在机械可靠性及电可靠性两方面均优越。
在半导体元件X1中，如图1A所示，优选金属屏蔽层40也向开口部30A周缘的钝化层30上延伸而形成，由此，可进一步地减少外部空气从金属屏蔽层40与钝化层30之间侵入的情况，可减少金属屏蔽层40(甚至是导电层20)产生腐蚀的情况。这样，通过使金属屏蔽层40也向开口部30A周缘的钝化层30上延伸形成，即可在半导体元件X1中进一步提高电可靠性。
在半导体元件X1中，优选通过非电解镀镍形成金属屏蔽层40，由此，可减少形成在金属屏蔽层40上形成的焊锡凸起50的导电性材料向导电层20扩散的情况。
以下，边参照图3A～图5C边说明第一实施方式的半导体元件X1的制造方法。另外，在第一实施方式中，采用铝作为形成导电层20的材料，且采用非电解镀镍层作为金属屏蔽层40，并采用焊锡膏P作为导电性构件来进行说明。
<导电层形成工序>
在半导体元件X1的制造方法中，首先，如图3A所示，在半导体基板10上以与构成该半导体基板10的集成电路的配线图案(未图示)电连接的方式形成导电层20。具体而言，首先，通过成膜技术形成导电膜。接着，通过微细加工技术将该导电膜加工成期望的图案，以形成导电层20。在此，成膜技术可举例如溅射法、蒸镀法，且作为微细加工技术可举例如使用光刻的方法。
<钝化层形成工序(保护层形成工序)>
如图3B所示，在半导体基板10及导电层20上形成具有沿厚度方向贯通的开口部30A的钝化层30。具体而言，首先，通过成膜技术以覆盖半导体基板10及导电层20整体的方式形成钝化层30。接着，通过微细加工技术在钝化层30形成开口部30A，并使电极层20的一部分露出，由此形成具有开口部30A的钝化层30。在此，成膜技术可举例如溅射法、蒸镀法，且作为微细加工技术可举例如使用光刻的方法。
<残渣除去工序>
如图3C所示，通过例如湿式蚀刻法除去残留于形成有导电层20及钝化层30的半导体基板10的无机残渣或有机残渣。具体而言，通过在蚀刻液中浸渍规定时间来进行各种残渣的除去。另外，用于除去无机残渣的蚀刻液可举例如含有氟化氢、硫酸及氯化氢的溶液，用于除去有机残渣的溶液可举例如乙醇、异丙醇及丙酮等的溶液。另外，也可通过O2灰化法等取代湿式蚀刻法来进行有机残渣的除去。
<第一水洗工序>
如图4A所示，对经残渣除去工序的半导体基板10进行水洗。具体而言，通过将经残渣除去工序的半导体基板10浸渍于洗净用水中来进行水洗。
<锌酸盐处理工序>
如图4B所示，对经第一水洗工序的半导体基板10施行锌酸盐处理。具体而言，将经第一水洗工序的半导体基板10在锌酸盐处理液中浸渍规定时间。该锌酸盐处理液中含有锌，使开口部30A的导电层20的铝与锌置换后使锌堆积，由此在该导电层20的表面形成锌膜21。另外，也可反复进行锌酸盐处理直到锌膜21堆积至规定膜厚为止。
<金属屏蔽层形成工序>
如图4C所示，在施有锌酸盐处理的半导体基板10的导电层20上形成作为金属屏蔽层40的非电解镀镍层。具体而言，将施有锌酸盐处理的半导体基板10在非电解镀镍液中浸渍规定时间。在该非电解镀镍液中，使导电层20的表面形成的锌膜21的锌与非电解镀镍液中的镍置换之后，再使镍堆积，由此在该导电层20上形成非电解镀镍层(金属屏蔽层40)。另外，非电解镀镍液可举例如，含有作为还原剂的次磷酸纳等，并且含有作为镍盐的硫酸镍或氯化镍等的溶液。就减少对半导体的影响的观点来看，该非电解镀镍液中，优选含有作为镍盐的硫酸镍的溶液为佳。另外，就更有效率地进行非电解镀镍的观点来看，非电解镀镍液的氢离子指数(pH)的值优选通过氨等pH调整剂将pH值调整在4以上5以下的范围内。
<第二水洗工序>
与第一水洗工序同样地，对经金属屏蔽层形成工序的半导体基板10进行水洗。具体而言，通过将经金属屏蔽层形成工序的半导体基板10浸渍于洗净用水中来进行水洗。
<有机覆盖膜形成工序>
如图5A所示，在形成有非电解镀镍层(金属屏蔽层40)的半导体基板10的该非电解镀镍层上形成有机覆盖膜70。具体而言，首先，将形成有非电解镀镍层(金属屏蔽层40)的半导体基板10在有机溶液中浸渍规定时间。接着，在使有机溶液附着于金属屏蔽层40的表面的状态下进行干燥，由此形成有机覆盖膜70。有机溶液可举例如，含有纯水、脂环族酸及脂肪族胺衍生物的溶液。在第一实施方式中，该有机溶液的蒸发温度设定为例如200[℃]以上240[℃]以下。另外，有机覆盖膜70的蒸发温度的测定为通过示差扫描量热仪(型号：DSC-6200、Seiko Instruments制)，以10[℃/min]的升温速度在空气环境中进行。
<导电性构件配置工序>
如图5B所示，在经有机覆盖膜形成工序的半导体基板10的有机覆盖膜70上配置(或涂布)作为导电性构件的焊锡膏P。具体而言，通过丝网印刷等进行印刷，由此将焊锡膏P配置于位于经有机覆盖膜形成工序的半导体基板10的金属屏蔽层40上的有机覆盖膜70上。焊锡膏P可举融点低于有机覆盖膜70的蒸发温度的焊锡膏。该焊锡膏P的融点温度可采用例如160[℃]以上230[℃]以下的范围中，低于有机覆盖膜70的蒸发温度的温度。另外，对耐环境性的观点来看，优选焊锡膏P为Sn/3.0Ag/0.5Cu等无铅焊锡。另外，焊锡膏P的融点采用的是固相线温度的值。
<凸起形成工序>
如图5C所示，以规定温度加热经导电性构件配置工序的半导体基板10，由此在金属屏蔽层40上形成焊锡凸起50。具体而言，首先，将涂布有焊锡膏P的半导体基板10配置于设有加热器的回焊炉内，并通过该加热器进行加热。在该回焊炉内以例如245[℃]以上的温度进行加热，以形成大致球状的焊锡凸起50，加热时间为例如可使有机覆盖膜70全部挥发的所需时间。
根据本半导体元件X1的制造方法，形成在金属屏蔽层40的中央部40b上的有机覆盖膜70的周围被金属屏蔽层40及焊锡膏P所包围，因此，比起在位于外在环境的附近的周缘部40c上所形成的有机覆盖膜70，可相对延长挥发所需的时间。因此，根据本半导体元件X1的制造方法，比起周缘部40c，可减少构成中央部40b的金属屏蔽层40的例如Ni等金属向焊锡凸起50内扩散的情况，故中央部40b的富磷部位40A的厚度可形成比周缘部40c小的厚度。因此，在本半导体元件X1的制造方法中，可缩小金属屏蔽层40的中央部40b的富磷部位40A的厚度，并且周缘部40c的富磷部位40A的厚度可形成比中央部40b大的厚度。
另外，根据第一实施方式的制造方法，可减少相对较脆的金属互化物层60(例如(Cu、Ni)6Sn5)过厚地形成在金属屏蔽层40与焊锡凸起50的界面的情况。由此，可进一步地提高所制造的半导体元件X1的可靠性。
<第二实施方式>
图6A为表示本发明第二实施方式的半导体元件X2的概略构造的主要部分截面图。图6B为放大表示图6A的一部分的截面图。
半导体元件X2在具有取代半导体元件X1的金属屏蔽层40的金属屏蔽层41的这一点上与半导体元件X1不同。关于半导体元件X2的其它构造，均与所述半导体元件X1相同。
金属屏蔽层41形成于钝化层30的开口部30A的导电层20上。该金属屏蔽层41相对于导电层20电连接。第二实施方式的金属屏蔽层41为第一层42与第二层43的层叠结构，该第一层42为以第一含磷率含有磷的镍，且该第二层43为以第二含磷率含有磷。该第二含磷率小于第一含磷率。另外，金属屏蔽层41为构造成其最上面41a位于比钝化层30的上表面30a更靠上方的位置。在此，第一含磷率优选设定为10[wt％]以下。
另外，第二实施方式的金属屏蔽层41的第一层42及第二层43也优选向开口部30A周缘的钝化层30上延伸形成。另外，金属屏蔽层41的第一层42的含磷率(第一含磷率)设定为例如5[wt％]以上10[wt％]以下(即所谓的中磷镍)。该范围的金属屏蔽层41的第一层42的硬度，在例如维氏硬度中为500[HV]以上600[HV]以下。另外，金属屏蔽层41的第二层43的含磷率(第二含磷率)设定为例如1[wt％]以上5[wt％]以下(即所谓的低磷镍)。该范围的金属屏蔽层41的第二层43的硬度，在例如维氏硬度中为700[HV]以上1000[HV]以下。
另外，第二实施方式的金属屏蔽层41为构造成使富磷部位41A(含磷率为10[wt％]以上的部位)少量存在于其焊锡凸起50侧的表面部，且该富磷部位41A通过构成该金属屏蔽层41的镍的一部分向焊锡凸起50侧扩散而产生。
在第二实施方式的半导体元件X2中，金属屏蔽层41的含磷率比富磷部位41A小，且具有第一层42及第二层43。该第一层42的含磷率比第二层43大。另外，该第一层42在钝化层30的开口部30A中，位于比第二层43更靠导电层20侧的位置。这样，使位于导电层20侧的第一层42的含磷率大于第二层43的含磷率，在半导体元件X2中，可进一步地提高金属屏蔽层41的耐腐蚀性。另外，在半导体元件X2中，过度减小含磷率可减少金属屏蔽层41的硬度过度提高的情况，且可减少在钝化层30产生裂痕或剥落的情况。因此，半导体元件X2在提高机械可靠性及电可靠性方面是合适的。另外，本构造在减少富磷层41A的厚度增大的情况方面也是合适的。
另外，在图6A等所示的半导体元件X2中，金属屏蔽层41的第一层42也形成于开口部30A周缘的钝化层30上，因此，可充分减少焊锡凸起50的形成区域的周缘部41c的耐腐蚀性降低的情况。
以下，边参照图7A、图7B边说明第二实施方式的半导体元件X2的制造方法。在半导体元件X2的制造方法中，形成半导体元件X2的金属屏蔽层41的金属屏蔽层形成工序与半导体元件X1的制造方法不同。关于半导体元件X2的其它工序，均与所述半导体元件X1的制造方法相同。
<金属屏蔽层形成工序>
首先，如图7A所示，在施有锌酸盐处理的半导体基板10的导电层20上形成作为金属屏蔽层41的第一层42的非电解镀镍层。具体而言，首先，将施有锌酸盐处理的半导体基板10在第一非电解镀镍液中浸渍规定时间。在该非电解镀镍液中，使导电层20的表面所形成的锌膜的锌与非电解镀镍液中的镍进行置换后，再使镍堆积，由此在该导电层20上形成非电解镀镍层(金属屏蔽层41的第一层42)。另外，第一非电解镀镍液可举，含有作为还原剂的次磷酸纳等，并且含有作为镍盐的硫酸镍或氯化镍等的溶液等。就减少对半导体的影响的观点来看，在该非电解镀镍液中优选含有作为镍盐的硫酸镍的溶液。另外，就更有效率地进行非电解镀镍的观点来看，第一非电解镀镍液的氢离子指数(pH)的值优选通过氨等pH调整剂将pH值调整在4以上5以下的范围内。
接着，如图7B所示，在第一层42上形成作为第二层43的非电解镀镍层。具体而言，除了采用第二非电解镀镍液取代第一非电解镀镍液以外，均与所述金属屏蔽层41的第一层42的形成方法相同。作为第二非电解镀镍液可举，含有作为还原剂的次磷酸纳等，并且含有作为镍盐的硫酸镍或氯化镍等的溶液等。就减少对半导体的影响的观点来看，在该非电解镀镍液中优选含有作为镍盐的硫酸镍的溶液。另外，第二非电解镀镍液与第一非电解镀镍液不同，为调剂成可降低析出的磷的比例。此外，就更有效率地进行非电解镀镍的观点来看，第二非电解镀镍液的pH的值优选通过氨等pH调整剂将pH值调整在6～7的范围内。
第二实施方式的半导体元件X2的制造方法可发挥与第一实施方式的半导体元件X1的制造方法相同的效果。
<第三实施方式>
图8为表示本发明第三实施方式的实装结构体Y的概略构造的主要部分截面图。
在第三实施方式的实装结构体Y中，将第一实施方式的半导体元件X1实装于电路基板80。该实装结构体Y具有半导体元件X1及电路基板80。另外，在第三实施方式中，采用半导体元件X1为例说明，但也可将半导体元件X1更换成半导体元件X2。
在此，电路基板80具有基板81、电路图案82、衬垫部83、功能元件(未图示)。
基板81可发挥作为电路图案82及衬垫部83的支承基材的功能。
电路图案82电连接于未图示的功能元件，并形成于基板81上。形成电路图案82的材料可举例如：Al、Cu、Al-Cu、Al-Si及Al-Si-Cu等金属材料。
衬垫部83为具有电连接于半导体元件X1的导电部20的功能的部位。该衬垫部83电连接于电路图案82。在该衬垫部83经由焊锡凸起50实装有半导体元件X1。
由于实装结构体Y实装半导体元件X1，所以可享有半导体元件X1具有的效果。因此，实装结构体Y在机械可靠性及电可靠性两方面均优越。
以上，示出了本发明的具体的第一～第三实施方式，但本发明不受限于此，可在不脱离发明思想的范围内进行各种变更。
在本发明的第一实施方式的半导体元件X1中，金属屏蔽层40的富磷部位40A在中央部40b具有大致均匀的厚度。本发明的半导体元件X1不受限于所述构造。例如，如图9A、图9B所示，金属屏蔽层40的富磷部位40A也可在中央部40b具有规定厚度的第一部位40Ab1及厚度比该第一部位40Ab1小的第二部位40Ab2。
另外，如图10A及图10B所示，金属屏蔽层30的富磷部位40A以外的部位也可贯通富磷部位40A而接合于金属互化物层60。在这种情况下，可在该区域40d中进一步提高金属屏蔽层40与焊锡凸起50的接合部分的机械强度，从而机械可靠性能够更加优越。
在本发明的第一实施方式的半导体元件X1中，富磷部位40A形成于金属屏蔽层40的焊锡凸起50侧。本发明的半导体元件X1不受限于所述构造，例如，如图11所示，富磷部位40A也可仅位于周缘部40c。即使是在这种情况下，也可发挥与半导体元件X1相同的效果。并且上，在这种情况下，富磷部位40A并未设于中央部40b，可更进一步提高金属屏蔽层40与焊锡凸起50的接合部分的机械强度。
以上，在第一～第三实施方式中，说明了具有富磷部位的半导体元件。
然而，第一实施方式中说明的制造方法也可应用于制造在金属屏蔽层40未具有富磷部位的半导体元件，在这种情况下，可使金属互化物层60的厚度变薄。
以下，将其具体内容作为第四实施方式来说明。
<第四实施方式>
本发明的第四实施方式的半导体元件X3的制造方法包括：在金属屏蔽层40上形成有机覆盖膜70的有机覆盖膜形成工序；在有机覆盖膜70上配置熔点低于有机覆盖膜70的蒸发温度的焊锡膏P的导电性构件配置工序；使焊锡膏P熔融并且使有机覆盖膜70挥发，从而在金属屏蔽层40上形成焊锡凸起50的凸起形成工序。
因此，在第四实施方式的制造方法中，即使焊锡膏P熔融，在有机覆盖膜70挥发之前的这段期间，也可减少金属屏蔽层40的形成成分(例如，镍)从金属屏蔽层40向焊锡膏P扩散的情况。因此，在第四实施方式的制造方法中，可减少相对较脆的金属互化物层60(例如(Cu、Ni)6Sn5)过厚地形成在金属屏蔽层40与焊锡凸起50的界面的情况。由此，根据第四实施方式的制造方法，可提高所制造的半导体元件X3的可靠性。
图12为表示通过第四实施方式的制造方法制作的半导体元件X3的概略构造的主要部分放大截面图。
另外，根据第四实施方式的制造方法，由于在金属屏蔽层40上形成有有机覆盖膜70，故无需在作为金属屏蔽层40的非电解镀镍层上设置作为防止氧化膜的金层，即使是仅由非电解镀镍层所构成的金属屏蔽层40，也可降低其氧化。
此外，根据第四实施方式的制造方法，金属屏蔽层40无需设置金层，故可减少构成金层的金向焊锡凸起50扩散，而使该焊锡凸起50的湿润性降低的情况。
在本制造方法中，优选使金属屏蔽层40上的有机覆盖膜70全部挥发，故可减少因过度残留有机覆盖膜70而降低焊锡膏P的湿润性的情况。
在本制造方法中，以覆盖金属屏蔽层40整体的方式形成有机覆盖膜70，故可减少金属屏蔽层40整体的氧化，而可减少对焊锡膏P的湿润性降低的情况。
在本制造方法中，也在钝化层30的开口部30A的周缘部上形成金属屏蔽层40，故可减少导电层20的腐蚀等产生。
在本制造方法中，金属屏蔽层40为通过非电解镀镍所形成，故可减少形成金属屏蔽层40的镍成分向该金属屏蔽层40上所形成的焊锡凸起50侧扩散的情况。另外，由于金属屏蔽层40含有磷，故可提高形成金属屏蔽层40的非电解镀镍的耐腐蚀性。
另外，在通过第四实施方式的制造方法所制作的半导体元件X3中，在焊锡凸起50与金属屏蔽层40之间虽然存在通过形成焊锡凸起50的焊锡与形成金属屏蔽层40的镍扩散而形成的金属互化物层60，但可使其厚度变薄。即，该金属互化物层60的厚度并非过厚的厚度(例如4.0[μm]以上)，而是在可确保适当接合的范围内的相当薄的厚度(例如2.0[μm]以下)。另外，可减少如以往那样会形成局部厚的情况，故可更提高厚度的均匀性。另外，作为形成金属互化物层60的材料可举例如(Cu、Ni)6Sn5。
以上，通过具体的第四实施方式表现出本发明，但本发明不受限于此，可在不脱离发明思想的范围内进行各种变更。
例如，在第四实施方式的制造方法中，也可使焊锡凸起50含有有机覆盖膜70的挥发成分。在这种制造方法中也可发挥与所述相同的效果。另外，若在该情况中含有作为有机覆盖膜70的挥发成分的脂环族胺，则构成胺的N可发挥与松香焊剂相同的功能，故可得到与使用松香焊剂时相同的效果。

Claims (14)

1.一种半导体元件，其特征在于，具有：
基板；导电层，其设于所述基板上；保护层，其设于所述导电层上且具有开口部；金属屏蔽层，其在所述开口部与所述导电层接合；导电性凸起，其形成于所述金属屏蔽层上，
所述金属屏蔽层含有磷，且具有含磷率大于其它部分的富磷部位，
所述富磷部位位于所述导电性凸起侧的表面部，所述导电性凸起的形成区域的周缘部中的所述富磷部位的厚度大于所述形成区域的中央部中的所述富磷部位的厚度。
2.如权利要求1所述的半导体元件，其特征在于，
在所述金属屏蔽层与所述导电性凸起之间还具有金属互化物层，该金属互化物层含有所述金属屏蔽层的构成材料与所述导电性凸起的构成材料而成，
在所述金属屏蔽层中，所述富磷部位以外的部位贯通所述富磷部位而与所述金属互化物层连接。
3.一种半导体元件，其特征在于，具有：
基板；导电层，其设于所述基板上；保护层，其设于所述导电层上且具有开口部；金属屏蔽层，其在所述开口部与所述导电层接合；导电性凸起，其形成于所述金属屏蔽层上，
所述金属屏蔽层含有磷，且具有含磷率大于其它部分的富磷部位，
所述富磷部位位于所述导电性凸起侧的表面部，且仅位于所述导电性凸起的形成区域的周缘部。
4.如权利要求1或3所述的半导体元件，其特征在于，
所述金属屏蔽层还形成于所述开口部周缘的所述保护层上。
5.如权利要求1或3所述的半导体元件，其特征在于，
所述金属屏蔽层的富磷部位以外的部位包括含磷率小于所述富磷部位的第一部位与含磷率小于所述富磷部位的第二部位，
所述第一部位位于所述导电层侧的表面部，且其含磷率小于所述第二部位。
6.一种实装结构体，其特征在于，具有：
权利要求1或3所述的半导体元件；具有配线电极的基体，
在所述基体上设有与所述配线电极电连接的衬垫部，
所述衬垫部与所述半导体元件的所述导电性凸起接合。
7.一种半导体元件的制造方法，其特征在于，包括：
导电层形成工序，在基板的主面形成导电层；
保护层形成工序，形成覆盖所述导电层且在所述导电层上具有开口部的保护层；
金属屏蔽层形成工序，形成在所述开口部与所述导电层接合并含有磷的金属屏蔽层；
有机覆盖膜形成工序，在所述金属屏蔽层上形成有机覆盖膜；
导电性构件配置工序，在所述有机覆盖膜上配置熔点低于所述有机覆盖膜的蒸发温度的导电性构件；
凸起形成工序，使所述导电性构件熔融并且以使在所述金属屏蔽层的周缘部上形成的所述有机覆盖膜挥发所需的时间比在所述金属屏蔽层的中央部上形成的所述有机覆盖膜挥发所需的时间短的方式使所述有机覆盖膜挥发，而在所述金属屏蔽层上形成导电性凸起。
8.如权利要求7所述的半导体元件的制造方法，其特征在于，
所述导电性凸起含有所述有机覆盖膜的挥发成分。
9.如权利要求8所述的半导体元件的制造方法，其特征在于，
所述有机覆盖膜的挥发成分含有脂环族酸及脂肪族胺衍生物。
10.如权利要求7所述的半导体元件的制造方法，其特征在于，
使所述金属屏蔽层上的所述有机覆盖膜全部挥发。
11.如权利要求7所述的半导体元件的制造方法，其特征在于，
以覆盖所述金属屏蔽层整体的方式形成所述有机覆盖膜。
12.如权利要求7所述的半导体元件的制造方法，其特征在于，
在所述保护层的所述开口部的周缘部上也形成所述金属屏蔽层。
13.如权利要求7所述的半导体元件的制造方法，其特征在于，
通过非电解镀镍形成所述金属屏蔽层。
14.如权利要求13所述的半导体元件的制造方法，其特征在于，
所述金属屏蔽层形成工序包括：
第一部位形成工序，形成在所述开口部与所述导电层接合的第一部位；
第二部位形成工序，在所述第一部位上形成含磷率小于第一部位的第二部位。
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