JPH01214141A - フリップチップ型半導体装置 - Google Patents

フリップチップ型半導体装置

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Publication number
JPH01214141A
JPH01214141A JP63041180A JP4118088A JPH01214141A JP H01214141 A JPH01214141 A JP H01214141A JP 63041180 A JP63041180 A JP 63041180A JP 4118088 A JP4118088 A JP 4118088A JP H01214141 A JPH01214141 A JP H01214141A
Authority
JP
Japan
Prior art keywords
film
electrode pad
pad
polyimide film
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63041180A
Other languages
English (en)
Inventor
Norimasa Takada
高田　教正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63041180A priority Critical patent/JPH01214141A/ja
Priority to US07/314,166 priority patent/US5046161A/en
Publication of JPH01214141A publication Critical patent/JPH01214141A/ja
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフリップチップ型半導体装置に関し、特に無機
質パッシベーション膜上にざリイミド膜を形成して電極
パッド上に球状のはんだバンプを形成する構造のフリッ
プチップ型半導体装置に関する。
〔従来の技術〕
従来、この種のフリップチップ型半導体装置は、第３図
に示すように、能動領域及び配線を含む回路領域１１と
、この回路領域１１と接続するアルミニウム製の電極パ
ッド１２とを備えた半導体ペレット１上全面に、例えば
窒化シリコン膜などの無機質パッシベーション膜２を、
電極バッド１２の中央部に窓（開孔部）を設けて形成し
、更にこの無機質パッシベーション膜２上全面に、前述
の窓と同じ位置に円形状の窓を設けたポリイミド膜３Ｂ
を形成した後、これらの窓を介して電極パッド１２上に
バイアメタル４を形成しこの上に球状のはんだバンプ５
を形成する構造となっている。
通常、電極パッド１２の形状は矩形であり、従って無機
質パッシベーション！２の窓も矩形であルノで、ポリイ
ミド膜を使わずにはんだバンプを形成した場合には、バ
ンプの底面が矩形になり、はんだバンプを球状に整形し
にくくなってはんだバンプの高さにばらつきが発生する
。
このような場合、半導体ペレットをフェイスダウンボン
ディングにより基板上にはんだバンプを溶融して接続す
るとき、接続不良が誘発され歩留りの低下及び信頼性の
低下を招くという不具合がある。
これを防ぐにためには、無機質パッシベーション膜２の
窓の形を円形にしておけばよいが、これを実現するため
にははんだバンプ専用のホトマスクを用意しなければな
らず、この場合にはセミカスタムとなるので、大量生産
している半導体装πの工程管理が極めて複雑になるとい
う不都合がある。
従って通常は、生産の合理化を考慮して大量生産してい
るモールド組立用のウェハースをそのまま流用し、場合
によ゛ってはユーザ側ではんだバンプを形成する方法が
とられる。
上述した矩形の窓をもつ無機質パッシベーション膜２を
下地として球状のはんだバンプ５を形成するために円形
状の窓をもつポリイミド膜３８と介在させている。
〔発明が解決しようとする課題〕
上述した従来の７リツプチツプ型半導体装置は、電極用
パッド１２上に窓をもち半導体ペレット１上全面を覆う
無機質パッシベーション膜２上全面に、更に、ｔｉ用バ
ッド１２上に円形上の窓をもつポリイミド膜３Ｂを形成
し、このポリイミド膜３Ｂを介在させてはんだバンプ５
を形成する構造となっているので、次のような欠点があ
る。
ポリイミド膜３Ｂは硬化収縮時の体積変化により発生す
る応力が大きく、しかも半導体ペレット１を形成するシ
リコンに比べて約１０倍の６０Ｘ１０−６（１／’Ｃ）
という線膨張係数をもつので、回路特性の劣化やクラッ
クが発生することがある。
さらに２５６に〜ＩＭビットのＤＲＡＭのような高密度
半導体ペレットになると、半導体ペレット上の配線が１
μｍまたはそれ以下と極めて微細となり、上層に形成さ
れているポリイミド膜の影響をうけて、配線パターンが
ずれたり配線が切断したりする現象が発生する。このた
め製品歩留りが低下し信頼性も失われるという欠点があ
る。
本発明の目的は、ポリイミド膜による回路特性の劣化や
クラックの発生、配線パターンのずれや断線を防止する
ことができ、製品歩留り及び信頼性の向上をはかること
ができるフリップチップ型半導体装置を提供することに
ある。
〔課題を解決するための手段〕
本発明のフリップチップ型半導体装置は、能動領域及び
配線を含む回路領域と、この回路領域と接続する電極用
パッドとを備えた半導体ペレットと、前記電極用パット
上に所定の形状の開孔部をもち前記半導体ペレット上全
面を覆って形成された無機質パッシベーション膜と、こ
の無機質パッシベーション膜の開孔部と対応する位置に
円形状の開孔部をもち、前記電極用パッド上の無機質パ
ッシベーション膜上及びこの電極用パッド周辺の無機質
パッシベーション膜上に、前記回路領域上にかからない
ように形成されたポリイミド膜と、このポリイミド膜の
開孔部を介して形成され前記電極用パッドと接続するは
んだバンプとを有している。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図は本発明の第１の実施例を示す断面図である。
この実施例は、能動領域及び配線等を含む回路領域１１
と、この回路領域と接続する電極用パッド１２とが形成
された半導体ペレット１と、電極用パッド１２上に通常
矩形の開孔部（窓）をもち、半導体ペレット１上全面番
覆って形成された無機質パッシベーション膜２と、この
無機質パッシベーション膜２の開孔部と同じ位置に円形
状の開孔部（窓）をもち、電極パッド１２上の無機質パ
ッシベーション膜２上及び電極パッド１２周辺のパッシ
ベーション膜２上に、回路領域１１上にかからないよう
に形成されたポリイミド膜３と、このポリイミド膜３の
開孔部を介して電極用パッド１２上にバリアメタル膜４
を成膜した後、電極用パッド１２と接続するはんだバン
プ５とを備えた構造となっている。
次に、この実施例の製造工程について説明する。
まず、回路領域１１．電極用パッド１２等が形成された
半導体ペレット１上全面に、電極用パッド１２の中央部
から周辺部内側にかけて開孔された無機質パッシベーシ
ョン膜２を形成する。
次に、開孔部を含む無機質パッシベーション膜２上全面
に厚さ約１μｍのポリイミド膜をスピンコード法により
成膜し、ホトリソグラフィ技術により、電極用パッド１
２上を円形状にエツチングして開孔すると同時に、この
開孔部から電極用パッド１２の外側周辺部にかけての領
域を除く領域すべてを一層エッチングし、電極用パッド
１２上に円形状の開孔部をもち電極用パッド１２上及び
この周辺のみの無機質パッシベーション膜２を覆うポリ
イミド膜３を形成する。このポリイミド膜３は、回路領
域１１上にかからないように形成する。
次に、電極用パッド１２．ポリイミド膜３等の上に、Ｔ
ｉ−Ｃｕ、Ｃｒ−Ｃｕ等のバリアメタル膜を形成した後
、メツキ用レジストを使って選択的に電極用パッド上の
みはんだめっきし、メツキ用レジストを剥離してバリア
メタル膜をエツチングし、続いてはんだめっきされたは
んだを溶融整形（ウェットバック）して球状のはんだバ
ンプ５を形成し第１図に示された構造のフリップチップ
型半導体装置ができ上る。
なお、電極用パッド１２上においてポリイミド膜３は、
この電極用パッド１２を保護するために、無機質パッシ
ベーション膜２の開孔部の縁も包含するように形成する
のが望ましい。
また、電極用パッド１２は１００μｍ角程度であり、こ
れに対し半導゛体ペレット１の回路領域１１から電極用
パッド１２までの距離は１００〜２００μｍ程度である
ので、ポリイミド膜３はこの寸法を考慮し回路領域１１
上にかからない範囲に形成する必要がある。
このように、ポリイミド膜３を回路領域１１にかからな
いように、かつ狭い範囲に形成することにより、ポリイ
ミド膜３の応力等による影響を除去することができ、配
線のパターンずれや断線、クラックの発生等を防止する
ことができる。
第２図は本発明の第２の実施例を示す平面図及びＡ−Ａ
′断面図である。
この実施例は、隣接する電極用パッド１２の間に回路領
域１１がなく、個々にポリイミド膜を形成することが困
難な場合に、これらを一体止してポリイミド膜３Ａとし
たものであり、ポリイミド膜加工条件が緩和されるとい
う利点がある。
〔発明の効果〕
以上説明したように本発明は、ポリイミド膜を、回路領
域上にかからないように電極用パッド周辺の狭い範囲に
形成する構成とすることにより、ポリイミド膜の応力等
の影響を除去することができるので、配線パターンのず
れや断線、クラックの発生や回路特性の劣化等を防止す
ることができ、製造歩留り及び信頼性の向上をはかるこ
とができる効果がある。
特に高密度のＤＲＡＭのように、微細配線をもつ半導体
装１に対しては、この効果は一層顕著である。
【図面の簡単な説明】
第１図は本発明の第１の実施例を示す断面図、第２図（
ａ＞、（ｂ）はそれぞれ本発明の第２の実施例を示す平
面図及び断面図、第３図は従来のフリップチップ型半導
体装置の一実施例を示す断面図である。 １・・・半導体ペレット、２・・・無機質パッシベーシ
ョン膜、３．３Ａ、３Ｂ・・・ポリイミド膜、４・・・
バリアメタル、５・・・はんだバンプ、１１・・・回路
領域、１２・・・電極用パッド。

Claims (1)

    【特許請求の範囲】
  1. 　能動領域及び配線を含む回路領域と、この回路領域と
    接続する電極用パッドとを備えた半導体ペレットと、前
    記電極用パット上に所定の形状の開孔部をもち前記半導
    体ペレット上全面を覆つて形成された無機質パッシベー
    ション膜と、この無機質パッシベーション膜の開孔部と
    対応する位置に円形状の開孔部をもち、前記電極用パッ
    ド上の無機質パッシベーション膜上及びこの電極用パッ
    ド周辺の無機質パッシベーション膜上に、前記回路領域
    上にかからないように形成されたポリイミド膜と、この
    ポリイミド膜の開孔部を介して形成され前記電極用パッ
    ドと接続するはんだバンプとを有することを特徴とする
    フリップチップ型半導体装置。
JP63041180A 1988-02-23 1988-02-23 フリップチップ型半導体装置 Pending JPH01214141A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63041180A JPH01214141A (ja) 1988-02-23 1988-02-23 フリップチップ型半導体装置
US07/314,166 US5046161A (en) 1988-02-23 1989-02-22 Flip chip type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63041180A JPH01214141A (ja) 1988-02-23 1988-02-23 フリップチップ型半導体装置

Publications (1)

Publication Number Publication Date
JPH01214141A true JPH01214141A (ja) 1989-08-28

Family

ID=12601231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63041180A Pending JPH01214141A (ja) 1988-02-23 1988-02-23 フリップチップ型半導体装置

Country Status (2)

Country Link
US (1) US5046161A (ja)
JP (1) JPH01214141A (ja)

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