FI962277A0 - Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar - Google Patents

Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar

Info

Publication number
FI962277A0
FI962277A0 FI962277A FI962277A FI962277A0 FI 962277 A0 FI962277 A0 FI 962277A0 FI 962277 A FI962277 A FI 962277A FI 962277 A FI962277 A FI 962277A FI 962277 A0 FI962277 A0 FI 962277A0
Authority
FI
Finland
Prior art keywords
tennknoelstruktur
oinkapslade
microcret
loed
eller
Prior art date
Application number
FI962277A
Other languages
English (en)
Inventor
Jorma Kivilahti
Petteri Palm
Original Assignee
Elcoteq Network Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elcoteq Network Oy filed Critical Elcoteq Network Oy
Priority to FI962277A priority Critical patent/FI962277A0/fi
Publication of FI962277A0 publication Critical patent/FI962277A0/fi
Priority to JP09541692A priority patent/JP2000511001A/ja
Priority to PCT/FI1997/000331 priority patent/WO1997045871A1/en
Priority to AU29642/97A priority patent/AU2964297A/en
Priority to EP97924046A priority patent/EP0958606A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
FI962277A 1996-05-31 1996-05-31 Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar FI962277A0 (fi)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FI962277A FI962277A0 (fi) 1996-05-31 1996-05-31 Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar
JP09541692A JP2000511001A (ja) 1996-05-31 1997-05-30 カプセル化されないマイクロ回路用のはんだ合金又は錫接触バンプ構造と同時にそれを製造するための手順
PCT/FI1997/000331 WO1997045871A1 (en) 1996-05-31 1997-05-30 Solder alloy or tin contact bump structure for unencapsulated microcircuits as well as a process for the production thereof
AU29642/97A AU2964297A (en) 1996-05-31 1997-05-30 Solder alloy or tin contact bump structure for unencapsulated microcircuits as well as a process for the production thereof
EP97924046A EP0958606A1 (en) 1996-05-31 1997-05-30 Solder alloy or tin contact bump structure for unencapsulated microcircuits as well as a process for the production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI962277A FI962277A0 (fi) 1996-05-31 1996-05-31 Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar

Publications (1)

Publication Number Publication Date
FI962277A0 true FI962277A0 (fi) 1996-05-31

Family

ID=8546126

Family Applications (1)

Application Number Title Priority Date Filing Date
FI962277A FI962277A0 (fi) 1996-05-31 1996-05-31 Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar

Country Status (5)

Country Link
EP (1) EP0958606A1 (fi)
JP (1) JP2000511001A (fi)
AU (1) AU2964297A (fi)
FI (1) FI962277A0 (fi)
WO (1) WO1997045871A1 (fi)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2799578B1 (fr) * 1999-10-08 2003-07-18 St Microelectronics Sa Procede de realisation de connexions electriques sur un boitier semi-conducteur et boitier semi-conducteur
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4880708A (en) * 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JPH07321114A (ja) * 1994-05-23 1995-12-08 Sharp Corp 半導体装置のハンダバンプ形成の方法および構造
US5587336A (en) * 1994-12-09 1996-12-24 Vlsi Technology Bump formation on yielded semiconductor dies

Also Published As

Publication number Publication date
AU2964297A (en) 1998-01-05
EP0958606A1 (en) 1999-11-24
JP2000511001A (ja) 2000-08-22
WO1997045871A1 (en) 1997-12-04

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