CN102456657B - 具有底部凸块金属化(ubm)结构的半导体器件及其形成方法 - Google Patents

具有底部凸块金属化(ubm)结构的半导体器件及其形成方法 Download PDF

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CN102456657B
CN102456657B CN201110217315.8A CN201110217315A CN102456657B CN 102456657 B CN102456657 B CN 102456657B CN 201110217315 A CN201110217315 A CN 201110217315A CN 102456657 B CN102456657 B CN 102456657B
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metal layer
layer
ubm
sectional dimension
semiconductor device
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CN102456657A (zh
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吴逸文
郭宏瑞
黄见翎
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件具有焊料凸块下方且电连接至焊料凸块的UBM(底部凸块金属化)结构。UBM结构包括具有第一截面尺寸d1的第一金属化层、形成在第一金属化层上的具有第二截面尺寸d2的第二金属化层和形成在第二金属化层上的具有第三截面尺寸d3的第三金属化层，其中，d1大于d3，d3大于d2。

Description

具有底部凸块金属化(UBM)结构的半导体器件及其形成方法
本申请要求于2010年10月21日提交的美国临时专利申请序列号61/405,412的优先权，其全部内容结合于此作为参考。
技术领域
本公开涉及半导体器件的制造，更具体地，涉及半导体器件中底部凸块金属化(UBM)的制造。
背景技术
现代集成电路由差不多百万个有源和/或无源器件(诸如晶体管和电容器)形成。这些器件最初都彼此隔离，但是稍后互连到一起以形成功能电路。典型的互连结构包括侧向互连(诸如金属线(配线))和垂直互连(诸如通孔和接触)。互连日益增加地确定现代集成电路的性能和密度的限制。在互连结构的顶部，形成结合焊盘并在各个芯片的顶部露出。通过结合焊盘进行电连接以将芯片连接至封装衬底或另一管芯。结合焊盘可用于配线结合或倒装结合。在典型的凸块形成工艺中，在金属化层上形成互连结构，然后形成底部凸块金属化(UMB)和焊球。倒装封装利用凸块来建立芯片的输入/输出(I/O)焊盘与衬底或封装的焊接框架之间的电接触。
结构上，凸块是指凸块本身以及位于凸块和I/O焊盘之间的UBM。UBM通常在I/O焊盘上包含顺序配置的粘合层、阻挡层和润湿层。基于所使用的材料，凸块被分为焊料凸块、金凸块、铜柱凸块和具有混合金属的凸块。通常，用于焊料凸块的材料为所谓的Sn-Pb易熔质焊料。近年来，半导体工业已经转移到“无铅(Pb)”封装和无铅器件连接技术。为了执行UBM的蚀刻，使用湿蚀刻或干蚀刻。湿蚀刻具有特定的缺点：焊料凸块下方的UBM由于各向同性的蚀刻特性而经常被底切，并且UBM的下层更加严重地被底切。这通常引起低介电常数(低k)电介质分层问题。由于这些原因，干蚀刻用于缓解底切问题，但其容易损坏凸块并生成需要通过额外工艺去除的聚合物残留。
发明内容
为解决上述问题，本发明提出了一种半导体器件，包括：半导体衬底；底部凸块金属化UBM结构，覆盖半导体衬底；以及焊料凸块，覆盖并电连接至UBM结构；其中，UBM结构包括具有第一截面尺寸d1的第一金属化层、形成在第一金属化层上的具有第二截面尺寸d2的第二金属化层、以及形成在第二金属化层上的具有第三截面尺寸d3的第三金属化层，其中，d1大于d3。
其中，d3大于d2。
其中，第一金属化层包括钛Ti。
其中，第二金属化层包括铜Cu。
其中，第三金属化层包括镍Ni和铜Cu中的至少一种。
其中，焊料凸块包括无铅焊料材料。
此外，本发明还提出了一种形成半导体器件的方法，包括：形成覆盖半导体衬底的第一金属化层；形成覆盖第一金属化层的第二金属化层；形成覆盖第二金属化层的具有开口的掩模层；在掩模层的开口中形成第三金属化层；形成覆盖第三金属化层的焊料材料层；去除掩模层；执行湿蚀刻工艺，以去除第二金属化层的未覆盖部分；在焊料材料层上执行热回流工艺，以形成焊料凸块；以及将焊料凸块用作硬掩模来执行干蚀刻工艺，以去除第一金属化层的一部分。
其中，在湿蚀刻工艺和干蚀刻工艺之后，第一金属化层具有第一截面尺寸d1，第二金属化层具有第二截面尺寸d2，以及第三金属化层具有第三截面尺寸d3，其中，d1大于d3。
其中，d3大于d2。
其中，第一金属化层包括钛Ti层、氧化钛TiOx层、钽Ta层和氮化钽TaN层中的至少一种。
其中，第二金属化层是铜Cu层。
其中，第三金属化层包括镍Ni层和铜Cu层中的至少一种。
该方法还包括：在热回流工艺之前，执行O2清除浮渣工艺。
此外，本发明还提出了一种形成半导体器件的方法，包括：形成覆盖半导体衬底的第一金属化层；形成覆盖第一金属化层的第二金属化层；形成覆盖第二金属化层的具有开口的掩模层；在掩模层的开口中形成第三金属化层；形成覆盖第三金属化层的蘑菇状焊料材料层；去除掩模层；执行湿蚀刻工艺，以去除第二金属化层的未覆盖部分；将蘑菇状焊料材料层用作硬掩模来执行干蚀刻工艺，以去除第一金属化层的一部分；以及在蘑菇状焊料材料上执行热回流工艺，以形成焊料凸块。
其中，在湿蚀刻工艺和干蚀刻工艺之后，第一金属化层具有第一截面尺寸d1，第二金属化层具有第二截面尺寸d2，以及第三金属化层具有第三截面尺寸d3，其中，d1大于d3。
其中，d3大于d2。
其中，第一金属化层包括钛Ti层、氧化钛TiOx层、钽Ta层和氮化钽TaN层中的至少一种。
其中，第二金属化层是铜Cu层。
其中，第三金属化层包括镍Ni层和铜Cu层中的至少一种。
该方法还包括：在热回流工艺之前，执行O2清除浮渣工艺。
附图说明
图1是根据本公开各个方面的半导体器件中的UBM结构的制造方法的流程图；
图2A至图2G是处于根据图1的方法的制造的各种阶段的半导体器件的一部分的截面图；
图3是根据本公开各个方面的半导体器件中的UBM结构的制造方法的另一实例的流程图；以及
图4A至图4D是处于根据图3的方法的制造的各种阶段的半导体器件的一部分的截面图。
具体实施方式
本公开提供了用于倒装组件、晶片级芯片尺寸封装(WLCSP)、三维集成电路(3D-IC)堆叠和/或任何先进的封装技术领域的半导体器件中所使用的UBM形成工艺。本文所描述的实施例涉及半导体器件所使用的UBM上的焊料凸块的形成方法。现在将详细参照附图所示的示例性实施例。在可能的情况下，在附图和描述中使用的相同参考标号表示相同或类似的部件。在附图中，为了清晰和方便可以夸大形状和厚度。
该描述的目的在于具体描述形成根据本公开的装置的一部分或者与其更加直接协作的元件。应该理解，没有具体示出或描述的元件可以采取本领域技术人员已知的各种形式。此外，当提到一层在另一层上或者在衬底上，则其可以直接在另一层或衬底上，或者还可以存在中间层。贯穿该说明书的“一个实施例”或“实施例”是指结合实施例描述的特定特征、结构或特性包括在至少一个实施例中。因此，该说明书各处出现的“在一个实施例中”或“在实施例中”不是必须都表示相同实施例。此外，可以在一个或多个实施例中以任何适当的方式组合特定的特征、结构或特性。应该理解，以下附图没有按比例绘制，这些附图只是为了说明的目的。
图1是根据本公开各个方面的具有UBM结构的半导体器件的制造方法的流程图。
参照图1，方法100开始于块102，其中，在半导体衬底的上方形成下部UBM层和上部UBM层。方法100继续到块104，其中，在上部UBM层上形成具有开口的掩模层。方法100继续到块106，其中，在掩模层的开口中形成金属化层。方法100继续到块108，其中，在金属化层上形成焊料材料层。方法100继续到块110，其中，去除掩模层。方法100继续到块112，其中，执行湿蚀刻工艺以去除上部UBM层的未覆盖部分。方法100继续到块113，其中，执行O2清除浮渣工艺，以氧化金属化层和下部UBM层的露出表面。方法100继续到块114，其中，在焊料材料层上执行热回流工艺。热回流工艺对焊料材料层进行再成形以形成焊料凸块。例如，半球状焊料凸块。方法100继续到块116，其中，将焊料凸块作为硬掩模，执行干蚀刻工艺以去除下部UBM的一部分。UBM形成工艺可以缓解UBM底切问题并形成外围区域延伸到焊料凸块的边缘外侧的下部UBM层。
图2A至图2G是处于根据图1的方法的制造的各个阶段的半导体器件的一部分的截面图。
参照图2A，在半导体器件制造中采用用于凸块制造的示例性半导体衬底10，并且可以在其中和/或其上形成集成电路。半导体衬底10被定义为包括半导体材料的任何结构，包括但不限于块状硅、半导体晶片、绝缘体上硅(SOI)衬底或硅锗衬底。还可以使用包括III族元素，IV族和/或V族元素的其他半导体材料。衬底10可以进一步包括多个隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或硅局部氧化(LOCOS)部件。隔离部件可以限定和隔离各种微电子元件(未示出)。可形成在衬底10中的各种微电子元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结晶体管(BJT)、高压晶体管、高频晶体管、p和/或n沟道场效应晶体管(PFET/NFET)等)、电阻器、二极管、电容器、电感器、熔丝或其他适当的元件。采用各种工艺制成各种微电子元件，包括沉积、蚀刻、注入、光刻、退火或其他适当的工艺。微电子元件被互连以形成集成电路器件，诸如逻辑器件、存储器件(例如，静态随机存取存储器或SRAM)、射频(RF)器件、输入/输出(I/O)器件、芯片上系统(SoC)器件、它们的组合或者其他适当类型的器件。半导体衬底10进一步包括覆盖集成电路的层间电介质层和金属化结构。金属化结构中的层间电介质层包括低k电介质材料、未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅或其他可应用的材料。低k电介质材料的介电常数(k值)可以小于约3.9或者小于约2.8。金属化结构中的金属线可以由铜或铜合金形成。本领域的技术人员可以意识到金属化层的形成细节。
图2A示出了形成在衬底10上的导电区域12和钝化层14。导电区域12是形成在层间电介质层之上的金属化层。在一些实施例中，导电区域12是导电路线的一部分并具有通过平面化工艺(诸如化学机械抛光(CMP))处理的露出表面。用于导电区域12的适当材料可以包括但不限于例如，铜、铝、铜合金或其他移动导电材料，尽管其还可以由其他材料---诸如具有单层或多层结构的铜、银、金、镍、钨或它们的合金--形成或包括这些材料。在至少一个实施例中，导电区域12是焊盘区域、终端区域或导电线的互连点，其可以用于结合工艺以将各个芯片中的集成电路连接至外部部件。钝化层14形成在衬底10上并覆盖导电区域12。使用光刻和蚀刻工艺，钝化层14被图样化以形成露出导电区域12的一部分的开口。在至少一个实施例中，钝化层14由包括未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅或它们的组合的无机材料形成。在另一实施例中，钝化层14由聚合物层，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或类似物形成，尽管还可以使用其他相对较软、通常为有机的电介质材料。
图2A还示出了钝化层14上的下部UBM层16和上部UBM层18的形成。下部UBM层16和上部UBM层18通过形成在钝化层14中的开口连接至导电区域12。下部UBM层16形成在钝化层14和导电区域12的露出部分上。在至少一个实施例中，下部UBM层16包括扩散阻挡层。形成还被称为粘结层的扩散阻挡层，以覆盖钝化层14的开口的侧壁和底部。扩散阻挡层可以由钛(Ti)形成，尽管其还可以由其他材料，诸如氮化钛(TiN)、氧化钛(TiOx)、钽(Ta)、氮化钽(TaN)或它们的组合(例如，Ti/TiN、Ti/TiN/Ti或类似物)形成。形成方法包括物理气相沉积(PVD)或溅射。上部UBM层18形成在下部UBM层16。在至少一个实施例中，上部UBM层18是通过执行PVD或溅射形成的铜层。在一些实施例中，上部UBM层18由包括银、铬、镍、锡、金或其组合物的铜合金形成。下部UBM层16可具有大约1000至2000埃的厚度，而上部UBM层18可具有等于大约3000至7000埃的厚度，尽管它们的厚度还可以更大或更小。在整个说明书中引用的尺寸仅仅是示例性的，并且可以随着集成电路的比例缩减而按比例变化。
接下来，如图2B所示，掩模层20被设置在上部UBM层18上且例如通过曝光、显影或蚀刻利用开口21进行图样化，使得露出了上部UBM层18的一部分。在至少一个实施例中，掩模层20是湿光刻胶膜。在另一实施例中，掩模层20是干膜或有机材料。掩模层20的厚度可以大于约5微米(μm)，或者甚至在大约10μm和大约120μm之间。
接下来，如图2C所示，在掩模层20的开口21中成功形成金属化层22和焊料材料层25。在至少一个实施例中，金属化层22是镍层、铜层或它们的组合物。在一些实施例中，金属化层22是镍合金层，例如镍-钯-金(NiPdAU)、镍-金(NiAu)、镍-钯(NiPd)或其他类似合金。金属化层22具有小于10μm的厚度。在一些实施例中，金属化层22具有小于5μm的厚度，例如大约0.02至5μm，尽管该厚度还可以更大或更小。可通过电镀、无电或浸入式金属沉积工艺来沉积金属化层22。
通过电镀方法，焊料材料层24由Sn、SnAg、Sn-Pb、SnAgCu、SnAGZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等形成。在至少一个实施例中，焊料材料层24是无铅焊料材料层。焊料材料层24具有大于30μm的厚度。在一些实施例中，焊料材料层24具有大约40至100μm的厚度，尽管该厚度可以更大或更小。如图2C所示，在掩模层20的开口21中电镀焊料材料层24，并且焊料材料层24的高度不超过掩模层20的高度。这样，焊料材料层24在开口21内保持柱状。
参照图2D，随后从上部UBM层18去除掩模层20，随后为如图2E所示的上部UBM层18的未覆盖部分的蚀刻。在至少一个实施例中，利用清除浮渣工艺执行湿蚀刻工艺。例如，H2SO4和H2O2的混合物被用作蚀刻剂，并且清除浮渣工艺使用O2。在湿蚀刻工艺期间，蚀刻位于金属化层22下方的上部UBM层18的覆盖部分的边缘，形成向内延伸不大于4μm的底切。然后，执行O2清除浮渣工艺25，以氧化下部UBM层16和金属化层22的露出表面，用于避免随后回流工艺中的焊料润湿。
参照图2F，在焊料材料层24上执行热回流工艺，形成半球形焊料凸块24a。焊料凸块24a可以覆盖金属化层22和上部UBM层18以及它们之间的底切的侧壁。在一些实施例中，焊料凸块24a的直径可以为各种尺寸，并且可以包括所谓的“微凸块”。例如，焊料凸块24a的尺寸可以为65至80μm。焊料凸块24a之间的间距可以小于150μm(诸如130至140μm)，并且未来可以甚至更小。对于微凸块应用，间距可以为20至50μm，并且尺寸可以为10至25μm。
接下来，如图2G所示，将焊料凸块24a用作硬掩模，执行干蚀刻工艺以去除下部UBM凸块16的一部分。由于焊料凸块24a的周长，避免了下部UBM凸块16的底切。在干蚀刻工艺之后，下部UBM层16具有延伸到焊料凸块24a的周长外的外围区域16p。外围区域16p在金属化层22的边缘外大约4至10μm。
这完成了焊料凸块24a下方的UBM结构26。UBM结构26包括具有第一截面尺寸d1的第一金属化层M1(参照下部UBM层16)、具有第二截面尺寸d2的第二金属化层M2(参照上部UBM层18)和具有第三截面尺寸d3的第三金属化层M3(参照金属化层22)。在至少一个实施例中，d1＞d3。在另一实施例中，d3＞d2。在另一实施例中，d1＞d3＞d2。在一些实施例中，d1-d3＞8μm。在一些实施例中，d3-d2＞4μm。例如，d3-d2＝4至10μm。UBM制造方法将半球状焊料凸块用作硬掩模以限定下部UBM层16的尺寸。因此，解决了UBM底切问题，并且可以通过很好地控制焊料涂料的大小来控制UBM尺寸。
图3是根据本公开各个方面的制造具有UBM结构的半导体器件的另一方法的流程图。将省略与图1所示相同或类似的部分。
参照图3，方法300开始于块102，其中，在半导体衬底的上方形成下部UBM层和上部UBM层。方法300继续到块104，其中，在上部UBM层上形成具有开口的掩模层。方法300继续到块106，其中，在掩模层的开口中形成金属化层。方法300继续到块308，其中，在金属化层上形成焊料材料层。该焊料材料层被电镀以超过掩模层的厚度，从而形成蘑菇状焊料材料层。方法300继续到块110，其中，去除掩模层。方法300继续到块112，其中，执行湿蚀刻工艺以去除上部UBM层的未覆盖部分。方法300继续到块316，其中，执行干蚀刻工艺以将蘑菇状焊料材料层用作硬掩模来去除下部UBM层的一部分。方法300继续到块113，其中，执行O2清除浮渣工艺，以氧化金属化层和下部UBM层的露出表面。方法300继续到块114，其中，在焊料材料层上执行热回流工艺。热回流工艺将焊料材料层再成形为半球焊料凸块。UBM形成工艺可以缓解UBM底切问题并形成外围区域延伸到焊料凸块的边缘外侧的下部UBM层。
图4A至图4D是处于根据图3的方法的制造的各个阶段的半导体器件的一部分的截面图。将省略与图2A至图2D的描述相同或类似部分的解释。
参照图4A，在掩模20的开口中形成金属化层22之后，在金属化层22上电镀焊料材料层。可以控制焊料电镀工艺以形成高度超过掩模层20的高度的焊料材料层，从而以蘑菇状展开到掩模层20的开口之外，形成蘑菇状焊料材料层24b。如图4B所示，随后去除焊料掩模20。接下来，如图4C所示，通过湿蚀刻工艺去除上部UBM层18的未覆盖部分，在金属化层22和上部UBM层18之间创建底切。然后，将蘑菇状焊料材料层24b用作硬掩模来执行干蚀刻工艺，以去除下部UBM层16的一部分。由于蘑菇状焊料材料层24b的周长，避免了下部UBM层16的底切。在干蚀刻工艺之后，下部UBM层16具有延伸到金属化层22的边缘外的外围区域16p。外围区域16p在金属化层22的边缘外大约10至20μm。然后，执行O2清除浮渣工艺25，以氧化下部UBM层16和金属化层22的露出表面，用于避免随后回流工艺中的焊料润湿。接下来，如图4D所示，在焊料材料层24b上执行热回流工艺，形成半球形焊料凸块24c。
这完成了焊料凸块24c下方的UBM结构26″。UBM结构26″包括具有第一截面尺寸d1的第一金属化层M1(参照下部UBM层16)、具有第二截面尺寸d2的第二金属化层M2(参照上部UBM层18)和具有第三截面尺寸d3的第三金属化层M3(参照金属化层22)，其中，d1＞d3＞d2。UBM制造方法将蘑菇状焊料材料层24b用作硬掩模以限定下部UBM层16的尺寸。因此，解决了UBM底切问题，并且可以通过很好地控制焊料涂料的大小来控制UBM尺寸。
在前面的详细描述中，参照具体的示例性实施例描述了本公开。然而，明显地，在不背离本公开的精神和范围的情况下，可以进行各种修改、结构、处理和变化。因此，说明书和附图被认为是示例性而不是限制性的。应该理解，本公开能够使用各种其他组合和情况并且能够在本文所表示的发明概念的范围内进行改变或修改。

Claims (13)

1.一种半导体器件，包括：
半导体衬底；
底部凸块金属化UBM结构，覆盖所述半导体衬底；以及
焊料凸块，覆盖并电连接至所述UBM结构；
其中，所述UBM结构包括具有第一截面尺寸d1的第一金属化层、形成在所述第一金属化层上的具有第二截面尺寸d2的第二金属化层、以及形成在所述第二金属化层上的具有第三截面尺寸d3的第三金属化层，其中，d1大于d3，d3大于d2，并且
其中，所述焊料凸块覆盖所述第三金属化层和所述第二金属化层以及它们之间的底切的侧壁，
并且其中，所述第一金属化层具有氧化的表面且所述第三金属化层具有氧化的侧壁表面。
2.根据权利要求1所述的半导体器件，其中，所述第一金属化层包括钛Ti。
3.根据权利要求1所述的半导体器件，其中，所述第二金属化层包括铜Cu。
4.根据权利要求1所述的半导体器件，其中，所述第三金属化层包括镍Ni和铜Cu中的至少一种。
5.根据权利要求1所述的半导体器件，其中，所述焊料凸块包括无铅焊料材料。
6.一种形成半导体器件的方法，包括：
形成覆盖半导体衬底的第一金属化层；
形成覆盖所述第一金属化层的第二金属化层；
形成覆盖所述第二金属化层的具有开口的掩模层；
在所述掩模层的所述开口中形成第三金属化层；
形成覆盖所述第三金属化层的焊料材料层；
去除所述掩模层；
执行湿蚀刻工艺，以去除所述第二金属化层的未覆盖部分；
执行O2清除浮渣工艺，以使所述第一金属化层和所述第三金属化层具有氧化的暴露表面；
在所述焊料材料层上执行热回流工艺，以形成焊料凸块，所述焊料凸块覆盖所述第三金属化层和所述第二金属化层以及它们之间的底切的侧壁；以及
将所述焊料凸块用作硬掩模来执行干蚀刻工艺，以去除所述第一金属化层的一部分，
其中，在所述湿蚀刻工艺和所述干蚀刻工艺之后，所述第一金属化层具有第一截面尺寸d1，所述第二金属化层具有第二截面尺寸d2，以及所述第三金属化层具有第三截面尺寸d3，其中，d1大于d3，d3大于d2。
7.根据权利要求6所述的方法，其中，所述第一金属化层包括钛Ti层、氧化钛TiOx层、钽Ta层和氮化钽TaN层中的至少一种。
8.根据权利要求6所述的方法，其中，所述第二金属化层是铜Cu层。
9.根据权利要求6所述的方法，其中，所述第三金属化层包括镍Ni层和铜Cu层中的至少一种。
10.一种形成半导体器件的方法，包括：
形成覆盖半导体衬底的第一金属化层；
形成覆盖所述第一金属化层的第二金属化层；
形成覆盖所述第二金属化层的具有开口的掩模层；
在所述掩模层的所述开口中形成第三金属化层；
形成覆盖所述第三金属化层的蘑菇状焊料材料层；
去除所述掩模层；
执行湿蚀刻工艺，以去除所述第二金属化层的未覆盖部分；
将所述蘑菇状焊料材料层用作硬掩模来执行干蚀刻工艺，以去除所述第一金属化层的一部分；
执行O2清除浮渣工艺，以使所述第一金属化层和所述第三金属化层具有氧化的暴露表面；以及
在所述蘑菇状焊料材料上执行热回流工艺，以形成焊料凸块，其中，在所述湿蚀刻工艺和所述干蚀刻工艺之后，所述第一金属化层具有第一截面尺寸d1，所述第二金属化层具有第二截面尺寸d2，以及所述第三金属化层具有第三截面尺寸d3，其中，d1大于d3，d3大于d2，并且
其中，所述焊料凸块覆盖所述第三金属化层和所述第二金属化层以及它们之间的底切的侧壁。
11.根据权利要求10所述的方法，其中，所述第一金属化层包括钛Ti层、氧化钛TiOx层、钽Ta层和氮化钽TaN层中的至少一种。
12.根据权利要求10所述的方法，其中，所述第二金属化层是铜Cu层。
13.根据权利要求10所述的方法，其中，所述第三金属化层包括镍Ni层和铜Cu层中的至少一种。
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