TWI463623B - 半導體元件 - Google Patents

半導體元件 Download PDF

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Publication number
TWI463623B
TWI463623B TW100124066A TW100124066A TWI463623B TW I463623 B TWI463623 B TW I463623B TW 100124066 A TW100124066 A TW 100124066A TW 100124066 A TW100124066 A TW 100124066A TW I463623 B TWI463623 B TW I463623B
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TW
Taiwan
Prior art keywords
layer
copper
metal
bump
bond pad
Prior art date
Application number
TW100124066A
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English (en)
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TW201212191A (en
Inventor
Weicheng Wu
Shangyun Hou
Shinpuu Jeng
Tzuanhorng Liu
Tzuwei Chiu
Chaowen Shih
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
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Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201212191A publication Critical patent/TW201212191A/zh
Application granted granted Critical
Publication of TWI463623B publication Critical patent/TWI463623B/zh

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Description

半導體元件
本揭露一般是有關於一種半導體元件，且特別是有關於一種具有接合墊(Pad/Bond Pad)結構之半導體元件，其中接合墊結構設有應力緩衝(Stress Buffer)層。
現代積體電路(IC)確實是由數百萬個如電晶體之主動元件與電容所組成。此些元件開始時是彼此分離，但隨後則被內連接(Interconnected)在一起以形成功能性電路。典型的內連接結構包含橫向(Lateral)內連接[例如金屬線(導線)]以及垂直(Vertical)內連接[例如介層窗(Vias)與接觸窗(Contacts)]。內連接正逐漸地決定了現在IC之性能與密度的限制。在內連接結構的頂端，接合墊係形成且暴露於個別晶片之表面。經由接合墊之電性連接係用以連接上述之晶片至封裝基材(Package Substrate)或另一晶粒(Die)。接合墊可使用在導線接合(Wire Bonding)或覆晶(Flip-Chip)接合中。由於成本低，晶圓級晶片尺寸封裝(Wafer Level Chip Scale Packaging；WLCSP)係目前廣泛使用且相對簡單的製程。在典型的WLCSP中，內連接結構形成在金屬化層(Metallization Layers)上，接著形成凸塊下金屬(Under-Bump Metallurgy/Under-Bump Metallization；UBM)並設置銲球(Solder Balls)。
覆晶封裝利用凸塊來建立晶片之輸入/輸出(I/O)接合墊與封裝基材之間，或與封裝導線框(Lead Frame)之間的電性接觸。就結構上來說，凸塊實際上包含凸塊本身以及位在凸塊與I/O接合墊之間的所謂的UBM。UBM一般包含利用以下所述順序配置在I/O接合墊上的黏合(Adhesion)層、阻障(Barrier)層以及潤濕(Wetting)層。根據所使用之材料，凸塊本身可區分為錫凸塊、金凸塊、銅(Copper/Cu)柱(Pillar)凸塊以及混合金屬(Mixed Metals)凸塊。最近提出有銅內連線柱(Interconnect Post)技術。以銅柱元件取代原來所使用之錫凸塊，來連接電子元件與一基材。上述銅內連線柱技術以最小之凸塊橋接(Bridging)可能性來達到較細的節距(Pitch)，降低電路的電容負載，並允許電子元件以較高頻率來執行。而錫合金仍然是必須的，其係用以覆蓋(Capping)凸塊結構以及接合電子元件。
WLCSP以及相關之覆晶封裝中之物理應力係與多項因素(Factors)的結合有關，例如元件尺寸、架構(Architecture)、操作狀況、以及實際的封裝設計與建構材料。然而，低介電常數材料的使用產生了封裝時施加於元件上之應力的關鍵問題。此外，在銅柱的介紹中包含了較錫凸塊更高的應力，因此需要應力緩衝層或應力重新分配(Re-Distribution)層。聚亞醯胺(Polyimide；PI)可做為應力緩衝以降低金屬凸塊區底下之低介電係數層的最大應力，但相對的，其亦衝擊元件的性能。例如，PI層需要高溫與長時間的固化程序(Curing Process)，故導致大體積PI的收縮，進而對矽產生了大的殘留(Residual)應力。常見之失效模式為沿著晶粒角落或PI層與底部填充(Underfill)材料間之介面的脫層(Delamination)或破裂(Cracking)。
本發明之目的在提供一種半導體元件，半導體元件之接合墊結構中設有環狀之應力緩衝層，藉由此小面積之應力緩衝層來降低上述沿著晶粒角落或PI層與底部填充材料間之介面產生脫層或破裂的缺陷。
根據本發明之一態樣，提供一種半導體元件。此半導體元件包含位在半導體基材之上的金屬接合墊、位在上述金屬接合墊之上的保護層、位在上述保護層及金屬接合墊之上的環狀層、位在上述環狀層之上的UBM層以及位在上述UBM層之上的金屬凸塊。上述保護層暴露出金屬接合墊的第一部分，而環狀層則暴露出金屬接合墊的第二部分，其中金屬接合墊的第二部分係位在金屬接合墊的第一部分之內。至於UBM層則電性連接至上述金屬接合墊的第二部分。
根據本發明之另一態樣，提供一種半導體元件。此半導體元件包含位在半導體基材之上的金屬接合墊、位在上述金屬接合墊之上的保護層、位在上述保護層之上的內連接線、位在上述內連接線之上的阻障層、位在上述阻障層之上的環狀層、位在上述環狀層之上的UBM層以及位在上述UBM層之上的金屬凸塊。上述保護層暴露出金屬接合墊的一部分，而內連接線係電性連接至上述金屬接合墊被暴露出的部分。此外，上述阻障層暴露出內連接線的一部分，而環狀層電性連接至內連接線被暴露出的部分，且UBM層亦電性連接至內連接線被暴露出的部分。
根據本發明之再一態樣，提供一種製造半導體元件之方法。此方法包含提供具有傳導區之半導體基材；形成位在上述半導體基材之上的介電層；形成第一開口部於上述介電層中，藉以暴露出傳導區的一部分；形成位在上述介電層之上的環狀層，其中環狀層暴露出上述傳導區被暴露出部分的至少一部份；形成UBM層，其中UBM層係位在上述環狀層、介電層與傳導區之上；形成具有第二開口部的遮罩層，其中遮罩層係位在UBM層之上；形成傳導材料層於上述遮罩層之第二開口部中，且傳導材料層電性連接至UBM層；以及移除上述之遮罩層。
本發明之優點為，藉由在半導體元件之接合墊結構中設置小面積之環狀應力緩衝層，可降低上述脫層或破裂的缺陷。因此，可提升半導體元件之良率，增加產能，亦可改善半導體元件之可靠度。
本揭露提供具有接合墊結構之半導體元件及形成此半導體元件之製程，其中接合墊結構設有應力緩衝層。上述半導體元件可具有銅柱、柱保護(Passivation)內連線、銲料凸塊、及/或製造於其中之穿透矽介層窗(Through-Silicon Vias；TSVs)，其中半導體元件可應用於覆晶組裝(Assembly)、WLCSP、三維積體電路(3D-IC)堆疊、及/或任何先進封裝技術領域。以下將參照相應圖式中之例示性實施例做詳細的說明。只要有可能，使用在圖式與說明中之相同參考號碼係用以表示相同或類似的部分。在圖式中，為了清楚與方便起見，形狀與厚度可能被誇張化。本揭露將特別地被導引至，形成符合本揭露之裝置之一部分的元件，或與符合本揭露之裝置更直接相關共同運作的元件。可理解的是，未特別繪示或描述之元件可採用熟悉此技藝者所熟知的各種型式。此外，當稱一層係位在另一層之上，或位在一基材之上，其可表示此一層係直接位在另一層或基材之上，或亦可包含有中間層(Intervening Layer)。在整分說明書中，對應於一實施例之參照係表示，被描述成與此實施例相關之特定特徵、結構或特性係至少包含在一實施例中。因此，在整分說明書中多處所使用之「在一實施例中」的用詞，並不需要全部均指相同的實施例。再者，特定之特徵、結構或特性可用任何適當之方式結合至一個或多個實施例中。可以明白的是，相應之圖式並未依比例繪示，而其中此些圖式僅係做為說明之用。
第1圖係繪示根據本揭露之各種觀點之製造半導體元件之方法100的流程圖。請參照第1圖，方法100開始於區塊101，以在半導體基材上形成金屬接合墊。方法100繼續進行至區塊102，以在半導體基材上形成保護層。圖案化保護層以形成開口，藉以暴露出上述金屬接合墊之主要部分。方法100繼續進行至區塊103，以在保護層上形成應力緩衝層。將應力緩衝層圖案化成一環狀(Ring-Shaped)層以具有一內部開口部，藉以暴露出上述金屬接合墊之主要部分的至少一部分。方法100繼續進行至區塊104，以在應力緩衝層上、保護層上以及金屬接合墊被暴露出之部分上形成UBM層。方法100繼續進行至區塊105，在UBM層上形成金屬凸塊，使得金屬凸塊電性連接至金屬接合墊。
第2至6圖係繪示根據第1圖之方法100之一個或多個實施例之半導體元件之各個製造階段的部分剖面示意圖。
請參照第2圖，其係繪示晶圓2的剖面示意圖。晶圓2包含使用於半導體IC製造中的半導體基材10，且IC可形成在晶圓2之中及/或之上。半導體基材10被定義成指包含有半導體材料的任何架構，其中半導體材料包含(但並不侷限)塊狀矽(Bulk Silicon)、半導體晶圓、絕緣層上覆矽(Silicon-On-Insulator；SOI)基材、或矽鍺(Germanium)基材。其他半導體材料(包含三族、四族與五族元素)亦可加以使用。半導體基材10更可包含多個隔離特徵(未繪示)，例如淺溝渠隔離(Shallow Trench Isolation；STI)特徵或矽區域氧化(LOCOS)特徵。隔離特徵可定義並隔離各種微電子元件12。可形成在半導體基材10中之各種微電子元件12的例子包含電晶體[例如金屬氧化物半導體場效應電晶體(MOSFET)、互補式金屬氧化物半導體(CMOS)電晶體、雙極接面電晶體(BJT)、高壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體(PFETs/NFETs)等]、電阻、二極體(Diodes)、電容(Capacitors)、電感(Inductors)、保險絲(Fuses)或其他適當的元件。可執行各種製程以形成各種的微電子元件，其中包含沉積(Deposition)、蝕刻(Etching)、植入(Implantation)、微影(Photolithography/Lithography)、退火(Annealing)、或其他適當的製程。內連接上述之微電子元件12以形成IC元件，例如邏輯元件、記憶體元件[例如靜態隨機存取記憶體(SRAM)]、無線射頻(Radio Frequency；RF)元件、I/O元件、系統整合晶片(System-On-Chip；SoC)元件、上述元件之組合、或其他適當型態之元件。在其他實施例中，晶圓2係中介層(Interposer)晶圓或封裝基材之晶圓，且實質未包含IC元件形成於其中，其中IC元件包含電晶體、電阻、電容、電感及/或類似之元件。在此些實施例中，半導體基材10可利用半導體材料、介電材料[例如氧化矽(Silicon Oxide)]或玻璃材料來形成。
第2圖亦繪示形成在半導體基材10之上的內連接結構14與第一保護層16。內連接結構14包含形成於其中之金屬線與介層窗(未繪示)，且電性耦合至微電子元件12(亦稱之為半導體元件12)。金屬線與介層窗可用銅或銅合金來形成，且可使用鑲嵌(Damascene)製程來形成。內連接結構14包含內層介電(Inter-Layer Dielectric；ILD)層與內金屬介電(Inter-Metal Dielectric；IMD)層其中至少一者。在特定之實施例中，上述ILD層或IMD層包含氧化矽、氮化矽(Silicon Nitride)、氮氧化矽(Silicon Oxynitride)或低介電常數介電材料。形成在內連接結構14之上的第一保護層16為一介電材料層，其中上述之介電材料層可用低介電常數介電材料、未摻雜矽玻璃(Un-doped Silicate Glass；USG)、氮化矽、氮氧化矽、或其他常用材料來形成。低介電常數介電材料之介電常數(K值)可小於約3.9，或小於約2.8。
金屬接合墊材料係沉積在第一保護層16之上，且接著圖案化以在不同的凸塊區I及II形成多個金屬接合墊18。至少一金屬接合墊18可電性連接至下層的內連接結構14。至少一金屬接合墊18可電性耦合至半導體元件12(例如經由內連接結構14)。在特定之實施例中，金屬接合墊18包含鋁(Al)、銅、銀(Silver/Ag)、金(Au)、鎳(Nickel/Ni)、鎢(Tungsten/W)、上述元素之合金、及/或上述元素之複合層。接著第二保護層20形成在晶圓2之上，其中第二保護層20被圖案化以包含分別暴露出下層之金屬接合墊18的開口部20a。在凸塊區I或II中，第二保護層20暴露出金屬接合墊18的主要部分18A。在特定之實施例中，第二保護層20可覆蓋金屬接合墊18的邊緣部分18E。第二保護層20係用高分子聚合物(Polymer)層[例如環氧樹脂(Epoxy)、PI、苯環丁烯(Benzocyclobutene；BCB)、聚苯噁唑(Polybenzoxazole；PBO)或類似之物質]來形成，雖然亦可採用其他相對較軟質(經常為有機的)之介電材料。在其他特定之實施例中，第二保護層20係用選自於USG、氮化矽、氮氧化矽、氧化矽或上述材料之組合之非有機材料來形成。
接著，緩衝材料沉積在晶圓2上，且接著圖案化以在凸塊區I及II中形成多個應力緩衝層24。上述多個應力緩衝層24係彼此分離。在凸塊區I或II中，應力緩衝層24覆蓋部分之第二保護層20與金屬接合墊18，並暴露出金屬接合墊18之主要部分18A的部分18B。應力緩衝層24係具有內部開口部24a之環狀體。在特定之實施例中，內部開口部24a係設置在開口部20a之內，且具有小於開口部20a之直徑，因此，暴露出的部分18B小於金屬接合墊18之主要部分18A。在特定之實施例中，內部開口部24a係沉積在開口部20a之內，且具有大於或等於開口部20a之直徑，因此，暴露出的部分18B係實質等於主要部分18A。在一凸塊區中，金屬接合墊18與應力緩衝層24的結合做為接合墊結構22，藉以電性連接外部終端(External Terminal)。
在至少某些特定之實施例中，緩衝材料的選擇係以如材料之介電常數，或材料之拉伸(Tensile)強度(延長至破斷)或楊氏係數(Young’s Modulus)為依據。在特定之實施例中，應力緩衝層24係用介電材料[如具有小於3.5之介電常數之低介電常數介電材料、USG或氟化矽酸鹽玻璃(Fluorinated Silica Glass；FSG)]來形成。在特定之實施例中，應力緩衝層24係用高分子聚合物材料(例如PI、BCB、PBO或環氧樹脂)來形成。特定之實施例中，應力緩衝層係用金屬層(例如鋁或銅)來形成。
如第2圖所繪示之實施例的俯視圖係描繪於第3A至3C圖中。多個應力緩衝層24可如所見配置在第二保護層20上。在以上所述之實施例中，應力緩衝層24為環狀層，其中環狀層係彼此分離，並分別位在凸塊區中。應力緩衝層24可為任何幾何形狀之環狀層。在特定之實施例(如第3A圖所示之實施例)中，接合墊結構22A包含形成圓形環之應力緩衝層24A。在特定之實施例(如第3B圖所示之實施例)中，接合墊結構22B包含形成方形環之應力緩衝層24B。在特定之實施例(如第3C圖所示之實施例)中，接合墊結構22C包含形成八邊形(Octagonal)環之應力緩衝層24C。其他未描述或繪示於此之實施例可具有其他形狀，例如橢圓形(Ovals)、其他正多邊形(Regular Polygons)或非正(Irregular)多邊形。在更進一步之實施例中，在相同晶圓上組合多種形狀係可能的，例如一晶圓上包含圓形(Circular)、方形以及多邊形之環狀應力緩衝層。環狀應力緩衝層24可從第二保護層20之邊緣延伸僅幾微米(Microns；μm)。在特定之實施例中，應力緩衝層24具有介於約2μm至10μm的厚度。
接著，請參照第4圖，UBM層26形成在晶圓2之上，以覆蓋第二保護層20、應力緩衝層24以及金屬接合墊18被暴露之部分18B。在特定之實施例中，UBM層26包含擴散阻障(Diffusion Barrier)層或黏著(Glue)層，其中擴散阻障層與黏著層係藉由物理氣相沉積(Physical Vapor Deposition；PVD)或濺鍍(Sputtering)沉積鈦(Titanium)、鉭(Tantalum)、氮化鈦(Titanium Nitride)、氮化鉭(Tantalum Nitride)或類似之材料來形成，且其厚度係介於約500至2000埃(Angstrom；)。在特定之實施例中，UBM層26包含形成於擴散阻障層上之晶種層(Seed Layer)，其中晶種層係藉由PVD或濺鍍沉積至介於約500至10000的厚度。上述晶種層可用銅或銅合金來形成，其中銅合金包含銀、鉻(Chromium)、鎳、錫(Tin/Sn)、金或上述元素之組合。
接著如第5圖所示，形成遮罩層28於UBM層26上。圖案化遮罩層28以形成開口部28a於其中，以便暴露出位在不同凸塊區之UBM層26的一部分。遮罩層28可為乾膜(Dry Film)或光阻(Photoresist)膜，其中遮罩層28可藉由微影及/或蝕刻製程。第5圖亦繪示有位於開口部28a中且具有銲料可濕性(Solder Wettability)之傳導(Conductive)材料的形成。在一實施例中，多個銅層30係分別形成於多個開口部28a中以接觸下層的UBM層26。在本揭露之所有內容中，「銅層」之用詞係欲實質包含具有純元素銅、包含不可避免雜質的銅、或包含份量較少之元素之銅合金的層，其中上述份量較少之元素可如鉭、銦(Indium/In)、錫、鋅(Zinc)、錳(Manganese)、鉻、鎳、鍺、鍶(Strontium)、鉑(Platinum)、鎂(Magnesium)、鋁或鋯(Zirconium)。形成之方法可包含濺鍍、印製(Printing)、電鍍(Electro Plating)、或化學氣相沉積法(Chemical Vapor Deposition；CVD)。例如，執行電化學電鍍(Electro-Chemical Plating；ECP)以形成銅層30。在一實施例中，銅層30的厚度係大於25μm。在另一實施例中，銅層30的厚度係大於40μm。例如，銅層30約為40至50μm厚，或約40至70μm厚，雖然上述之厚度可更大或更小。
在此之後，如第6圖所示，從UBM層26移除遮罩層28，因此暴露出銅層30的側壁表面。在以下之說明書中，從UBM層26凸出之銅層30被稱之為銅柱30。處理程序進行至使用銅柱30做為遮罩以蝕刻UBM層26暴露出來的部分，因此暴露出銅柱30之外的第二保護層20及應力緩衝層24。
上述步驟在晶圓2上之不同凸塊區I及II中完成多個凸塊結構32。在凸塊區I或II中，凸塊結構32包含銅柱30、由銅柱30覆蓋之UBM層26、以及位在UBM層26底下之接合墊結構22。接合墊結構22包含金屬接合墊18與環狀之應力緩衝層24，且第二保護層20係形成於上述二者之間。第二保護層20覆蓋金屬接合墊18之邊緣部分18E，並暴露出金屬接合墊18之主要部分18A。形成於第二保護層20上之環狀應力緩衝層24暴露出主要部分18A的部分18B。因此，形成在金屬接合墊18之上的UBM層26可接觸金屬接合墊18被暴露出的部分18B。環狀應力緩衝層24從UBM層26的邊緣延伸一距離D。在特定之實施例中，距離D係約5μm至15μm。在其他之實施例中，從金屬接合墊18之外側邊緣開始量測，環狀應力緩衝層24可延伸約5μm至15μm。接著鋸開(Saw)晶圓2，並以銲球或銅凸塊將其封裝至一封裝基材或另一晶粒上，其中上述之銲球或銅凸塊係裝設在上述封裝基材或另一晶粒的接合墊上。
本揭露所揭露之接合墊結構22，其中環狀之應力緩衝層24係位在金屬接合墊18之上。環狀之應力緩衝層24係分別設置在凸塊區中，其中環狀之應力緩衝層24係彼此分離。比較使用PI層且在晶圓上具有大覆蓋面積之方法，環狀之應力緩衝層24具有較小之尺寸，且從UBM層26延伸一較小之距離，此方法可透過凸塊降低大的殘留應力並緩解(Relieve)外部應力負荷，其中上述殘留應力與應力負荷係由熱的不匹配(Thermal Mismatch)或溫度循環所引起。當與錫/鉛(Lead)銲料凸塊相比較時，雖然銅柱施加(Place)了額外的應力於矽晶片上，但是藉著區域化環狀應力緩衝層於凸塊區之上，較厚之應力緩衝層可用來避免相對應之壓縮(Compressive)負載或拉伸負載非必要性地施加在矽基材上。
第7圖係繪示根據第1圖所示方法之一實施例之晶圓製造過程中之晶圓一部分的剖面示意圖。與第2至6圖之描述相同或相似部分的說明將加以省略。在第7圖中繪示有形成於銅柱30之頂表面上的遮蔽(Cap)層34以及形成於遮蔽層34上的銲料層36。遮蔽層34與銲料層36係在移除遮罩層28之前依次地沉積於銅層30之上，並在UBM之蝕刻製程後仍維持在銅柱30之上。遮蔽層34係做為阻障層以避免銅柱30中的銅擴散至接合材料(例如銲料合金)中，其中接合材料係用來接合半導體基材10至外部特徵。銅擴散的避免增加封裝的可靠度以及接合強度。遮蔽層34可包含鎳、錫、錫鉛(Tin-Lead/SnPb)、金、銀、鈀(Palladium/Pd)、銦、鎳鈀金(NiPdAu)、鎳金(NiAu)、其他類似材料、或以電鍍方式沉積之合金。遮蔽層34具有約1μm至10μm的厚度。在特定之實施例中，遮蔽層34係用鎳、金、鈀、鎳基(Ni-Based)合金、金基合金、鈀基合金或上述材料之組合來形成。在特定之實施例中，銲料層36係用錫、錫銀(SnAg)、錫鉛、錫銀銅(SnAgCu)[其中銅之重量百分比(wt%)小於0.3%]、錫銀鋅(SnAgZn)、錫鋅(SnZn)、錫鉍銦(SnBiIn)、錫銦(SnIn)、錫金(SnAu)、錫銅(SnCu)、錫鋅銦(SnZnIn)或錫銀銻(SnAgSb)等，以及電鍍製程來形成。在一實施例中，銲料層36為無鉛(Lead-Free)銲料層。在無鉛銲料系統中，銲料層為錫銀，其中銀含量係控制在小於3.0 wt%。例如，無鉛銲料層為錫銀，且銀含量控制在約2.5 wt%。可執行迴銲(Reflowing)製程於銲料層36，藉以形成銲球於遮蔽層34之上。
在額外之其他實施例中，環狀應力緩衝層24係使用於銲料凸塊中，而不是使用於銅柱凸塊中。第8與9圖係繪示根據第1圖中方法100之一實施例之半導體元件製造過程中各階段之半導體元件的部分剖面示意圖。與第2至6圖之描述相同或相似部分的說明將加以省略。
比較描繪於第5圖中之製程，銅柱的形成係由銲料凸塊製程中之薄銅層所取代，且緊接在銲料凸塊製程之後形成阻障層與銲料層。請參照第8圖，在形成遮罩層28於UBM層26之上後，薄銅層40沉積在UBM層26之上的開口部28a中。薄銅層40具有相對於銅柱30較薄的厚度。在特定之實施例中，薄銅層40具有小於10μm的厚度。在特定之實施例中，薄銅層40具有約為4μm至6μm的厚度，雖然薄銅層40的厚度可以更厚或更薄。薄銅層40形成方法可包含濺鍍、印製、電鍍、無電電鍍(Electroless Plating)、與CVD等方法。
阻障層44(選擇性的層)接著形成於薄銅層40之上的開口部28a中。阻障層44係用銅、鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其他類似材料、或合金以及電鍍方法來形成。阻障層44具有小於10μm的厚度。在特定之實施例中，阻障層44有小於5μm的厚度。接著，銲料層46形成於阻障層44之上的開口部28a中。在一實施例中，銲料層46為無鉛銲料層。在特定之實施例中，銲料層46係用錫、錫銀、錫鉛、錫銀銅[其中銅之重量百分比小於0.3%]、錫銀鋅、錫鋅、錫鉍銦、錫銦、錫金、錫銅、錫鋅銦或錫銀銻等，以及電鍍製程來形成。在移除遮罩層28之後(接著執行UBM之蝕刻製程)。對銲料層46執行迴銲以形成銲球。因此，迴銲銲料層46”、阻障層44以及薄銅層40被稱之為銲料凸塊結構。
在額外之其他實施例中，環狀應力緩衝層24係使用於銲料凸塊中，其中銲料凸塊係位在後護層內連接(Post-Passivation Interconnect；PPI)結構之上。第10圖係繪示根據本揭露之各種觀點之製造半導體元件之方法200的流程圖。請參照第10圖，方法200開始於區塊201，藉以形成PPI結構於半導體基材之上。方法200繼續進行至區塊202，以在PPI結構之上形成阻障層。圖案化阻障層以形成開口，藉以暴露出上述PPI結構之一部分。方法200繼續進行至區塊203，以在阻障層上形成應力緩衝層。將應力緩衝層圖案化成一環狀層以具有一內部開口部，藉以暴露出上述PPI結構被暴露出之部分的至少一部分。方法200繼續進行至區塊204，以在應力緩衝層上以及PPI結構被暴露出之部分上形成UBM層。方法200繼續進行至區塊205，在UBM層上形成金屬凸塊，使得金屬凸塊電性連接至PPI結構。
第11至14圖係繪示根據第10圖之方法200之一實施例之半導體元件之各個製造階段的部分剖面示意圖。與第2至6圖之描述相同或相似部分的說明將加以省略。
比較描繪於第2圖中之製程，提供PPI結構於第二保護層之上，接著形成環狀應力緩衝層。請參照第11圖，第二保護層20係形成在晶圓4之上，藉此暴露出位在不同凸塊區I及II的金屬接合墊18。在特定之實施例中，第二保護層20包含第一層19與第二層21。在凸塊區I或II中，第一層19係形成在第一保護層16之上，並加以圖案化以形成第一開口部19a，而暴露出金屬接合墊18的主要部分18A(亦可稱之為第一部分18A)。第二層21係形成在第一層19之上，並加以圖案化以形成第二開口部21a，藉以暴露出金屬接合墊18的部分18B(亦可稱之為第二部分18B)。第二部分18B係形成在第一部分18A之內。在特定之實施例中，第一層19與第二層21係用非有機材料來形成，其中非有機材料係選自於未摻雜矽玻璃、氮化矽、氮氧化矽、氧化矽或上述材料之組合。在特定之實施例中，第一層19與第二層21係用高分子聚合物層來形成，例如環氧樹脂、PI、BCB、PBO及類似之物質。第一層19與第二層21可用相同或不同的材料來形成。
接著，傳導材料層沉積在晶圓4之上，覆蓋住第二保護層20，並與金屬接合墊18被暴露出之第二部分18B接觸。接著圖案化傳導材料層以形成配置在凸塊區I與II之中的內連接線50。在凸塊區I或II中，內連接線50(亦稱之為PPI線50)包含電性連接至金屬接合墊18之第一端50A1 、電性連接至UBM層之第二端50A2 、以及形成於後續製程中之金屬凸塊。PPI線50包含(但未限制)如銅、鋁、銅合金或其他具有可移動載子之傳導材料。在特定之實施例中，PPI線50更可在含銅層之頂部包含一含鎳層(未繪示)。PPI之形成方法包含電鍍、無電電鍍、濺鍍、CVD方法以及類似之方法。PPI線50在功能上亦可做為電力線(Power Lines)、重新分配線(Re-Distribution Lines；RDL)、電感、電容、或任何被動(Passive)元件。PPI線50可具有小於約30μm的厚度，例如介於約2μm至約25μm。
請參照第12圖，阻障層52接著形成在晶圓4之上，藉以覆蓋PPI線50以及第二保護層20被暴露出的部分。使用微影以及蝕刻製程來進一步圖案化阻障層52，藉此分別形成暴露出PPI線50之第二端50A2 的開口部52a。在特定之實施例中，阻障層52係用選自於USG、氮化矽、氮氧化矽、氧化矽與上述材料之組合之非有機材料來形成。在特定之實施例中，阻障層52係用高分子聚合物層(例如環氧樹脂、PI、BCB、PBO與類似之物質)來形成，雖然亦可採用其他相對較軟質(經常為有機的)之介電材料。
接著，如第13圖所示，多個環狀應力緩衝層24形成於凸塊區I與II中之阻障層52之上。應力緩衝層24係彼此分離。在凸塊區I或II中，應力緩衝層24覆蓋阻障層52的一部分，且至少暴露出PPI線50之第二端50A2 的一部分。應力緩衝層24之內部開口部24a可小於、大於或等於阻障層52的開口部52a。在一凸塊區中，PPI線50之第二端50A2 與應力緩衝層24之結合係做為電性連接外部終端之接合墊結構54。應力緩衝層24可為任何幾何形狀之環狀層。在特定之實施例中，應力緩衝層24係形成圓形環。在特定之實施例中，應力緩衝層24係形成方形環。在特定之實施例中，應力緩衝層24係形成八邊形環。在更進一步之實施例中，在相同晶圓上組合多種形狀係可能的，例如一晶圓上包含圓形、方形以及多邊形之環狀應力緩衝層。環狀應力緩衝層24可從阻障層52之邊緣延伸幾μm或數十μm。
以下，請參照第14圖，UBM層56與銲球58係形成在凸塊區中環狀應力緩衝層24以及PPI線50被暴露出之部分之上，其中凸塊區使用了包含UBM沉積、遮罩製程、薄銅層沉積、銲料層沉積、遮罩剝除(Stripping)製程、UBM蝕刻製程以及銲料迴銲製程之凸塊形成方法。在其他之實施例中，使用在PPI線50之上係銅柱凸塊，而不是銲料凸塊中。接著鋸開晶圓4，並以銲球或銅凸塊將其封裝至一封裝基材或另一晶粒上，其中上述之銲球或銅凸塊係裝設在上述封裝基材或另一晶粒的接合墊上。
在前述之詳細描述中，本揭露係參照特定之例示性實施例來加以描述。然而，很顯然的，在不脫離本揭露之廣義的精神和範圍內，當可做各種修改、結構、程序、與改變。因此，本說明書與圖式係被視為說明之用，而並非用以限制本發明之範圍。可以理解的是，本揭露之實施例可使用各種其他之結合與環境，且在如以上所述之本發明的範圍內可做改變或修改。
2．．．晶圓
4．．．晶圓
10．．．半導體基材
12．．．微電子元件
14．．．內連接結構
16．．．第一保護層
18．．．金屬接合墊
18A．．．主要部分
18B．．．部分
18E．．．邊緣部分
19．．．第一層
19a．．．第一開口部
20．．．第二保護層
20a．．．開口部
21．．．第二層
21a．．．第二開口部
22．．．接合墊結構
22A．．．接合墊結構
22B．．．接合墊結構
22C．．．接合墊結構
24．．．應力緩衝層
24a．．．內部開口部
24A．．．應力緩衝層
24B．．．應力緩衝層
24C．．．應力緩衝層
26．．．UBM層
28．．．遮罩層
28a．．．開口部
30．．．銅層
32．．．凸塊結構
34．．．遮蔽層
36．．．銲料層
40．．．薄銅層
44．．．阻障層
46．．．銲料層
46”．．．迴銲銲料層
50．．．內連接線
50A1 ．．．第一端
50A2 ．．．第二端
52．．．阻障層
52a．．．開口部
54．．．接合墊結構
56．．．UBM層
58．．．銲球
100．．．製造半導體元件之方法
101．．．區塊
102．．．區塊
103．．．區塊
104．．．區塊
105．．．區塊
200．．．製造半導體元件之方法
201．．．區塊
202．．．區塊
203．．．區塊
204．．．區塊
205．．．區塊
D．．．距離
I．．．凸塊
II．．．凸塊區
為了對本發明之實施例及其優點有更完整之理解，現請參照以上之說明並配合相應之圖式。相關圖式內容說明如下。
第1圖係繪示根據本揭露之各種觀點之製造半導體元件之方法的流程圖。
第2至6圖係繪示根據第1圖之方法之一實施例之半導體元件之各個製造階段的部分剖面示意圖。
第7圖係繪示根據第1圖中方法之一實施例之晶圓製造過程中之晶圓的部分剖面示意圖。
第8與9圖係繪示根據第1圖中方法之一實施例之晶圓製造過程中各階段之晶圓的部分剖面示意圖。
第10圖係繪示根據本揭露之各種觀點之製造半導體元件之方法的流程圖，其中半導體元件係具有PPI結構。
第11至14圖係繪示根據第10圖之方法之一實施例之晶圓之各個製造階段的部分剖面示意圖。
2．．．晶圓
16．．．第一保護層
20．．．第二保護層
24．．．應力緩衝層
26．．．UBM層
30．．．銅層
34．．．遮蔽層
36．．．銲料層

Claims (4)

  1. 一種半導體元件，包含：一金屬接合墊，位在一半導體基材之上；一保護層，位在該金屬接合墊之上，且該保護層暴露出該金屬接合墊的一部分；一內連接線，位在該保護層之上，且該內連接線電性連接至該金屬接合墊被暴露出的該部分；一阻障層，位在該內連接線之上，且該阻障層暴露出該內連接線的一部分；一環狀層，位在該阻障層之上，且該環狀層電性連接至該內連接線被暴露出的該部分；一凸塊下金屬層，位在該環狀層之上，且該凸塊下金屬層電性連接至該內連接線被暴露出的該部分；以及一金屬凸塊，位在該凸塊下金屬層之上。
  2. 如請求項1所述之半導體元件，其中該環狀層包含高分子聚合物層、一介電層、或至少一鋁層與一銅層，其中該介電層具有小於3.5之介電常數。
  3. 如請求項1所述之半導體元件，其中該金屬凸塊包含一銅層以及位在該銅層之上的一銲球。
  4. 如請求項1所述之半導體元件，其中該環狀層包含至少一圓形環、一方形環以及一八邊形環。
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US8283781B2 (en) 2012-10-09
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