CN102403290B - 半导体组件及制造半导体组件的方法 - Google Patents

半导体组件及制造半导体组件的方法 Download PDF

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Publication number
CN102403290B
CN102403290B CN201110204956.XA CN201110204956A CN102403290B CN 102403290 B CN102403290 B CN 102403290B CN 201110204956 A CN201110204956 A CN 201110204956A CN 102403290 B CN102403290 B CN 102403290B
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layer
circular
bond pads
metal
copper
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CN102403290A (zh
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吴伟诚
侯上勇
郑心圃
刘醇鸿
邱志威
史朝文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体组件及制造半导体组件的方法，半导体组件包含接合垫结构，其中接合垫结构具有介于金属接合垫与凸块下金属(UBM)层的环状应力缓冲层。应力缓冲层是用介电层、高分子聚合物层或铝层来形成，其中介电层具有小于3.5的介电常数。上述应力缓冲层是圆形环、方形环、八边形(Octagonal)环或任何几何形状的环。

Description

半导体组件及制造半导体组件的方法
技术领域
本发明一般是有关于一种半导体组件，且特别是有关于一种具有接合垫(Pad/Bond Pad)结构的半导体组件，其中接合垫结构设有应力缓冲(Stress Buffer)层。
背景技术
现代集成电路(IC)确实是由数百万个如晶体管的主动组件与电容所组成。这些组件开始时是彼此分离，但随后则被内连接(Interconnected)在一起以形成功能性电路。典型的内连接结构包含横向(Lateral)内连接[例如金属线(导线)]以及垂直(Vertical)内连接[例如介层窗(Vias)与接触窗(Contacts)]。内连接正逐渐地决定了现在IC的性能与密度的限制。在内连接结构的顶端，接合垫是形成且暴露于个别芯片的表面。经由接合垫的电性连接是用以连接上述的芯片至封装基材(Package Substrate)或另一晶粒(Die)。接合垫可使用在导线接合(WireBonding)或覆晶(Flip-Chip)接合中。由于成本低，晶片级芯片尺寸封装(WaferLevel Chip Scale Packaging；WLCSP)是目前广泛使用且相对简单的制程。在典型的WLCSP中，内连接结构形成在金属化层(Metallization Layers)上，接着形成凸块下金属(Under-Bump Metallurgy/Under-Bump Metallization；UBM)并设置焊球(Solder Balls)。
覆晶封装利用凸块来建立芯片的输入/输出(I/O)接合垫与封装基材之间，或与封装导线框(Lead Frame)之间的电性接触。就结构上来说，凸块实际上包含凸块本身以及位于凸块与I/O接合垫之间的所谓的UBM。UBM一般包含利用以下所述顺序配置在I/O接合垫上的粘合(Adhesion)层、阻障(Barrier)层以及润湿(Wetting)层。根据所使用的材料，凸块本身可区分为锡凸块、金凸块、铜(Copper/Cu)柱(Pillar)凸块以及混合金属(Mixed Metals)凸块。最近提出有铜内连线柱(Interconnect Post)技术。以铜柱组件取代原来所使用的锡凸块，来连接电子组件与一基材。上述铜内连线柱技术以最小的凸块桥接(Bridging)可能性来达到较细的节距(Pitch)，降低电路的电容负载，并允许电子组件以较高频率来执行。而锡合金仍然是必须的，其是用以覆盖(Capping)凸块结构以及接合电子组件。
WLCSP以及相关的覆晶封装中的物理应力是与多项因素(Factors)的结合有关，例如组件尺寸、架构(Architecture)、操作状况、以及实际的封装设计与建构材料。然而，低介电常数材料的使用产生了封装时施加于组件上的应力的关键问题。此外，在铜柱的介绍中包含了较锡凸块更高的应力，因此需要应力缓冲层或应力重新分配(Re-Distribution)层。聚亚酰胺(Polyimide；PI)可作为应力缓冲以降低金属凸块区底下的低介电系数层的最大应力，但相对的，其亦冲击组件的性能。例如，PI层需要高温与长时间的固化程序(Curing Process)，故导致大体积PI的收缩，进而对硅产生了大的残留(Residual)应力。常见的失效模式为沿着晶粒角落或PI层与底部填充(Underfill)材料间的界面的脱层(Delamination)或破裂(Cracking)。
发明内容
本发明的目的在提供一种半导体组件以及制造半导体组件的方法，半导体组件的接合垫结构中设有环状的应力缓冲层，通过此小面积的应力缓冲层来降低上述沿着晶粒角落或PI层与底部填充材料间的接口产生脱层或破裂的缺陷。
根据本发明的一方面，提供一种半导体组件。此半导体组件包含位于半导体基材之上的金属接合垫、位于上述金属接合垫之上的保护层、位于上述保护层及金属接合垫之上的环状层、位于上述环状层之上的UBM层以及位于上述UBM层之上的金属凸块。上述保护层暴露出金属接合垫的第一部分，而环状层则暴露出金属接合垫的第二部分，其中金属接合垫的第二部分是位于金属接合垫的第一部分之内。至于UBM层则电性连接至上述金属接合垫的第二部分。
根据本发明的另一方面，提供一种半导体组件。此半导体组件包含位于半导体基材之上的金属接合垫、位于上述金属接合垫之上的保护层、位于上述保护层之上的内连接线、位于上述内连接线之上的阻障层、位于上述阻障层之上的环状层、位于上述环状层之上的UBM层以及位于上述UBM层之上的金属凸块。上述保护层暴露出金属接合垫的一部分，而内连接线是电性连接至上述金属接合垫被暴露出的部分。此外，上述阻障层暴露出内连接线的一部分，而环状层电性连接至内连接线被暴露出的部分，且UBM层亦电性连接至内连接线被暴露出的部分。
根据本发明的再一方面，提供一种制造半导体组件的方法。此方法包含提供具有传导区的半导体基材；形成位于上述半导体基材之上的介电层；形成第一开口部于上述介电层中，借以暴露出传导区的一部分；形成位于上述介电层之上的环状层，其中环状层暴露出上述传导区被暴露出部分的至少一部分；形成UBM层，其中UBM层是位于上述环状层、介电层与传导区之上；形成具有第二开口部的遮罩层(mask layer)，其中遮罩层是位于UBM层之上；形成传导材料层于上述遮罩层的第二开口部中，且传导材料层电性连接至UBM层；以及移除上述的遮罩层。
本发明的优点为，通过在半导体组件的接合垫结构中设置小面积的环状应力缓冲层，可降低上述脱层或破裂的缺陷。因此，可提升半导体组件的合格率，增加产能，亦可改善半导体组件的可靠度。
附图说明
为了对本发明的实施例及其优点有更完整的理解，现请参照以上的说明并配合相应的附图。相关附图内容说明如下。
图1是绘示根据本发明的各种观点的制造半导体组件的方法的流程图；
图2至6是绘示根据图1的方法的一实施例的半导体组件的各个制造阶段的部分剖面示意图；
图7是绘示根据图1中方法的一实施例的晶片制造过程中的晶片的部分剖面示意图；
图8与9是绘示根据图1中方法的一实施例的晶片制造过程中各阶段的晶片的部分剖面示意图；
图10是绘示根据本发明的各种观点的制造半导体组件的方法的流程图，其中半导体组件具有PPI结构；
图11至14是绘示根据图10的方法的一实施例的晶片的各个制造阶段的部分剖面示意图。
【主要组件符号说明】
2：晶片                      4：晶片
10：半导体基材               12：微电子组件
14：内连接结构               16：第一保护层
18：金属接合垫               18A：主要部分
18B：部分                    18E：边缘部分
19：第一层                   19a：第一开口部
20：第二保护层               20a：开口部
21：第二层                   21a：第二开口部
22：接合垫结构               22A：接合垫结构
22B：接合垫结构              22C：接合垫结构
24：应力缓冲层               24a：内部开口部
24A：应力缓冲层              24B：应力缓冲层
24C：应力缓冲层              26：UBM层
28：遮罩层                   28a：开口部
30：铜层                     32：凸块结构
34：遮蔽层                   36：焊料层
40：薄铜层                   44：阻障层
46：焊料层                   46”：回焊焊料层
50：内连接线                 50A1：第一端
50A2：第二端                 52：阻障层
52a：开口部                  54：接合垫结构
56：UBM层                    58：焊球
100：制造半导体组件的方法    101：区块
102：区块                    103：区块
104：区块                    105：区块
200：制造半导体组件的方法    201：区块
202：区块                    203：区块
204：区块                    205：区块
D：距离                      I：凸块
II：凸块区
具体实施方式
本发明提供具有接合垫结构的半导体组件及形成此半导体组件的制程，其中接合垫结构设有应力缓冲层。上述半导体组件可具有铜柱、柱保护(Passivation)内连线、焊料凸块、及/或制造于其中的穿透硅介层窗(Through-Silicon Vias；TSVs)，其中半导体组件可应用于覆晶组装(Assembly)、WLCSP、三维集成电路(3D-IC)堆叠、及/或任何先进封装技术领域。以下将参照相应附图中的例示性实施例做详细的说明。只要有可能，使用在附图与说明中的相同参考号码是用以表示相同或类似的部分。在附图中，为了清楚与方便起见，形状与厚度可能被夸张化。本发明将特别地被导引至，形成符合本发明的装置的一部分的组件，或与符合本发明的装置更直接相关共同运作的组件。可理解的是，未特别绘示或描述的组件可采用熟悉此技艺者所熟知的各种型式。此外，当称一层是位于另一层之上，或位于一基材之上，其可表示此一层是直接位于另一层或基材之上，或亦可包含有中间层(Intervening Layer)。在整分说明书中，对应于一实施例的参照是表示，被描述成与此实施例相关的特定特征、结构或特性是至少包含在一实施例中。因此，在整分说明书中多处所使用的“在一实施例中”的用词，并不需要全部均指相同的实施例。再者，特定的特征、结构或特性可用任何适当的方式结合至一个或多个实施例中。可以明白的是，相应的附图并未依比例绘示，而其中这些附图仅是作为说明之用。
图1是绘示根据本发明的各种观点的制造半导体组件的方法100的流程图。请参照图1，方法100开始于区块101，以在半导体基材上形成金属接合垫。方法100继续进行至区块102，以在半导体基材上形成保护层。图案化保护层以形成开口，借以暴露出上述金属接合垫的主要部分。方法100继续进行至区块103，以在保护层上形成应力缓冲层。将应力缓冲层图案化成一环状(Ring-Shaped)层以具有一内部开口部，借以暴露出上述金属接合垫的主要部分的至少一部分。方法100继续进行至区块104，以在应力缓冲层上、保护层上以及金属接合垫被暴露出的部分上形成UBM层。方法100继续进行至区块105，在UBM层上形成金属凸块，使得金属凸块电性连接至金属接合垫。
图2至6是绘示根据图1的方法100的一个或多个实施例的半导体组件的各个制造阶段的部分剖面示意图。
请参照图2，其是绘示晶片2的剖面示意图。晶片2包含使用于半导体IC制造中的半导体基材10，且IC可形成在晶片2之中及/或之上。半导体基材10被定义成指包含有半导体材料的任何架构，其中半导体材料包含(但并不局限)块状硅(Bulk Silicon)、半导体晶片、绝缘层上覆硅(Silicon-On-Insulator；SOI)基材、或硅锗(Germanium)基材。其它半导体材料(包含三族、四族与五族元素)亦可加以使用。半导体基材10还可包含多个隔离特征(未绘示)，例如浅沟渠隔离(Shallow Trench Isolation；STI)特征或硅区域氧化(LOCOS)特征。隔离特征可定义并隔离各种微电子组件12。可形成在半导体基材10中的各种微电子组件12的例子包含晶体管[例如金属氧化物半导体场效应晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极接面晶体管(BJT)、高压晶体管、高频晶体管、p通道及/或n通道场效晶体管(PFETs/NFETs)等]、电阻、二极管(Diodes)、电容(Capacitors)、电感(Inductors)、保险丝(Fuses)或其它适当的组件。可执行各种制程以形成各种的微电子组件，其中包含沉积(Deposition)、蚀刻(Etching)、植入(Implantation)、微影(Photolithography/Lithography)、退火(Annealing)、或其它适当的制程。内连接上述的微电子组件12以形成IC组件，例如逻辑组件、内存组件[例如静态随机存取内存(SRAM)]、无线射频(RadioFrequency；RF)组件、I/O组件、系统整合芯片(System-On-Chip；SoC)组件、上述组件的组合、或其它适当型态的组件。在其它实施例中，晶片2是中介层(Interposer)晶片或封装基材的晶片，且实质未包含IC组件形成于其中，其中IC组件包含晶体管、电阻、电容、电感及/或类似的组件。在这些实施例中，半导体基材10可利用半导体材料、介电材料[例如氧化硅(Silicon Oxide)]或玻璃材料来形成。
图2亦绘示形成在半导体基材10之上的内连接结构14与第一保护层16。内连接结构14包含形成于其中的金属线与介层窗(未绘示)，且电性耦合至微电子组件12(亦称之为半导体组件12)。金属线与介层窗可用铜或铜合金来形成，且可使用镶嵌(Damascene)制程来形成。内连接结构14包含内层介电(Inter-Layer Dielectric；ILD)层与内金属介电(Inter-Metal Dielectric；IMD)层其中至少一者。在特定的实施例中，上述ILD层或IMD层包含氧化硅、氮化硅(Silicon Nitride)、氮氧化硅(Silicon Oxynitride)或低介电常数介电材料。形成在内连接结构14之上的第一保护层16为一介电材料层，其中上述的介电材料层可用低介电常数介电材料、未掺杂硅玻璃(Un-doped Silicate Glass；USG)、氮化硅、氮氧化硅、或其它常用材料来形成。低介电常数介电材料的介电常数(K值)可小于约3.9，或小于约2.8。
金属接合垫材料是沉积在第一保护层16之上，且接着图案化以在不同的凸块区I及II形成多个金属接合垫18。至少一金属接合垫18可电性连接至下层的内连接结构14。至少一金属接合垫18可电性耦合至半导体组件12(例如经由内连接结构14)。在特定的实施例中，金属接合垫18包含铝(Al)、铜、银(Silver/Ag)、金(Au)、镍(Nickel/Ni)、钨(Tungsten/W)、上述元素的合金、及/或上述元素的复合层。接着第二保护层20形成在晶片2之上，其中第二保护层20被图案化以包含分别暴露出下层的金属接合垫18的开口部20a。在凸块区I或II中，第二保护层20暴露出金属接合垫18的主要部分18A。在特定的实施例中，第二保护层20可覆盖金属接合垫18的边缘部分18E。第二保护层20是用高分子聚合物(Polymer)层[例如环氧树脂(Epoxy)、PI、苯环丁烯(Benzocyclobutene；BCB)、聚苯恶唑(Polybenzoxazole；PBO)或类似的物质]来形成，虽然亦可采用其它相对较软质(经常为有机的)的介电材料。在其它特定的实施例中，第二保护层20是用选自于USG、氮化硅、氮氧化硅、氧化硅或上述材料的组合的非有机材料来形成。
接着，缓冲材料沉积在晶片2上，且接着图案化以在凸块区I及II中形成多个应力缓冲层24。上述多个应力缓冲层24是彼此分离。在凸块区I或II中，应力缓冲层24覆盖部分的第二保护层20与金属接合垫18，并暴露出金属接合垫18的主要部分18A的部分18B。应力缓冲层24是具有内部开口部24a的环状体。在特定的实施例中，内部开口部24a是设置在开口部20a之内，且具有小于开口部20a的直径，因此，暴露出的部分18B小于金属接合垫18的主要部分18A。在特定的实施例中，内部开口部24a是沉积在开口部20a之内，且具有大于或等于开口部20a的直径，因此，暴露出的部分18B是实质等于主要部分18A。在一凸块区中，金属接合垫18与应力缓冲层24的结合作为接合垫结构22，借以电性连接外部终端(External Terminal)。
在至少某些特定的实施例中，缓冲材料的选择是以如材料的介电常数，或材料的拉伸(Tensile)强度(延长至破断)或杨氏系数(Young’s Modulus)为依据。在特定的实施例中，应力缓冲层24是用介电材料[如具有小于3.5的介电常数的低介电常数介电材料、USG或氟化硅酸盐玻璃(Fluorinated Silica Glass；FSG)]来形成。在特定的实施例中，应力缓冲层24是用高分子聚合物材料(例如PI、BCB、PBO或环氧树脂)来形成。特定的实施例中，应力缓冲层是用金属层(例如铝或铜)来形成。
如图2所绘示的实施例的俯视图是描绘于图3A至3C中。多个应力缓冲层24可如所见配置在第二保护层20上。在以上所述的实施例中，应力缓冲层24为环状层，其中环状层是彼此分离，并分别位于凸块区中。应力缓冲层24可为任何几何形状的环状层。在特定的实施例(如图3A所示的实施例)中，接合垫结构22A包含形成圆形环的应力缓冲层24A。在特定的实施例(如图3B所示的实施例)中，接合垫结构22B包含形成方形环的应力缓冲层24B。在特定的实施例(如图3C所示的实施例)中，接合垫结构22C包含形成八边形(Octagonal)环的应力缓冲层24C。其它未描述或绘示于此的实施例可具有其它形状，例如椭圆形(Ovals)、其它正多边形(Regular Polygons)或非正(Irregular)多边形。在更进一步的实施例中，在相同晶片上组合多种形状是可能的，例如一晶片上包含圆形(Circular)、方形以及多边形的环状应力缓冲层。环状应力缓冲层24可从第二保护层20的边缘延伸仅几微米(Microns；μm)。在特定的实施例中，应力缓冲层24具有介于约2μm至10μm的厚度。
接着，请参照图4，UBM层26形成在晶片2之上，以覆盖第二保护层20、应力缓冲层24以及金属接合垫18被暴露的部分18B。在特定的实施例中，UBM层26包含扩散阻障(Diffusion Barrier)层或粘着(Glue)层，其中扩散阻障层与粘着层是通过物理气相沉积(Physical Vapor Deposition；PVD)或溅镀(Sputtering)沉积钛(Titanium)、钽(Tantalum)、氮化钛(Titanium Nitride)、氮化钽(Tantalum Nitride)或类似的材料来形成，且其厚度是介于约500至2000埃(Angstrom；)。在特定的实施例中，UBM层26包含形成于扩散阻障层上的晶种层(Seed Layer)，其中晶种层是通过PVD或溅镀沉积至介于约500至10000的厚度。上述晶种层可用铜或铜合金来形成，其中铜合金包含银、铬(Chromium)、镍、锡(Tin/Sn)、金或上述元素的组合。
接着如图5所示，形成遮罩层28于UBM层26上。图案化遮罩层28以形成开口部28a于其中，以便暴露出位于不同凸块区的UBM层26的一部分。遮罩层28可为干膜(Dry Film)或光阻(Photoresist)膜，其中遮罩层28可通过微影及/或蚀刻制程。图5亦绘示有位于开口部28a中且具有焊料可湿性(SolderWettability)的传导(Conductive)材料的形成。在一实施例中，多个铜层30是分别形成于多个开口部28a中以接触下层的UBM层26。在本发明的所有内容中，“铜层”的用词是欲实质包含具有纯元素铜、包含不可避免杂质的铜、或包含份量较少的元素的铜合金的层，其中上述份量较少的元素可如钽、铟(Indium/In)、锡、锌(Zinc)、锰(Manganese)、铬、镍、锗、锶(Strontium)、铂(Platinum)、镁(Magnesium)、铝或锆(Zirconium)。形成的方法可包含溅镀、印制(Printing)、电镀(Electro Plating)、或化学气相沉积法(Chemical VaporDeposition；CVD)。例如，执行电化学电镀(Electro-Chemical Plating；ECP)以形成铜层30。在一实施例中，铜层30的厚度是大于25μm。在另一实施例中，铜层30的厚度是大于40μm。例如，铜层30约为40至50μm厚，或约40至70μm厚，虽然上述的厚度可更大或更小。
在此之后，如图6所示，从UBM层26移除遮罩层28，因此暴露出铜层30的侧壁表面。在以下的说明书中，从UBM层26凸出的铜层30被称之为铜柱30。处理程序进行至使用铜柱30作为遮罩以蚀刻UBM层26暴露出来的部分，因此暴露出铜柱30之外的第二保护层20及应力缓冲层24。
上述步骤在晶片2上的不同凸块区I及II中完成多个凸块结构32。在凸块区I或II中，凸块结构32包含铜柱30、由铜柱30覆盖的UBM层26、以及位于UBM层26底下的接合垫结构22。接合垫结构22包含金属接合垫18与环状的应力缓冲层24，且第二保护层20是形成于上述二者之间。第二保护层20覆盖金属接合垫18的边缘部分18E，并暴露出金属接合垫18的主要部分18A。形成于第二保护层20上的环状应力缓冲层24暴露出主要部分18A的部分18B。因此，形成在金属接合垫18之上的UBM层26可接触金属接合垫18被暴露出的部分18B。环状应力缓冲层24从UBM层26的边缘延伸一距离D。在特定的实施例中，距离D是约5μm至15μm。在其它的实施例中，从金属接合垫18的外侧边缘开始测量，环状应力缓冲层24可延伸约5μm至15μm。接着锯开(Saw)晶片2，并以焊球或铜凸块将其封装至一封装基材或另一晶粒上，其中上述的焊球或铜凸块是装设在上述封装基材或另一晶粒的接合垫上。
本发明所揭露的接合垫结构22，其中环状的应力缓冲层24是位于金属接合垫18之上。环状的应力缓冲层24是分别设置在凸块区中，其中环状的应力缓冲层24是彼此分离。比较使用PI层且在晶片上具有大覆盖面积的方法，环状的应力缓冲层24具有较小的尺寸，且从UBM层26延伸一较小的距离，此方法可透过凸块降低大的残留应力并缓解(Relieve)外部应力负荷，其中上述残留应力与应力负荷是由热的不匹配(Thermal Mismatch)或温度循环所引起。当与锡/铅(Lead)焊料凸块相比较时，虽然铜柱施加(Place)了额外的应力于硅芯片上，但是借着区域化环状应力缓冲层于凸块区之上，较厚的应力缓冲层可用来避免相对应的压缩(Compressive)负载或拉伸负载非必要性地施加在硅基材上。
图7是绘示根据图1所示方法的一实施例的晶片制造过程中的晶片一部分的剖面示意图。与图2至6的描述相同或相似部分的说明将加以省略。在图7中绘示有形成于铜柱30的顶表面上的遮蔽(Cap)层34以及形成于遮蔽层34上的焊料层36。遮蔽层34与焊料层36是在移除遮罩层28之前依次地沉积于铜层30之上，并在UBM的蚀刻制程后仍维持在铜柱30之上。遮蔽层34是作为阻障层以避免铜柱30中的铜扩散至接合材料(例如焊料合金)中，其中接合材料是用来接合半导体基材10至外部特征。铜扩散的避免增加封装的可靠度以及接合强度。遮蔽层34可包含镍、锡、锡铅(Tin-Lead/SnPb)、金、银、钯(Palladium/Pd)、铟、镍钯金(NiPdAu)、镍金(NiAu)、其它类似材料、或以电镀方式沉积的合金。遮蔽层34具有约1μm至10μm的厚度。在特定的实施例中，遮蔽层34是用镍、金、钯、镍基(Ni-Based)合金、金基合金、钯基合金或上述材料的组合来形成。在特定的实施例中，焊料层36是用锡、锡银(SnAg)、锡铅、锡银铜(SnAgCu)[其中铜的重量百分比(wt％)小于0.3％]、锡银锌(SnAgZn)、锡锌(SnZn)、锡铋铟(SnBiIn)、锡铟(SnIn)、锡金(SnAu)、锡铜(SnCu)、锡锌铟(SnZnIn)或锡银锑(SnAgSb)等，以及电镀制程来形成。在一实施例中，焊料层36为无铅(Lead-Free)焊料层。在无铅焊料系统中，焊料层为锡银，其中银含量是控制在小于3.0wt％。例如，无铅焊料层为锡银，且银含量控制在约2.5wt％。可执行回焊(Reflowing)制程于焊料层36，借以形成焊球于遮蔽层34之上。
在额外的其它实施例中，环状应力缓冲层24是使用于焊料凸块中，而不是使用于铜柱凸块中。图8与9是绘示根据图1中方法100的一实施例的半导体组件制造过程中各阶段的半导体组件的部分剖面示意图。与图2至6的描述相同或相似部分的说明将加以省略。
比较描绘于图5中的制程，铜柱的形成是由焊料凸块制程中的薄铜层所取代，且紧接在焊料凸块制程之后形成阻障层与焊料层。请参照图8，在形成遮罩层28于UBM层26之上后，薄铜层40沉积在UBM层26之上的开口部28a中。薄铜层40具有相对于铜柱30较薄的厚度。在特定的实施例中，薄铜层40具有小于10μm的厚度。在特定的实施例中，薄铜层40具有约为4μm至6μm的厚度，虽然薄铜层40的厚度可以更厚或更薄。薄铜层40形成方法可包含溅镀、印制、电镀、无电电镀(Electroless Plating)、与CVD等方法。
阻障层44(选择性的层)接着形成于薄铜层40之上的开口部28a中。阻障层44是用铜、镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金、其它类似材料、或合金以及电镀方法来形成。阻障层44具有小于10μm的厚度。在特定的实施例中，阻障层44有小于5μm的厚度。接着，焊料层46形成于阻障层44之上的开口部28a中。在一实施例中，焊料层46为无铅焊料层。在特定的实施例中，焊料层46是用锡、锡银、锡铅、锡银铜[其中铜的重量百分比小于0.3％]、锡银锌、锡锌、锡铋铟、锡铟、锡金、锡铜、锡锌铟或锡银锑等，以及电镀制程来形成。在移除遮罩层28之后(接着执行UBM的蚀刻制程)。对焊料层46执行回焊以形成焊球。因此，回焊焊料层46”、阻障层44以及薄铜层40被称之为焊料凸块结构。
在额外的其它实施例中，环状应力缓冲层24是使用于焊料凸块中，其中焊料凸块是位于后护层内连接(Post-Passivation Interconnect；PPI)结构之上。图10是绘示根据本发明的各种观点的制造半导体组件的方法200的流程图。请参照图10，方法200开始于区块201，借以形成PPI结构于半导体基材之上。方法200继续进行至区块202，以在PPI结构之上形成阻障层。图案化阻障层以形成开口，借以暴露出上述PPI结构的一部分。方法200继续进行至区块203，以在阻障层上形成应力缓冲层。将应力缓冲层图案化成一环状层以具有一内部开口部，借以暴露出上述PPI结构被暴露出的部分的至少一部分。方法200继续进行至区块204，以在应力缓冲层上以及PPI结构被暴露出的部分上形成UBM层。方法200继续进行至区块205，在UBM层上形成金属凸块，使得金属凸块电性连接至PPI结构。
图11至14是绘示根据图10的方法200的一实施例的半导体组件的各个制造阶段的部分剖面示意图。与图2至6的描述相同或相似部分的说明将加以省略。
比较描绘于图2中的制程，提供PPI结构于第二保护层之上，接着形成环状应力缓冲层。请参照图11，第二保护层20是形成在晶片4之上，借此暴露出位于不同凸块区I及II的金属接合垫18。在特定的实施例中，第二保护层20包含第一层19与第二层21。在凸块区I或II中，第一层19是形成在第一保护层16之上，并加以图案化以形成第一开口部19a，而暴露出金属接合垫18的主要部分18A(亦可称之为第一部分18A)。第二层21是形成在第一层19之上，并加以图案化以形成第二开口部21a，借以暴露出金属接合垫18的部分18B(亦可称之为第二部分18B)。第二部分18B是形成在第一部分18A之内。在特定的实施例中，第一层19与第二层21是用非有机材料来形成，其中非有机材料是选自于未掺杂硅玻璃、氮化硅、氮氧化硅、氧化硅或上述材料的组合。在特定的实施例中，第一层19与第二层21是用高分子聚合物层来形成，例如环氧树脂、PI、BCB、PBO及类似的物质。第一层19与第二层21可用相同或不同的材料来形成。
接着，传导材料层沉积在晶片4之上，覆盖住第二保护层20，并与金属接合垫18被暴露出的第二部分18B接触。接着图案化传导材料层以形成配置在凸块区I与II之中的内连接线50。在凸块区I或II中，内连接线50(亦称之为PPI线50)包含电性连接至金属接合垫18的第一端50A1、电性连接至UBM层的第二端50A2、以及形成于后续制程中的金属凸块。PPI线50包含(但未限制)如铜、铝、铜合金或其它具有可移动载子的传导材料。在特定的实施例中，PPI线50还可在含铜层的顶部包含一含镍层(未绘示)。PPI的形成方法包含电镀、无电电镀、溅镀、CVD方法以及类似的方法。PPI线50在功能上亦可作为电力线(Power Lines)、重新分配线(Re-Distribution Lines；RDL)、电感、电容、或任何被动(Passive)组件。PPI线50可具有小于约30μm的厚度，例如介于约2μm至约25μm。
请参照图12，阻障层52接着形成在晶片4之上，借以覆盖PPI线50以及第二保护层20被暴露出的部分。使用微影以及蚀刻制程来进一步图案化阻障层52，借此分别形成暴露出PPI线50的第二端50A2的开口部52a。在特定的实施例中，阻障层52是用选自于USG、氮化硅、氮氧化硅、氧化硅与上述材料的组合的非有机材料来形成。在特定的实施例中，阻障层52是用高分子聚合物层(例如环氧树脂、PI、BCB、PBO与类似的物质)来形成，虽然亦可采用其它相对较软质(经常为有机的)的介电材料。
接着，如图13所示，多个环状应力缓冲层24形成于凸块区I与II中的阻障层52之上。应力缓冲层24是彼此分离。在凸块区I或II中，应力缓冲层24覆盖阻障层52的一部分，且至少暴露出PPI线50的第二端50A2的一部分。应力缓冲层24的内部开口部24a可小于、大于或等于阻障层52的开口部52a。在一凸块区中，PPI线50的第二端50A2与应力缓冲层24的结合是作为电性连接外部终端的接合垫结构54。应力缓冲层24可为任何几何形状的环状层。在特定的实施例中，应力缓冲层24是形成圆形环。在特定的实施例中，应力缓冲层24是形成方形环。在特定的实施例中，应力缓冲层24是形成八边形环。在更进一步的实施例中，在相同晶片上组合多种形状是可能的，例如一晶片上包含圆形、方形以及多边形的环状应力缓冲层。环状应力缓冲层24可从阻障层52的边缘延伸几μm或数十μm。
以下，请参照图14，UBM层56与焊球58是形成在凸块区中环状应力缓冲层24以及PPI线50被暴露出的部分之上，其中凸块区使用了包含UBM沉积、遮罩制程、薄铜层沉积、焊料层沉积、遮罩剥除(Stripping)制程、UBM蚀刻制程以及焊料回焊制程的凸块形成方法。在其它的实施例中，使用在PPI线50之上是铜柱凸块，而不是焊料凸块中。接着锯开晶片4，并以焊球或铜凸块将其封装至一封装基材或另一晶粒上，其中上述的焊球或铜凸块是装设在上述封装基材或另一晶粒的接合垫上。
在前述的详细描述中，本发明是参照特定的例示性实施例来加以描述。然而，很显然的，在不脱离本发明的广义的精神和范围内，当可做各种修改、结构、程序、与改变。因此，本说明书与附图是被视为说明之用，而并非用以限制本发明的范围。可以理解的是，本发明的实施例可使用各种其它的结合与环境，且在如以上所述的本发明的范围内可做改变或修改。

Claims (5)

1.一种半导体组件，其特征在于，包含：
一金属接合垫，位于一半导体基材之上；
一保护层，位于该金属接合垫之上，且该保护层暴露出该金属接合垫的一第一部分；
一环状层，位于该保护层及该金属接合垫之上，其中该环状层暴露出该金属接合垫的一第二部分，该金属接合垫的该第二部分是位于该金属接合垫的该第一部分之内，且该环状层覆盖部分的该保护层；
一凸块下金属层，位于该环状层之上，且该凸块下金属层电性连接至该金属接合垫的该第二部分；以及
一金属凸块，位于该凸块下金属层之上，其中该金属凸块包含一铜柱、位于该铜柱之上的一遮蔽层、以及位于该遮蔽层之上的一焊料层，该遮蔽层包含镍，且该焊料层包含一无铅焊料层，其中该遮蔽层是作为阻障层以避免铜柱中的铜扩散至该焊料层中，该环状层从该凸块下金属层的边缘延伸一距离，该距离约5微米至15微米，且该环状层为一圆形环、一方形环或一八边形环。
2.根据权利要求1所述的半导体组件，其特征在于，该环状层包含高分子聚合物层、一介电层、或至少一铝层与一铜层，其中该介电层具有小于3.5的介电常数。
3.一种半导体组件，其特征在于，包含：
一金属接合垫，位于一半导体基材之上；
一保护层，位于该金属接合垫之上，且该保护层暴露出该金属接合垫的一部分；
一内连接线，位于该保护层之上，且该内连接线电性连接至该金属接合垫被暴露出的该部分；
一阻障层，位于该内连接线之上，且该阻障层暴露出该内连接线的一部分；
一环状层，位于该阻障层之上，且该环状层电性连接至该内连接线被暴露出的该部分；
一凸块下金属层，位于该环状层之上，且该凸块下金属层电性连接至该内连接线被暴露出的该部分；以及
一金属凸块，位于该凸块下金属层之上，其中该金属凸块包含一铜柱、位于该铜柱之上的一遮蔽层、以及位于该遮蔽层之上的一焊料层，其中该遮蔽层是作为阻障层以避免铜柱中的铜扩散至该焊料层中，该环状层从该凸块下金属层的边缘延伸一距离，该距离约5微米至15微米，且该环状层为一圆形环、一方形环或一八边形环。
4.根据权利要求3所述的半导体组件，其特征在于，该环状层包含高分子聚合物层、一介电层、或至少一铝层与一铜层，其中该介电层具有小于3.5的介电常数。
5.一种制造半导体组件的方法，其特征在于，包含：
提供一半导体基材，其中该半导体基材具有一传导区；
形成一介电层，其中该介电层是位于该半导体基材之上；
形成一第一开口部于该介电层中，以暴露出该传导区的一部分；
形成一环状层，其中该环状层是位于该介电层之上，该环状层暴露出该传导区被暴露出的该部分的至少一部分，且该环状层覆盖部分的该介电层；
形成一凸块下金属层，其中该凸块下金属层是位于该环状层、该介电层与该传导区之上；
形成一遮罩层，其中该遮罩层具有一第二开口部，且位于该凸块下金属层之上；
形成一传导材料层于该遮罩层的该第二开口部中，且其中该传导材料层电性连接至该凸块下金属层；
移除该遮罩层，其中该环状层从该凸块下金属层的边缘延伸一距离，该距离约5微米至15微米，且该环状层为一圆形环、一方形环或一八边形环；以及
使用该传导材料层为遮罩，蚀刻该凸块下金属层，以暴露出该传导材料层之外的该介电层及该环状层，其中该传导材料层包含一铜柱、位于该铜柱之上的一遮蔽层、以及位于该遮蔽层之上的一焊料层，其中该遮蔽层是作为阻障层以避免铜柱中的铜扩散至该焊料层中。
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