TWI488273B - 半導體製程及其半導體結構 - Google Patents

半導體製程及其半導體結構 Download PDF

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Publication number
TWI488273B
TWI488273B TW101125709A TW101125709A TWI488273B TW I488273 B TWI488273 B TW I488273B TW 101125709 A TW101125709 A TW 101125709A TW 101125709 A TW101125709 A TW 101125709A TW I488273 B TWI488273 B TW I488273B
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Taiwan
Prior art keywords
layer
core
joint
portions
bonding
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TW101125709A
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English (en)
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TW201405743A (zh
Inventor
Chih Ming Kuo
Lung Hua Ho
Shih Chieh Chang
Chia Yeh Huang
Chin Tang Hsieh
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Chipbond Technology Corp
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Priority to TW101125709A priority Critical patent/TWI488273B/zh
Priority to US13/644,749 priority patent/US8823169B2/en
Priority to US14/164,628 priority patent/US9059260B2/en
Publication of TW201405743A publication Critical patent/TW201405743A/zh
Application granted granted Critical
Publication of TWI488273B publication Critical patent/TWI488273B/zh

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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Description

半導體製程及其半導體結構
本發明係有關於一種半導體製程，特別係有關於一種可提高封裝可靠度之半導體製程。
如第6圖所示，習知半導體封裝結構200係包含有一基板210、一晶片220及複數個銲料230，該基板210係具有複數個連接墊211、該晶片220係具有複數個凸塊221，該些銲料230係點塗於該些凸塊221上並壓合該基板210及該晶片220以藉由該些銲料230電性連接該些凸塊221及該些連接墊211，但由於電子產品體積越來越小，因此該些凸塊221間距及連接墊211間距相對也越來越小，於此情形下，該些銲料230在回焊時容易溢流至鄰近凸塊或鄰近連接墊而產生短路之情形，導致產品良率不佳。
本發明之主要目的係在於提供一種半導體製程，其包含提供一載體，該載體係具有一表面及一形成於該表面之金屬層，該金屬層係具有複數個第一區及複數個位於第一區外側之第二區；形成一第一光阻層於該金屬層，該第一光阻層係具有複數個第一開口；形成複數個芯部於該些第一開口；移除該第一光阻層以顯露出該些芯部，各該芯部係具有一頂面；形成一第二光阻層於該金屬層，該第二光阻層係具有複數個第二開口且該些第二開口係顯露該些芯部之該些頂面；形成複數個接合部於 該些第二開口，各該接合部係包含有一第一接合層及一第二接合層，各該第一接合層係形成於各該芯部之該頂面及該金屬層，使各該接合部連接各該芯部以形成一混成凸塊，其中各該第一接合層具有一基底部、一凸出部及一容置空間，各該基底部係具有一上表面，各該凸出部係凸出於該表面，且各該凸出部係位於各該芯部上方，各該容置空間係位於各該凸出部外側，該些第二接合層係覆蓋該些凸出部及該些表面且填充於該些容置空間；移除該第二光阻層以顯露出該些混成凸塊；以及移除該金屬層之該些第二區，以使該金屬層之該些第一區形成複數個凸塊下金屬層。由於該些第一接合層係具有該些容置空間，因此該半導體結構之該些第二接合層會填充於該些容置空間，可防止該些第二接合層溢流至鄰近混成凸塊而導致短路之情形。
請參閱第1及2A至2I圖，其係本發明之第一實施例，一種半導體製程係包含下列步驟：首先，請參閱第1圖之步驟10及2A圖，提供一載體110，該載體110係具有一表面111及一形成於該表面111之金屬層M，該金屬層M係具有複數個第一區M1及複數個位於第一區M1外側之第二區M2；接著，請參閱第1圖之步驟11及2B圖，形成一第一光阻層P1於該金屬層M，該第一光阻層P1係具有複數個第一開口O1；之後，請參閱第1圖之步驟12及2C圖，形成複數個芯部121於該些第一開口O1；接著，請參閱第1圖之步驟13及2D圖，移除該第一光阻層P1以顯露出該些芯部121，各該芯部121係具有一頂面121a；之後，請參閱第 1圖之步驟14及2E圖，形成一第二光阻層P2於該金屬層M，該第二光阻層P2係具有複數個第二開口O2且該些第二開口O2係顯露該些芯部121之該些頂面121a；接著，請參閱第1圖之步驟15及2F圖，形成複數個接合部122於該些第二開口O2，各該接合部122係包含有一第一接合層122a及一第二接合層122b，各該第一接合層122a係形成於各該芯部121之該頂面121a及該金屬層M，使各該接合部122連接各該芯部121以形成一混成凸塊120，其中各該第一接合層122a具有一基底部122c、一凸出部122d及一容置空間122e，各該基底部122c係具有一上表面122f，各該凸出部122d係凸出於該上表面122f，且各該凸出部122d係位於各該芯部121上方，各該容置空間122e係位於各該凸出部122d外側，該些第二接合層122b係覆蓋該些凸出部122d及該些上表面122f且填充於該些容置空間122e，在本實施例中，各該基底部122c係具有一第一高度H1，各該第二接合層122b係具有一第二高度H2，各該第一高度H1係不小於各該第二高度H2，且該些第一接合層122a之材質係選自於銅或金，該些第二接合層122b之材質係為銲料。
之後，請參閱第1圖之步驟16及2G圖，移除該第二光阻層P2以顯露出該些混成凸塊120；接著，請參閱第1圖之步驟17及2H圖，移除該金屬層M之該些第二區M2，以使該金屬層M之該些第一區M1形成複數個凸塊下金屬層112，該些凸塊下金屬層112之材質係選自於鈦/銅或鈦鎢/銅。最後，請參閱第1圖之步驟18及2I圖，回焊該些第二接合層122b，使該些第二接合層122b形成有一弧狀表面S 並覆蓋該些凸出部122d及該些上表面122f且填充於該些容置空間122e，並形成一半導體結構100，由於該些混成凸塊120之該些接合部122具有該些第一接合層122a及該些第二接合層122b，且該些第一接合層122a係具有該些基底部122c、該些形成於該些芯部121上方之凸出部122d及該些容置空間122e，因此當該半導體結構100熱壓合至一基板(圖未繪出)時，該些第二接合層122b會受壓往外側移動並填充於該些容置空間122e，因此可防止該些第二接合層122b溢流至鄰近混成凸塊120而導致短路之情形發生。
接著，請參閱第2I及3圖，其係本發明之第一實施例之一種半導體結構100，其至少包含有一載體110以及複數個混成凸塊120，該載體110係具有一表面111及複數個形成於該表面111之凸塊下金屬層112，該些凸塊下金屬層112之材質係選自於鈦/銅或鈦鎢/銅，該些混成凸塊120係形成於該些凸塊下金屬層112上，各該混成凸塊120係具有一芯部121及一接合部122，該芯部121係具有一頂面121a，該接合部122係包含有一第一接合層122a及一第二接合層122b，該些第一接合層122a之材質係選自於銅或金，該些第二接合層122b之材質係為銲料，該第一接合層122a係形成於該芯部121之該頂面121a及該凸塊下金屬層112，其中該第一接合層122a具有一基底部122c、一凸出部122d及一容置空間122e，該基底部122c係具有一上表面122f及一第一高度H1，該凸出部122d係凸出於該上表面122f，且該凸出部122d係位於該芯部121上方，該容置空間122e係位於該凸出部122d外 側，該第二接合層122b係覆蓋該凸出部122d及該上表面122f且填充於該容置空間122e，該第二接合層122b係具有一第二高度H2，各該第一高度H1係不小於各該第二高度H2。
或者，請參閱第4圖，其係本發明之第二實施例，一種半導體結構100，其至少包含有一載體110以及複數個混成凸塊120，該載體110係具有一表面111及複數個形成於該表面111之凸塊下金屬層112，該些混成凸塊120係形成於該些凸塊下金屬層112上，各該混成凸塊120係具有一芯部121及一接合部122，其中該第一實施例與該第二實施例不同之處在於該第二實施例之各該芯部121係具有一第一芯層121b及一第二芯層121c，且各該第二芯層121c係位於各該第一芯層121b與各該第一接合層122a之間，該第一芯層121b係具有一第一厚度T1，該第二芯層121c係具有一第二厚度T2，該第一厚度T1係大於該第二厚度T2，該第一芯層121b之材質係為銅，該第二芯層121c之材質係為鎳，當該些第一接合層122a之材質選自於金，而該些芯部121之該些第一芯層121b係為銅時，由於該芯部121之該第二芯層121c係為鎳，因此可增加該些第一接合層122a及該些第一芯層121b之結合強度。
較佳地，請參閱第5圖，其係本發明之第三實施例，一種半導體結構100，其至少包含有一載體110以及複數個混成凸塊120，該載體110係具有一表面111及複數個形成於該表面111之凸塊下金屬層112，該些混成凸塊120係形成於該些凸塊下金屬層112上，各該混成凸塊120係具有一芯部121及一接合部122，該芯部121係具有 一頂面121a，該接合部122係包含有一第一接合層122a及一第二接合層122b，該第一接合層122a係形成於該芯部121之該頂面121a及該凸塊下金屬層112，其中該第一接合層122a具有一基底部122c、一凸出部122d及一容置空間122e，在本實施例中，該第三實施例與該第一實施例不同之處在於該第三實施例之該基底部122c係具有一側壁122g，在回焊該些第二接合層122b之步驟中，該些第二接合層122b係亦覆蓋該些側壁122g，使得該半導體結構100與一基板(圖未繪出)進行封裝時該半導體結構100之該些混成凸塊120不容易與該基板剝離。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
10‧‧‧提供一載體，該載體係具有一表面及一形成於該表面之金屬層
11‧‧‧形成一第一光阻層
12‧‧‧形成複數個芯部
13‧‧‧移除該第一光阻層
14‧‧‧形成一第二光阻層
15‧‧‧形成複數個接合部，各該接合部係包含有一第一接合層及一第二接合層
16‧‧‧移除該第二光阻層
17‧‧‧移除該金屬層
18‧‧‧回焊該些第二接合層
100‧‧‧半導體結構
110‧‧‧載體
111‧‧‧表面
112‧‧‧凸塊下金屬層
120‧‧‧混成凸塊
121‧‧‧芯部
121a‧‧‧頂面
121b‧‧‧第一芯層
121c‧‧‧第二芯層
122‧‧‧接合部
122a‧‧‧第一接合層
122b‧‧‧第二接合層
122c‧‧‧基底部
122d‧‧‧凸出部
122e‧‧‧容置空間
122f‧‧‧表面
122g‧‧‧側壁
200‧‧‧半導體封裝結構
210‧‧‧基板
211‧‧‧連接墊
220‧‧‧晶片
221‧‧‧凸塊
230‧‧‧銲料
H1‧‧‧第一高度
H2‧‧‧第二高度
M‧‧‧金屬層
M1‧‧‧第一區
M2‧‧‧第二區
O1‧‧‧第一開口
O2‧‧‧第二開口
P1‧‧‧第一光阻層
P2‧‧‧第二光阻層
S‧‧‧弧狀表面
T1‧‧‧第一厚度
T2‧‧‧第二厚度
第1圖：依據本發明之第一實施例，一種半導體製程之流程圖。
第2A至2I圖：依據本發明之第一實施例，該半導體製程之截面示意圖。
第3圖：依據本發明之第一實施例，該半導體結構之立體圖。
第4圖：依據本發明之第二實施例，一種半導體結構之截面示意圖。
第5圖：依據本發明之第三實施例，一種半導體結構之截面示意圖。
第6圖：習知半導體封裝結構之示意圖。
100‧‧‧半導體結構
110‧‧‧載體
111‧‧‧表面
112‧‧‧凸塊下金屬層
120‧‧‧混成凸塊
122a‧‧‧第一接合層
122b‧‧‧第二接合層
122c‧‧‧基底部
122d‧‧‧凸出部
122e‧‧‧容置空間

Claims (16)

  1. 一種半導體製程，其至少包含下列步驟：提供一載體，該載體係具有一表面及一形成於該表面之金屬層，該金屬層係具有複數個第一區及複數個位於第一區外側之第二區；形成一第一光阻層於該金屬層，該第一光阻層係具有複數個第一開口；形成複數個芯部於該些第一開口；移除該第一光阻層以顯露出該些芯部，各該芯部係具有一頂面；形成一第二光阻層於該金屬層，該第二光阻層係具有複數個第二開口且該些第二開口係顯露該些芯部之該些頂面；形成複數個接合部於該些第二開口，各該接合部係包含有一第一接合層及一第二接合層，各該第一接合層係形成於各該芯部之該頂面及該金屬層，使各該接合部連接各該芯部以形成一混成凸塊，其中各該第一接合層具有一基底部、一凸出部及一容置空間，各該基底部係具有一上表面，各該凸出部係凸出於該上表面，且各該凸出部係位於各該芯部上方，各該容置空間係位於各該凸出部外側，該些第二接合層係覆蓋該些凸出部及該些上表面且填充於該些容置空間；移除該第二光阻層以顯露出該些混成凸塊；以及移除該金屬層之該些第二區，以使該金屬層之該些第一區形成複數個凸塊下金屬層。
  2. 如申請專利範圍第1項所述之半導體製程，其另包含有一回焊該些第二接合層之步驟，且各該基底部係具有一側壁，該些第二接合層係覆蓋該些側壁。
  3. 如申請專利範圍第1項所述之半導體製程，其中各該芯部係具有一第一芯層及一第二芯層，該第一芯層係具有一第一厚度，該第二芯層係具有一第二厚度，該第一厚度係大於該第二厚度。
  4. 如申請專利範圍第1項所述之半導體製程，其中各該基底部係具有一第一高度，各該第二接合層係具有一第二高度，各該第一高度係不小於各該第二高度。
  5. 如申請專利範圍第1項所述之半導體製程，其中該些凸塊下金屬層之材質係選自於鈦/銅或鈦鎢/銅。
  6. 如申請專利範圍第3項所述之半導體製程，其中該第一芯層之材質係為銅，該第二芯層之材質係為鎳。
  7. 如申請專利範圍第1項所述之半導體製程，其中該些第一接合層之材質係選自於銅或金。
  8. 如申請專利範圍第1項所述之半導體製程，其中該些第二接合層之材質係為銲料。
  9. 一種半導體結構，其至少包含：一載體，其係具有一表面及複數個形成於該表面之凸塊下金屬層；以及複數個混成凸塊，其係形成於該些凸塊下金屬層上，各該混成凸塊係具有一芯部及一接合部，該芯部係具有一頂面，該接合部係包含有一第一接合層及一第二接合層，該第一接合層係形成於該芯部之該頂面及該凸塊下金屬層，其中該第一接合層具有一基底部、一凸出部及一容置空間 ，該基底部係具有一上表面，該凸出部係凸出於該上表面，且該凸出部係位於該芯部上方，該容置空間係位於該凸出部外側，該第二接合層係覆蓋該凸出部及該上表面且填充於該容置空間。
  10. 如申請專利範圍第9項所述之半導體結構，其中各該基底部係具有一側壁，該些第二接合層係覆蓋該些側壁。
  11. 如申請專利範圍第9項所述之半導體結構，其中各該芯部係具有一第一芯層及一第二芯層，該第一芯層係具有一第一厚度，該第二芯層係具有一第二厚度，該第一厚度係大於該第二厚度。
  12. 如申請專利範圍第9項所述之半導體結構，其中各該基底部係具有一第一高度，各該第二接合層係具有一第二高度，各該第一高度係不小於各該第二高度。
  13. 如申請專利範圍第9項所述之半導體結構，其中該些凸塊下金屬層之材質係選自於鈦/銅或鈦鎢/銅。
  14. 如申請專利範圍第11項所述之半導體結構，其中該第一芯層之材質係為銅，該第二芯層之材質係為鎳。
  15. 如申請專利範圍第9項所述之半導體結構，其中該些第一接合層之材質係選自於銅或金。
  16. 如申請專利範圍第9項所述之半導體結構，其中該些第二接合層之材質係為銲料。
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