JP6161380B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6161380B2 JP6161380B2 JP2013086899A JP2013086899A JP6161380B2 JP 6161380 B2 JP6161380 B2 JP 6161380B2 JP 2013086899 A JP2013086899 A JP 2013086899A JP 2013086899 A JP2013086899 A JP 2013086899A JP 6161380 B2 JP6161380 B2 JP 6161380B2
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- resin layer
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- wiring
- semiconductor device
- wiring board
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Description
<半導体装置>
図1は実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示すA−A線に沿って切断した構造の一例を示す断面図、図3は図1に示す半導体装置の裏面側の構造の一例を示す裏面図である。
図4は図1に示す半導体装置に組み込まれる配線基板の上面側の構造の一例を示す平面図、図5は図4に示すA−A線に沿って切断した構造の一例を示す断面図、図6は図5に示すB部の構造の一例を示す拡大部分断面図、図7は図4に示す配線基板の下面側の構造の一例を示す裏面図である。
図8は図1に示す半導体装置に搭載される半導体チップの主面側の構造の一例を示す平面図、図9は図8に示すA−A線に沿って切断した構造の一例を示す断面図、図10は図1に示す半導体装置に搭載される半導体チップの裏面側の構造の一例を示す裏面図、図11は図10のA−A線に沿って切断した構造の一例を示す断面図である。
図12は図1に示す半導体装置の組み立てで用いられる配線基板の構造の一例を示す平面図、図13は図12のA−A線に沿って切断した構造の一例を示す断面図、図14は図12に示す配線基板における1つのデバイス領域の構造の一例を示す断面図、図15は図1に示す半導体装置の組み立てにおける半田プリコート後の構造の一例を示す断面図である。また、図16は図1に示す半導体装置の組み立てにおけるアンダーフィル塗布後の構造の一例を示す平面図、図17は図16のA−A線に沿って切断した構造の一例を示す断面図、図18は図1に示す半導体装置の組み立てのフリップチップ実装工程におけるチップ搭載後の構造の一例を示す断面図である。さらに、図19は図18に示すフリップチップ実装工程におけるチップ圧着後の構造の一例を示す断面図、図20は図1に示す半導体装置の組み立てのボールマウント後の構造の一例を示す断面図である。
本実施の形態の配線基板は、図12および図13に示すように、複数のデバイス領域2uを有する多数個取り基板(マトリクス基板)2tであり、多数個取り基板2tを用いて半導体装置を組み立てる場合を説明するが、予め1つのデバイス領域2uに個片化された配線基板を用いて半導体装置を組み立てることも可能である。
図16および図17に示すように、配線基板2の上面2aにアンダーフィル(封止材)6を配置する。この時、複数のボンディングリード2mを覆うようにアンダーフィル6を配置する。アンダーフィル6は、例えばNCF(Non-Conductive Film)であり、絶縁性のエポキシ系樹脂等から成るフィルム状の封止材(接着材)である。ただし、ペースト状の封止材であるNCP(Non-Conductive Paste) を用いてもよい。
図18に示すように、まず、半導体チップ1を配線基板2の上面2a上に配置する。この時、図10に示す半導体チップ1の複数のパッド1cと、配線基板2の複数のボンディングリード2mの位置を合わせる。ここで、半導体チップ1は、図10および図11に示すように、各パッド1cに形成された柱状(または突起状)の導電性部材(本実施の形態では、複数の銅ピラー4)を有している。
外部端子形成工程では、図20に示すように、配線基板2の下面2bの複数のランド2nに複数の半田ボール5をそれぞれ形成または接続する。なお、半田ボール5は、外部端子あるいはボール状電極等とも呼ばれる。
個片化工程では、回転する切断刃であるダイシング用のブレード(図示せず)を用いて個片化を行う。例えば、図12に示すような多数個取り基板2tの上方から切断部2rに対して上記ブレードを進入・回転させてダイシングを行い、各BGA7に個片化する。
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
図21は実施の形態の変形例1の半導体装置に組み込まれる配線基板の上面側のリード配列の一例を示す平面図である。
図22は実施の形態の変形例2の半導体装置の構造の一例を示す断面図である。
また、上記実施の形態では、半導体チップ1と配線基板2を電気的に接続する柱状または突起状の導電性部材として、例えば銅(Cu)を主成分とする材料を用いることについて説明したが、これに限定されるものではない。すなわち、銅(Cu)よりも柔らかい材料として、例えば金(Au)を主成分とする材料を用いてもよい。
図23は実施の形態の変形例4の半導体装置に組み込まれる配線基板の構造の一例を示す断面図である。
ガラスクロスを含まない樹脂層2db、2fbとガラスクロス2hを含む樹脂層(プリプレグ2da、2fa)との位置関係については、上記の実施の形態のような積層構造に限らない。すなわち、図24に示すように、ガラスクロスを含まない樹脂層2db、2fbは、柱状(または突起状)の導電性部材(銅ピラー4)が接続される電極(ボンディングリード2m)の直下にのみ設けられていてもよい。
上記実施の形態では、半導体装置がBGAの場合を一例として説明したが、上記半導体装置は、BGAに限らず、ランドの表面に導電性部材が形成されたLGA(Land Grid Array)であってもよい。
さらに、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
1a 主面(素子形成面)
1b 裏面
1c パッド(電極)
1d,1e 辺
2 配線基板
2a 上面(チップ搭載面)
2b 下面
2c ソルダレジスト膜(上面側保護膜)
2ca 内側ソルダレジスト膜(内側絶縁膜)
2d 絶縁層(絶縁膜)
2da プリプレグ(樹脂層)
2db 樹脂層(樹脂材)
2e コア層(プリプレグ)
2f 絶縁層(絶縁膜)
2fa プリプレグ(樹脂層)
2fb 樹脂層
2g ソルダレジスト膜(下面側保護膜)
2h ガラスクロス(ガラス繊維)
2i,2j 配線層
2k 開口部
2m ボンディングリード(電極)
2ma 外周リード群
2mb 内周リード群
2mba,2mbb,2mbc ボンディングリード(電極)
2n ランド(電極)
2p,2q 配線層
2r 切断部
2s 枠部
2t 多数個取り基板(マトリクス基板)
2u デバイス領域
2v ボンディングリード(電極)
2w 樹脂層
3 半田材(接続部材)
4 銅ピラー(導電性部材、ポスト)
5 半田ボール(導電性部材)
6 アンダーフィル(封止材)
7 BGA(半導体装置)
8 半導体チップ
8a 主面(素子形成面)
8b 裏面
8c パッド(電極)
9 ダイボンド材
10 ワイヤ(導電性部材)
11 封止体
12 BGA(半導体装置)
50 半導体チップ
52 バンプ(突起)
60 配線基板
61 樹脂層
64 ボンディングリード(電極)
65 ガラスクロス(ガラス繊維)
66 樹脂層
67 クラック
Claims (6)
- 以下の工程を含む半導体装置の製造方法:
(a)第1絶縁層、第2絶縁層、第1配線層および第2配線層、を有する配線基板を準備する工程;
ここで、
前記第1絶縁層は、ガラス繊維を有する第1樹脂層と、ガラス繊維を有さない第2樹脂層と、で構成されており、
前記第2樹脂層は、前記第1樹脂層と前記第2樹脂層との間に配線層を有さないように前記第1樹脂層上に積層されており、
前記第2絶縁層は、ガラス繊維を有する第3樹脂層で構成されており、
複数の第1配線パターンを有する前記第1配線層は、前記第1絶縁層の前記第1樹脂層と前記第2絶縁層である前記第3樹脂層との間に配置されており、
前記第2配線層に形成された複数のボンディングリードのそれぞれは、前記第2樹脂層上に形成されており、
(b)前記(a)工程の後、主面、前記主面に形成された複数のパッド、および前記主面とは反対側の裏面を有する半導体チップを、前記半導体チップの前記主面が前記配線基板の前記第2樹脂層の表面と対向するように、複数の導電性部材を介して前記配線基板の前記第2樹脂層の前記表面上に配置する工程;
(c)前記(b)工程の後、前記半導体チップの前記裏面に、前記配線基板の厚さ方向の荷重を加えることで、前記複数の導電性部材を介して前記複数のパッドと前記複数のボンディングリードをそれぞれ電気的に接続する工程。 - 請求項1記載の半導体装置の製造方法において、前記第2樹脂層の厚さは、前記第1樹脂層の厚さよりも薄い、半導体装置の製造方法。
- 請求項2記載の半導体装置の製造方法において、前記複数の導電性部材のそれぞれは、銅を主成分とする材料から成る、半導体装置の製造方法。
- 請求項3記載の半導体装置の製造方法において、前記(c)工程の前では、前記複数の導電性部材のそれぞれの先端面に半田材が配置され、前記配線基板の前記複数のボンディングリードのそれぞれの表面には半田材が配置されていない、半導体装置の製造方法。
- 請求項4記載の半導体装置の製造方法において、前記配線基板は、前記第1絶縁層と、前記第2絶縁層と、前記第1配線層と、前記複数のボンディングリードを構成する前記第2配線層と、複数のランドを構成する第3配線層と、をそれぞれ重ね合せ、さらに、圧接することで形成されたものである、半導体装置の製造方法。
- 請求項5記載の半導体装置の製造方法において、前記複数の導電性部材のそれぞれは、柱状である、半導体装置の製造方法。
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JP2013086899A JP6161380B2 (ja) | 2013-04-17 | 2013-04-17 | 半導体装置の製造方法 |
US14/229,981 US20140312498A1 (en) | 2013-04-17 | 2014-03-30 | Semiconductor device and method of manufacturing same |
TW103112076A TWI600123B (zh) | 2013-04-17 | 2014-04-01 | 半導體裝置及其製造方法 |
KR1020140044242A KR20140124725A (ko) | 2013-04-17 | 2014-04-14 | 반도체 장치 및 그 제조 방법 |
CN201410153991.7A CN104112715B (zh) | 2013-04-17 | 2014-04-17 | 半导体装置及其制造方法 |
HK15102431.6A HK1201990A1 (en) | 2013-04-17 | 2015-03-10 | Semiconductor device and method of manufacturing same |
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US20140312498A1 (en) | 2014-10-23 |
CN104112715B (zh) | 2018-04-10 |
TWI600123B (zh) | 2017-09-21 |
CN104112715A (zh) | 2014-10-22 |
KR20140124725A (ko) | 2014-10-27 |
TW201507073A (zh) | 2015-02-16 |
HK1201990A1 (en) | 2015-09-11 |
JP2014212174A (ja) | 2014-11-13 |
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