CN104112715B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN104112715B CN104112715B CN201410153991.7A CN201410153991A CN104112715B CN 104112715 B CN104112715 B CN 104112715B CN 201410153991 A CN201410153991 A CN 201410153991A CN 104112715 B CN104112715 B CN 104112715B
- Authority
- CN
- China
- Prior art keywords
- resin bed
- bonding wire
- semiconductor device
- wiring plate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 164
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 131
- 239000011347 resin Substances 0.000 claims abstract description 131
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 239000010949 copper Substances 0.000 claims description 66
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 61
- 229910052802 copper Inorganic materials 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 47
- 229910000679 solder Inorganic materials 0.000 claims description 38
- 239000003365 glass fiber Substances 0.000 claims description 15
- 239000011521 glass Substances 0.000 abstract description 41
- 239000004744 fabric Substances 0.000 abstract description 39
- 239000010410 layer Substances 0.000 description 73
- 230000008859 change Effects 0.000 description 20
- 239000012792 core layer Substances 0.000 description 19
- 230000035882 stress Effects 0.000 description 12
- 239000010931 gold Substances 0.000 description 11
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000012634 fragment Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910017770 Cu—Ag Inorganic materials 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
- H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
- H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
本发明涉及半导体装置及其制造方法。提供了一种具有改善的可靠性的半导体装置。在BGA的布线板中,绝缘层在其上具有多个接合引线。绝缘层由具有玻璃布的预浸料和不具有玻璃布的树脂层组成。预浸料在其上具有树脂层。接合引线被直接布置在较软的树脂层上,并且因此由这个较软的树脂层支撑。当在倒装芯片接合期间负荷被施加到每个接合引线时,树脂层下沉,由此可以使施加到半导体芯片的应力缓和。
Description
相关申请的交叉引用
将2013年4月17日提交的日本专利申请No.2013-086899的公开内容(包括说明书、附图以及摘要)通过参考全部并入在本申请中。
技术领域
本发明涉及半导体装置及其制造技术,例如,在应用于通过使用倒装芯片接合(flip chip bonding)技术将半导体芯片安装在布线板上而获得的半导体装置时有效的技术。
背景技术
日本专利公开No.2004-165311(专利文献1)描述了其中半导体芯片经由金属桩(post)而与板的芯片安装表面上的焊盘连接的结构。
日本专利公开No.2007-329396(专利文献2)描述了其中半导体衬底经由金属柱(column)和布置在其端部处的突出电极而被布置在安装板上的结构。
日本专利公开No.2009-289908(专利文献3)描述了其中通过接合引线上形成的焊料与由金制成的凸块(bump)电极之间的金-焊料接合来实现半导体芯片的焊盘与布线板的接合引线之间的电连接的结构。
[专利文献1]日本专利公开No.2004-165311
[专利文献2]日本专利公开No.2007-329396
[专利文献3]日本专利公开No.2009-289908(图38和39)
发明内容
在倒装芯片接合技术中,例如如上面在专利文献1和2中所述的,半导体芯片经由柱状的(桩状或支柱状的)导电部件被安装在布线板上,或者,如上面在专利文献3中所述的,半导体芯片经由突出(凸块状)导电部件被安装在布线板上。在倒装芯片接合技术中,在半导体芯片被安装时,沿与其垂直的方向(沿布线板的厚度方向)将负荷施加到布置在布线板上的半导体芯片。
然而在布线板的芯片安装表面上形成的电极(接合引线,连接到导电部件的电极)、要用于将半导体芯片与布线板电气连接的柱状(桩状)或突出(凸块状)导电部件、或者电极和导电部件两者之间存在变化。
换句话说,由于加工中的变化的影响,电极的各个表面(连接到导电部件的表面)不总是具有相同的高度(换句话说,并不总是彼此齐平)或者导电部件不总是具有相同的高度(尺寸)(换句话说,并不总是彼此齐平)。当半导体芯片被布置在布线板上时,导电部件中的一些未能与布线板的电极接触。
当支撑布线板的电极的绝缘层(电极接触的绝缘层)不是预浸料(prepreg)(包含玻璃布(glass cloth)的树脂层)时,换言之,由不包含玻璃布(其也可以被称作“玻璃纤维”)的树脂层组成时,绝缘层具有比预浸料低的硬度(刚性或强度)。
如图25所示,负荷到半导体芯片50的施加使接触到凸块52(导电部件)的布线板60的接合引线64下沉。换句话说,负荷到不包含玻璃布的树脂层61的施加使得这个树脂层61变形。
即使凸块52或接合引线64的高度改变,这个高度变化也可以被接合引线64的下沉吸收,使得凸块52和接合引线64之间的接合故障可以被抑制。
如上所述,另一方面,不包含玻璃布的树脂层61具有比其层被示出在图26中的包含玻璃布65的树脂层66(预浸料)低的硬度。从减薄半导体装置的观点来看,不使用预浸料作为支撑包括接合引线64的布线层的树脂层的半导体装置是不利的。
然而,当采用树脂层(预浸料)66作为支撑电极(诸如如图26所示的接合引线64)的绝缘层时,与不包含玻璃布的树脂层61不同,即使负荷被施加到这个树脂层66它也不容易变形。因此在这个树脂层66上形成的接合引线64不下沉。换句话说,由于作为绝缘层的树脂层66不容易变形,因此难以吸收凸块或接合引线之间的高度变化。
在此公开的实施例的一个目的是提供能够改善半导体装置的可靠性的技术。
根据在此的描述和附图,其它目的和新颖的特征将是清楚的。
根据一个实施例的半导体装置包括布线板和半导体芯片,所述布线板具有第一绝缘层、多个接合引线和多个连接盘,所述半导体芯片经由多个导电部件被安装在布线板上,使得半导体芯片的主表面面对布线板。导电部件经由多个焊料材料而与布线板的接合引线分别连接。在上述的半导体装置中,第一绝缘层由具有玻璃纤维的第一树脂层以及没有玻璃纤维的第二树脂层构成,并且每个接合引线与第二树脂层接触。
根据上述一个实施例,可以提供具有改善的可靠性的半导体装置。
附图说明
图1是示出根据实施例的半导体装置的结构的一个示例的平面图;
图2是示出沿着图1中示出的线A-A截取的结构的一个示例的截面图;
图3是示出图1中示出的半导体装置的背面侧结构的一个示例的背面视图;
图4是示出要被并入图1中示出的半导体装置中的布线板的上表面侧结构的一个示例的平面图;
图5是示出沿着图4中示出的线A-A截取的结构的一个示例的截面图;
图6是示出图5中示出的部分B的结构的一个示例的放大片段截面图;
图7是示出图4中示出的布线板的下表面侧结构的一个示例的背面视图;
图8是示出要被安装在图1中示出的半导体装置上的半导体芯片的主表面侧结构的一个示例的平面图;
图9是示出沿着图8中示出的线A-A截取的结构的一个示例的截面图;
图10是示出要被安装在图1中示出的半导体装置上的半导体芯片的背面侧结构的一个示例的背面视图;
图11是示出沿着图10的线A-A截取的结构的一个示例的截面图;
图12是示出要在图1中示出的半导体装置的制造中使用的布线板的结构的一个示例的平面图;
图13是示出沿着图12的线A-A截取的结构的一个示例的截面图;
图14是示出图12中示出的布线板中的一个装置区域的结构的一个示例的截面图;
图15是示出图1中示出的半导体装置的制造中的焊料预涂覆之后的结构的一个示例的截面图;
图16是示出图1中示出的半导体装置的制造中的底部填料(underfill)施加之后的结构的一个示例的平面图;
图17是示出沿着图16中示出的线A-A截取的结构的一个示例的截面图;
图18是示出图1中示出的半导体装置的制造中的倒装芯片接合步骤中的芯片安装之后的结构的一个示例的截面图;
图19是示出图18中示出的倒装芯片接合步骤中的芯片的压力接合之后的结构的一个示例的截面图;
图20是示出图1中示出的半导体装置的制造中的球安装(ball mounting)之后的结构的一个示例的截面图;
图21是示出要被并入根据实施例的变型示例1的半导体装置中的布线板的上表面侧上的引线布置的一个示例的平面图;
图22是示出根据实施例的变型示例2的半导体装置的结构的一个示例的截面图;
图23是示出要被并入根据实施例的变型示例4的半导体装置中的布线板的结构的一个示例的截面图;
图24是示出实施例的变型示例5的布线板的一个示例的放大片段截面图;
图25是示出在本发明的发明人研究的倒装芯片接合中的负荷施加期间的第一结构的放大片段截面图;以及
图26是示出在本发明的发明人研究的倒装芯片接合中的负荷施加期间的第二结构的放大片段截面图。
具体实施方式
在下面描述的实施例中,除非特别必要否则将基本上省略对相同的或类似的部件的描述。
在下面描述的实施例中,为了方便起见必要时将在分成多个部分或多个实施例之后进行描述。除非具体地指出,否则这些多个部分或实施例不是彼此独立的,而是处于使得一个是另一个的部分或整体的变型示例、细节或互补的描述的关系。
在下面描述的实施例中,当提到要素的数字(包括个数、值、量、范围等)时,除非具体地指出或者在原理上清楚该数字被限制于特定的数字的情况下,否则要素的数字不限于特定的数字而是可以大于或小于该特定的数字。
此外在下面描述的实施例中,不用说,除非具体地指出或者在原理上清楚构成要素必不可少的情况下,否则构成要素(包括要素步骤)并不总是必不可少的。
另外,不用说,提及在下面描述的实施例中使用的构成要素时,除非具体地指出构成要素被限制于仅仅特定的要素,否则术语“由A制成”、“由A组成”、“具有A”或者“包括A”不排除其它要素。类似地,在下面描述的实施例中,当提到构成要素的形状或者位置关系时,除非具体地指出或者原理上清楚它不是的情况下,否则也包括与其基本上类同的或者类似的形状或者位置关系。这也适用于上述的值和范围。
在下文中,将基于附图详细描述本发明的实施例。在用于描述实施例的所有附图中,将用类似的附图标记来标识类似的功能的部件,并且将省略重复的描述。此外,为了便于理解附图,甚至平面图有时也可以被画阴影线。
(实施例)<半导体装置>
图1是示出根据实施例的半导体装置的结构的一个示例的平面图;图2是示出沿着图1中示出的线A-A截取的结构的一个示例的截面图;并且图3是示出图1中示出的半导体装置的背面侧结构的一个示例的背面视图。
接下来将描述图1-3中示出的根据实施例的半导体装置的构造。如图2所示,本实施例的半导体装置具有布线板2。半导体芯片1被倒装芯片接合到这个布线板2上。这意味着半导体芯片1经由多个导电部件而被安装在布线板2的上表面2a上,使得半导体芯片1的主表面1a面对布线板2的上表面(芯片安装表面)2a。
另一方面,布线板2在其下表面2b上具有多个焊球5,该多个焊球5将用作半导体装置的外部端子。在本实施例中,这些焊球5在平面图中以格子形式被布置,如图3所示。
因此,在本实施例中,BGA(球栅阵列)7将作为上述半导体装置的一个示例被描述。
在根据本实施例的BGA7中,设置在半导体芯片1的主表面(元件形成表面)1a上的多个焊盘(电极)1c以及设置在布线板2的上表面2a上的多个接合引线(电极)2m分别经由导电部件和焊料材料(连接部件)3而彼此电气连接。
在根据本实施例的BGA7中,半导体芯片1的焊盘1c在其上具有导电部件。在本实施例中,将描述使用铜(Cu)支柱(pillar)4作为导电部件的BGA7。铜支柱4中的每一个由主要由铜组成的材料制成,并且同时它们是柱状(桩状)电极。因此半导体芯片1经由分别形成在半导体芯片的主表面1a上的焊盘1c的表面上的这些铜支柱4而与布线板2倒装芯片式连接。在倒装芯片接合中,铜支柱4经由分别布置在铜支柱的端面(与接合引线2m相对的表面)上的焊料材料3而分别与布线板2的接合引线2m电气连接。
作为在此描述的焊料材料3,基本上没有铅(Pb)的所谓的无铅焊料是优选的。它是例如锡-银(Sn-Ag)焊料。
使用这种材料使得可以应付环境污染问题。术语“无铅焊料”意味着铅(Pb)的含量不大于0.1wt%的焊料。这个含量已经被确定为RoHS(有害物质限制)指令的标准。
在BGA7中,在布线板2的上表面2a侧,在半导体芯片1和布线板2之间形成的空间用作为成型(molding)树脂的底部填料6填充,如图2所示。这个底部填料6是例如环氧树脂并且该空间用它填充以使得确保半导体芯片1和布线板2之间的连接可靠性。
底部填料6还覆盖半导体芯片1的侧表面。这使得可以保护倒装芯片连接(铜支柱4和接合引线2m之间的连接),并且另外,可以防止水从半导体芯片1的外部(周边)浸入到倒装芯片连接。然而半导体芯片1的背面1b在朝向BGA7的上部的同时被露出,如图1和2所示。
如图2所示,布线板2是具有多个布线层的多层布线板。具体而言,核芯层2e在其表面和背面上具有布线层2i和布线层2j,并且如图5所示,最上的布线层2p具有用于倒装芯片连接的接合引线2m。另一方面,最下的布线层2q在其中具有用于连接到作为BGA7的外部端子的焊球(导电部件)5的多个连接盘(land)(电极)2n。
这意味着布线板2的上表面2a和下表面2b在其上分别具有作为绝缘膜的阻焊膜2c和2g。在上表面2a侧,阻焊膜2c在其开口部2k中具有接合引线2m,而在下表面2b侧,阻焊膜2g在其多个开口部2k中分别具有连接盘2n。
在本实施例的布线板2中,在上表面2a侧,接合引线2m被布置在绝缘层2d上。这个绝缘层2d由具有玻璃布(玻璃纤维)2h的预浸料(树脂层)2da和不具有玻璃布2h的树脂层2db组成。更具体地,树脂层2db被形成(堆叠)在预浸料2da(在半导体芯片1侧的表面)上。
因此,接合引线2m中的每一个接触树脂层2db并且被布置在这个树脂层2db上。此外,接合引线2m经由焊料材料3而分别与铜支柱4连接,使得预浸料2da与铜支柱4中的每一个在其之间具有树脂层2db。
当将具有玻璃布2h的预浸料2da和不具有玻璃布2h的树脂层2db相比较时,预浸料2da具有更大的(更高的)硬度和更大的刚度。这意味着具有玻璃布2h的预浸料2da较硬,而不具有玻璃布2h的树脂层2db较软。
接合引线2m中的每一个在其与较软的树脂层2db之间没有包含玻璃布(玻璃纤维)2h的预浸料2da的情况下接触较软的树脂层2db(不包含玻璃布的层)。
如上所述,在BGA7的布线板2中,预浸料2da在其上经由较软的树脂层2db具有接合引线2m,使得由于倒装芯片连接等引起的负荷的施加导致树脂层2db的变形和接合引线2m的下沉。即使在铜支柱4之间发生高度变化,所有铜支柱4也可以因此与接合引线2m连接。简而言之,即使具有低高度的铜支柱4也可以与接合引线2m连接。
另外,与铜支柱4之中的具有比其它铜支柱4更大的高度的铜支柱连接的布线板2的接合引线2m下沉,使得可以抑制在其上形成有这个高的铜支柱4的半导体芯片1的焊盘1c正下方的绝缘层中的裂缝67(参考图26)的形成。这使得可以改善BGA7的可靠性。
此外,即使在应力被施加到BGA7的焊球5等时,这个应力也可以利用较软的树脂层2db被缓和并且可以抑制对倒装芯片连接的损伤的直接传播。
具体而言,由于较软的树脂层2db被布置在连接铜支柱4的接合引线2m的下面,因此甚至包括施加到焊球5的热应力的应力也被较软的树脂层2db的变形吸收以便使应力缓和并且防止对倒装芯片连接或者半导体芯片1的损伤的直接传播。
结果,可以抑制倒装芯片连接处的连接故障的出现。
<布线板>
图4是示出要被并入图1中示出的半导体装置中的布线板的上表面侧结构的一个示例的平面图;图5是示出沿着图4中示出的线A-A截取的结构的一个示例的截面图;图6是示出图5中示出的部分B的结构的一个示例的放大片段截面图;并且图7是示出图4中示出的布线板的下表面侧结构的一个示例的背面视图。
接下来,将描述根据本实施例的布线板2的细节结构。
如上所述,布线板2为多层布线板并且在本实施例中,将描述具有四个布线层的多层布线板作为示例。然而布线层的数量不限于四个。
布线板2具有上表面2a和下表面2b,上表面2a具有如图4所示的方形平面形状,下表面2b为与上表面2a相对的安装表面或者背面。
如图4所示,布线板2在其上表面2a上具有在最上的布线层上形成的用于倒装芯片连接的多个接合区域2m。它们在图5中示出的阻焊膜2c的开口部2k中被布置成两行,即内侧行和外侧行。内侧行和外侧行的接合引线在彼此不交迭的情况下被布置,使得它们对应于在芯片侧以Z字形(zigzag)方式布置的焊盘并且适合于多管脚连接(multi-pinconnection)。
从在其中具有接合引线2m的阻焊膜2c的开口部2k,还露出支撑这些接合引线2m的树脂层2db。
如图7所示,另一方面,在布线板2的下表面2b上,在最下的布线层中形成的用于焊球连接的多个连接盘2n被分别布置在图5中示出的阻焊膜2g的多个开口部2k中,并且这些连接盘2n以格子形式被布置。
如图5和6所示,布线板2是通过层叠核芯层(预浸料)2e、分别布置在核芯层2e的上表面和下表面上的布线层2i和2j、绝缘层(绝缘膜)2d和2f、以及分别为最上层和最下层的布线层2p和2q来形成的。这些部件利用加压通过接触接合而被彼此层叠。例如,诸如核芯层2e、布线层2i和2j、绝缘层2d和2f、以及布线层2p和2q之类的部件被夹在平板状钢板之间并且在高压强之下在高温处被按压。
因此,根据装置区域2u的位置(参考图12),特别地在形成在诸如最上层和最下层之类的最外层上的布线(包括诸如接合引线2m和连接盘2n之类的电极)之间出现高度变化。
如图6所示,根据本实施例的布线板2具有拥有四个布线层的结构。它在其核芯层2e的表面和背面上分别具有布线层2i和布线层2j,并且经由绝缘层2d和绝缘层2f在最上的布线层2p和最下的布线层2q中具有多个布线(布线图案)。在最上的布线层2p中形成的布线中的每一个的一部分构成用于倒装芯片连接的多个接合引线(电极)2m。
由于布线板的上述制造方法(接触接合),因此,倾向于在作为在最上的(最外的)布线层2p中形成的电极的接合引线2m之间发生高度变化。
布线板2在其最下的布线层(在下表面2b侧)2q中具有用于连接焊球5的多个连接盘2n。这意味着在最下的布线层2q中形成的布线中的每一个的一部分构成用于连接作为外部端子的焊球的多个连接盘(电极)2n。
在布线板2中,多个接合引线2m被形成在上表面2a侧,并且与多个接合引线2m对应的多个连接盘2n被形成在下表面2b侧。彼此对应的接合引线2m和连接盘2n经由未示出的内部布线、贯通孔布线等而彼此电气连接。
布线板2在其上表面2a和下表面2b上分别具有作为绝缘膜的阻焊膜2c和2g。在上表面2a侧,阻焊膜2c在其开口部2k中具有多个接合引线2m,而在下表面2b侧,阻焊膜2g在其多个开口部2k中分别具有连接盘2n。
这意味着在布线板2的上表面2a侧,绝缘层2d在其上表面上具有阻焊膜(上表面侧保护膜)2c,从而露出多个接合引线2m,而在布线板2的下表面2b侧,绝缘层2f在其下表面上具有阻焊膜(下表面侧保护膜)2g,从而露出多个连接盘2n。
在上表面2a侧,绝缘层2d在其上具有多个接合引线2m。这个绝缘层2d由具有玻璃布(玻璃纤维)2h的预浸料(树脂层)2da和不具有玻璃布2h的树脂层2db组成,并且这个预浸料2da在其上具有树脂层2db。
因此这些接合引线2m中的每一个与树脂层2db接触并且它们被布置在这个树脂层2db上。换句话说,这些接合引线2m由树脂层2db支撑。
此外在下表面2b侧,绝缘层2f在其上具有多个连接盘2n。这个绝缘层2f由具有玻璃布(玻璃纤维)2h的预浸料(树脂层)2fa和不具有玻璃布2h的树脂层2fb组成。类似于上表面2a侧,连接盘2n中的每一个与树脂层2fb接触并且它们被布置在这个树脂层2fb上。换句话说,这些连接盘2n由树脂层2fb支撑。
上述树脂层(树脂材料)2db和2fb由例如环氧树脂制成。树脂层2db和2fb的树脂为不具有玻璃布(玻璃纤维)2h但是具有多种填料(filler)的树脂。
另一方面,预浸料2da和2fa由例如环氧树脂制成。预浸料2da和2fa的树脂具有多种填料并且还具有玻璃布(玻璃纤维)2h。
当将具有玻璃布2h的预浸料2da和2fa与不具有玻璃布2h的树脂层2db和2fb相比较时,预浸料2da和2fa具有更大的(更高的)硬度和更大的刚度。换句话说,具有玻璃布2h的预浸料2da和2ft较硬,但是不具有玻璃布2h的树脂层2db和2fb具有较小的(较低的)硬度并且较软。
接合引线2m中的每一个被直接布置在较软的树脂层2db上,并且这个较软的树脂层2db在其下方具有较硬的预浸料2da。
另一方面,在下表面2b侧的连接盘2n中的每一个被直接布置在较软的树脂层2fb上,并且这个较软的树脂层2fb在其下方(在核芯层2e侧,在下表面2b侧)具有较硬的预浸料2fa。
布线板2中的布线层的布线、连接盘2n和接合引线2m中的每一个由主要由铜组成的材料制成,并且接合引线2m和连接盘2n具有镀敷的表面。
关于布线板2的层中的每一个的厚度,作为树脂层的预浸料2da和2fa具有例如30μm的厚度,并且预浸料2da和2fa上的树脂层2db和2fb具有例如5μm的厚度。核芯层2e具有例如从40到60μm的厚度并且布线层中的每一个具有例如十几μm的厚度。这意味着树脂层2db和2fb比预浸料2da和2fa薄。
树脂层2db的厚度可以等于预浸料2da的厚度或者可以比预浸料2da的厚度大。
然而,当考虑半导体装置的减薄或者布线板的翘曲时,优选的是,如在本实施例中一样使得树脂层2db或2fb比预浸料2da或2fa薄。
布线板2的接合引线2m可以在其表面上具有焊料材料3。当在倒装芯片连接期间负荷被施加时,布置在每一个铜支柱4和每一个接合引线2m上的焊料材料3可以吸收部件的高度变化。
当焊料材料3不被布置在接合引线2m(由纯铜制成的接合引线2m或者具有镀金的表面的接合引线2m)中的每一个上时,因为不使用焊料材料3,BGA7的成本可以被减少。
<半导体芯片>
图8是示出要被安装在图1中示出的半导体装置上的半导体芯片的主表面侧结构的一个示例的平面图;图9是示出沿着图8中示出的线A-A截取的结构的一个示例的截面图;图10是示出要被安装在图1中示出的半导体装置上的半导体芯片的背面侧结构的一个示例的背面视图;并且图11是示出沿着图10的线A-A截取的结构的一个示例的截面图。
如图8和9所示,半导体芯片在其主表面1a上在主表面1a的周边(外周缘部分)处具有成两行的多个焊盘1c。根据本实施例的半导体芯片1适合于多管脚连接,使得这些焊盘1c以Z字形方式被设置。
此外,如图10和11所示,作为导电部件的铜支柱4分别与焊盘1c连接。铜支柱4中的每一个是柱状的(桩状)电极并且由例如具有铜(Cu)作为主要成分的材料制成。
例如通过电镀形成铜支柱4。具体而言,这个支柱通过在未示出的半导体晶片的主表面(元件形成表面)上放置具有与半导体晶片的每一个芯片形成区域中的焊盘布置对应的多个圆孔的干膜并且通过电镀在孔中从下方开始堆积来形成。
作为导电部件,可以使用突出(凸块)电极。突出电极由例如具有金(Au)作为主要成分的材料制成。使用利用毛细管作用(capillary)的导线接合技术形成突出电极,使得在形成这个突出电极之前半导体晶片被切成半导体芯片。
如上所述,通过在半导体晶片的主表面上形成干膜(抗蚀剂膜)并且随后例如通过电镀(也可以使用无电镀敷)形成每个芯片形成区域的多个焊盘,获得柱状的电极。从用于形成导电部件的步骤的数量的观点来看,如在本实施例中一样,使用柱状的(桩状)电极是优选的。
<半导体装置的制造方法>
图12是示出要在图1中示出的半导体装置的制造中使用的布线板的结构的一个示例的平面图;图13是示出沿着图12的线A-A截取的结构的一个示例的截面图;图14是示出图12中示出的布线板中的一个装置区域的结构的一个示例的截面图;并且图15是示出图1中示出的半导体装置的制造中的焊料预涂覆之后的结构的一个示例的截面图。图16是示出图1中示出的半导体装置的制造中的底部填料施加之后的结构的一个示例的平面图;图17是示出沿着图16中的线A-A截取的结构的一个示例的截面图;并且图18是示出图1中示出的半导体装置的制造中的倒装芯片接合步骤中的芯片安装之后的结构的一个示例的截面图。图19是示出图18中示出的倒装芯片接合步骤中的芯片的压力接合之后的结构的一个示例的截面图;并且图20是示出图1中示出的半导体装置的制造中的球安装之后的结构的一个示例的截面图。
1、布线板的设置(多片式(multi-piece)布线板)
如图12和13所示,根据本实施例的布线板是具有多个装置区域2u的多片式布线板(矩阵板(matrix board))2t。在下文中将描述通过使用这个多片式布线板2t的半导体装置的制造。然而可以通过使用预先已经被分成每个装置区域2u的布线板来制造半导体装置。
在根据本实施例的半导体装置的制造中,为了方便起见将参考仅仅示出装置区域2u之一的附图进行描述。不用说,当使用多片式布线板2t制造装置时,多片式布线板2t上的多个装置区域2u经受每个步骤中的期望的处理。
首先,提供多片式布线板2t。多片式布线板2t具有上表面2a和在与上表面2a相对的那侧的下表面2b。此外,多片式布线板2t具有多个装置区域2u(这里作为一个示例示出2×4=8个装置区域2u)、设置在多个装置区域2u之中的彼此相邻的装置区域2u之间的切割部位(site)2r、以及在平面图中设置在多个装置区域2u周围的框架部分2s。切割部位2r也被称为“除去部位”、“划片(dicing)部位”、“划片区域”等。
切割部位2r具有凹槽形状,如图13所示。更具体地,切割部位是通过在形成镀敷膜之后刻蚀并且由此去除用于通过电镀法在每个布线的表面上形成镀敷膜的供电线而形成的凹槽。由于切割部位2r具有凹槽形状,因此可以减少在单片化(singulation)步骤中划片期间来自阻焊膜2c的切割灰尘(dust)的产生。此外,还可以减少划片刀片的负荷。因此,可以利用改善的技术执行切割。
在图12中示出的框架部分2s上的每个切割部位2r的延伸处,存在未示出的划片标记。在用于单片化的划片期间,在识别标记之后,从其中找到刀片的运行线(running line)并且随后,使得旋转的刀片运行以便在切割部位2r处切割该板。
如图12所示,在每个装置区域2u中,在靠近装置区域的中心部分的阻焊膜2c的开口部2k中,用于倒装芯片连接的接合引线2m沿着多片式布线板2t的每个边被布置成两个或更多个行(这里,两行)。根据图8中示出的半导体芯片1的焊盘1c的布置,两行接合引线2m以Z字形方式被布置。接合引线2m的行的数量可以是单个(一行)。
在根据本实施例的多片式布线板2t的每个装置区域2u中,接合引线2m被布置在绝缘层2d上,如图14所示。这个绝缘层2d由具有玻璃布(玻璃纤维)2h的预浸料(树脂层)2da和不具有玻璃布2h的树脂层2db组成。预浸料2da在其上具有树脂层2db。
由于这种结构,每个接合引线2m与树脂层2db接触并且被布置在这个树脂层2db上。换句话说,接合引线2m由与预浸料2da相比具有更低硬度的和更软的树脂层2db支撑。
多片式布线板2t在其下表面2b上具有与上表面2a上的接合引线2m电气连接的多个连接盘2n,并且在下表面2b上具有阻焊膜2g使得露出每个连接盘2n。
多片式布线板2t是通过一个接一个地重叠核芯层(预浸料)2e、在核芯层2e上和在核芯层2e下的布线层2i和2j、绝缘层(绝缘膜)2d和2f、构成接合引线2m的布线层2p以及构成连接盘2n的布线层2q并且加压接合来获得的。例如,诸如核芯层2e、布线层2i和2j、绝缘层2d和2f、以及布线层2p和2q之类的部件被夹在平板状钢板之间,继而在高压强下在高温处按压它们。
根据装置区域2u中的位置,倾向于在电极(特别地,诸如最上的布线层2p的接合引线2m之类的电极或者诸如最下的布线层2q的连接盘2n之类的电极)的高度方面发生变化。
例如,在最上的(最外的)布线层2p中形成的接合引线2m中,由于通过加压的接触接合,可能发生电极高度的变化。
考虑到由上述的电极高度的变化引起的倒装芯片连接中的连接故障的减少,焊料材料3优选地被布置在每个接合引线2m的表面上,如图15所示。这意味着在倒装芯片连接时,上述的电极高度的变化可以被分别布置在接合引线2m的表面上的焊料材料3吸收,这使得倒装芯片连接中的连接故障减少。
然而,当如图10的半导体芯片1所示的铜支柱4被用作用于倒装芯片连接的导电部件时,每个接合引线2m的表面上的焊料材料3并不总是必要的。在该情况下,省略这个焊料材料3使得布线板的成本减少。
2、成型材料的布置(底部填料的施加)
如图16和17所示,底部填料(成型材料)6被布置在布线板2的上表面2a上。这个底部填料6被布置为使得用其覆盖多个接合引线2m。底部填料6是例如NCF(非导电膜)和由绝缘的环氧树脂等制成的膜形状的成型材料(粘合剂)。可替代地,可以使用作为浆料形式的成型材料的NCP(非导电浆料)。
这里,在倒装芯片连接之前底部填料6被布置在布线板2上。可替代地,可以在倒装芯片连接之后将底部填料6填充在布线板2和半导体芯片1之间。
3、倒装芯片接合
如图18所示,半导体芯片1被布置在布线板2的上表面2a上。它在将图10中示出的半导体芯片1的焊盘1c的位置与布线板2的接合引线2m的位置相匹配的时候被布置。如图10和11所示,半导体芯片1具有在每个焊盘1c上形成的柱状的(或者突出的)导电部件(在本实施例中为多个铜支柱4)。
如图18所示,铜支柱4在其端面(面对接合引线2m的表面)上分别具有焊料材料3。
具有设置有在其端面上具有焊料材料3的铜支柱4的焊盘1c的半导体芯片1经由铜支柱4被布置在布线板2的上表面2a上,使得半导体芯片1的主表面1a面对布线板2的上表面2a。
然后,如图19所示,进行芯片的压力接合。在这时候,通过向半导体芯片1的背面1b施加在布线板2的厚度方向(垂直方向,从布线板2的上表面2a到下表面2b的方向)上的负荷(垂直负荷)F和热量,在铜支柱4的端面上形成的焊料材料3接触布线板2的接合引线2m。然后热量被施加到在铜支柱4和接合引线2m之间要连接(接合)的部分以便熔化焊料材料3并且经由焊料材料3将铜支柱4和接合引线2m彼此电气连接。
在本实施例的布线板2中,支撑接合引线2m的绝缘层2d是不包含玻璃布2h的较软的树脂层2db。当在倒装芯片接合期间负荷被施加到接合引线2m时,因此树脂层2db变形并且在这个树脂层2db上设置的接合引线2m下沉。因此如果有的话,在导电部件(铜支柱4)或者接合引线2m之间的高度变化不妨碍具有小的高度的铜支柱4与接合引线2m之间的连接。此外,由于接合引线2m在其下部(在核芯层2e侧,在下表面2b侧)中具有较软的树脂层2db,使得即使在倒装芯片接合期间负荷被从铜支柱4施加到接合引线2m时,可归因于电极的高度变化的应力也可以通过较软的树脂层2db的下沉被吸收。结果,可以减少要被施加到半导体芯片1的应力。
这使得可以减少对半导体芯片1的损伤并且由此防止半导体芯片1中的裂缝或者麻烦(诸如表面保护膜的剥落)。简而言之,可以减少或者防止在倒装芯片接合期间对半导体芯片1的损伤。
结果,可以改善半导体装置(BGA7)的可靠性。
当在倒装芯片接合期间负荷被施加时,支撑接合引线2m的树脂层2db下沉以便吸收在铜支柱4或者接合引线2m之间的高度变化。这使得可以减少在倒装芯片接合时半导体芯片1的连接故障并且由此改善半导体芯片1的连接可靠性。
结果,可以改善半导体装置(BGA7)的可靠性。
在布线板2中,通过使得预浸料2da的厚度比树脂层2db的厚度大,预浸料2da具有比树脂层2db大的硬度。结果,能够减小板的翘曲。此外,核芯层2e的厚度可以通过使绝缘层2d的预浸料2da变厚而被减少。这引起布线板2的总厚度的减少并且此外半导体装置(BGA7)的厚度的减少。
铜支柱4中的每一个在其端面上具有焊料材料3。焊料材料3通过加热熔化并且吸收在利用力布置铜支柱4时由于铜支柱4或者接合引线2m之间的高度变化形成的铜支柱4与接合引线2m之间的空隙。
当不仅铜支柱4而且接合引线2m在其表面上具有焊料材料3时,可以进一步吸收铜支柱4或者接合引线2m之间的高度变化并且可以进一步减少在倒装芯片接合时的半导体芯片1的连接故障。
另外,通过使用铜支柱4作为导电部件,铜支柱4可以在晶片阶段中一起与焊盘1c连接。因此,导电部件可以有效地与焊盘1c连接。
铜支柱4是柱状的导电部件,使得它们可以保证倒装芯片接合中的电极高度(半导体芯片1与布线板2之间的距离)。
当增加负荷F时,底部填料6通过半导体芯片1也被向下变平,使得倒装芯片连接被底部填料6填充,并且被变平以从半导体芯片1的周边突出的底部填料6在半导体芯片1的每个侧表面之上延伸。结果,半导体芯片1的每个侧表面被底部填料6覆盖。
通过上述步骤完成倒装芯片接合。
4、外部端子的形成(球安装)
在外部端子形成步骤中,如图20所示,多个焊球5被形成在布线板2的下表面2b上的多个连接盘2n上或者与该多个连接盘2n连接。这些焊球5也被称为外部端子或球状电极等。
要与连接盘2n连接的外部端子不限于球状焊料材料,并且它可以通过利用焊料材料涂敷连接盘2n的表面或者在连接盘2n的表面上形成的镀敷膜(镀敷层)而获得。在该情况下,由此获得的半导体装置是LGA(平面网格阵列(land grid array))。
类似于上述焊料材料3,用于焊球5的焊料材料由基本上不包含铅(Pb)的所谓的无铅焊料制成。例如,它仅仅由锡(Sn)制成或者由锡-铜-银(Sn-Cu-Ag)制成。
5、单片化
通过使用作为旋转的切割刀片的划片刀片(未示出)进行单片化步骤。例如,通过从如图12所示的多片式布线板2t上方将刀片插入到切割部位2r中、旋转它并且由此对布线板进行划片,来进行单片化成每个BGA7。
可以不仅通过利用刀片的划片而且通过利用冲模的切割,来实现单片化。
以上述方式,完成图1-3中示出的BGA7的制造。
<变型示例>
已经基于本发明的实施例具体地描述了由本发明的发明人做出的本发明。然而不必说,本发明不限于本发明的上述实施例,而是可以在不脱离本发明范围的情况下以各种方式进行改变。
(变型示例1)
图21是示出要被并入根据实施例的变型示例1的半导体装置中的布线板的上表面侧上的引线布置的一个示例的平面图。
图21中示出的结构示出采用多管脚连接的倒装芯片接合类型半导体装置的变型示例,在其中布线板2上的多个接合引线2m的布置模式已经被修改。
在采用多管脚连接的半导体装置中,如从图8中示出的半导体芯片1明白的,焊盘1c经常以Z字形方式被布置。在图21中示出的布线板侧的阻焊膜2c的开口部2k中设置的多个接合引线2m被布置成两行,即,外周边引线组2ma与内周边引线组2mb。
此外,在布线板2中,内周边引线组2mb在平面图中具有在与半导体芯片1的边1d交叉(几乎垂直)的方向上延伸的多个接合引线2mba、在与半导体芯片1的边1e交叉(几乎垂直)的方向上延伸的多个接合引线2mbb、以及在既不与边1d垂直也不与边1e垂直的方向上延伸的多个接合引线2mbc。
这意味着从阻焊膜2c的框架状开口部2k露出的内周边引线组2mb的接合引线2m可以根据它们的延伸方向被分类为上述三组(接合引线2mba、2mbb与2mbc)。在这三组接合引线中,在既不与半导体芯片1的边1d垂直也不与边1e垂直的方向上延伸的接合引线2mbc被布置在框架状开口部2k的角落附近。
这意味着在内周边引线组2mb的接合引线2m之中,布置在开口部2k的角落附近的接合引线2mbc很可能与位于几乎垂直于包括上述接合引线2mbc的引线行的另一个引线行的端部(角落)处的接合引线2mbc接触。因此布置在角落附近的接合引线相对于布置的中心部分附近的接合引线2m倾斜地布置。当仅仅倾斜地布置在端部位置处的接合引线2mbc时,在它们的内侧端部处发生这个接合引线2mbc与同一行中但与其相邻的接合引线2mbc之间的干涉。在各个角落部分附近的多个(在图21中从端部开始数起四个引线)接合引线2mbc被倾斜地布置,使得它们从布线板2的中心部分向外辐射。
因此,接合引线2mbc的延伸方向既不与半导体芯片1的边1d垂直也不与边1e垂直。
因此这种布置可以防止彼此相邻的两个接合引线2m之间的短路。结果,可以实现半导体装置的多管脚连接。
内周边引线组2mb的接合引线2m中的每一个沿着与作为覆盖接合引线2m的一部分的绝缘膜的一部分的内侧阻焊膜(内侧绝缘膜)2ca的端部交叉(几乎垂直)的方向延伸。
这意味着内周边引线组2mb的所有接合引线2m被布置在具有基本上方形形状的内部阻焊膜2ca的每一个边上使得与边(端部)垂直。这使得可以使得从内侧阻焊膜2ca露出的内周边引线组2mb的接合引线2m的长度几乎彼此相等。这也适用于外周边引线组2ma的接合引线2m。它们被布置为使得,使从阻焊膜2c露出的布置在开口部2k中的接合引线2m的长度基本上彼此相等。
即使在接合引线2m上形成焊料预涂层,引线也可以利用基本上等量的焊料被预涂敷,并且因此可以形成具有基本上相等的高度的焊料预涂层。
结果,可以在倒装芯片接合期间实现均匀的焊料湿度(wetness)。
(变型示例2)
图22是示出实施例的变型示例2的半导体装置的结构的一个示例的截面图。
变型示例2的半导体装置是芯片堆叠类型半导体装置。在这个半导体装置中,在倒装芯片接合到布线板2的半导体芯片1上,另一个半导体芯片8被安装并且上侧的半导体芯片8经由导线而与布线板2电气连接。
布线板2在下表面2b侧具有多个焊球5作为外部端子。因此,图22中示出的半导体装置也是BGA12。
在BGA12中,例如,在下侧的半导体芯片1是控制器芯片,而在上侧的半导体芯片8是存储器芯片。因此,它也是在其中在上侧的半导体芯片8由在下侧的半导体芯片1控制的SIP(封装体中系统(system in package))类型半导体装置。然而半导体芯片1与半导体芯片8可以是具有其它功能的半导体芯片。
在上侧的半导体芯片8利用管芯接合材料9在主表面8a向上的状态下被附接到在下侧的半导体芯片1的背面1b上。因此,在下侧的半导体芯片1的背面1b与在上侧的半导体芯片8的背面8b利用管芯接合材料9彼此接合。
在半导体芯片8的主表面8a上的焊盘8c与在布线板2的上表面2a上的接合引线2v经由导线(导电部件)10彼此电气连接。导线10是金导线或者铜导线。
类似于实施例的BGA7,在下侧的半导体芯片1经由诸如多个铜支柱4之类的导电部件而与布线板2的多个接合引线2m倒装芯片连接。利用底部填料6保护这个倒装芯片连接,并且半导体芯片1的背面1b、半导体芯片8、以及多个导线10利用由成型树脂制成的成型部件11而成型。构成成型部件11的成型树脂是例如基于环氧的热固性树脂。
变型示例2的BGA12的布线板2类似于实施例的BGA7的布线板2并且绝缘层2d在其上具有多个接合引线2m。这个绝缘层2d由具有玻璃布(玻璃纤维)2h的预浸料(树脂层)2da和形成(堆叠)在预浸料2da上且不具有玻璃布2h的树脂层2db组成。
因此,每个接合引线2m与树脂层2db接触并且被布置在这个树脂层2db上。这意味着接合引线2m由与预浸料2da相比具有更低硬度的和更软的树脂层2db支撑。
接合引线2m中的每一个在其下方具有较软的树脂层2db,使得类似于实施例的BGA7,即使在负荷在倒装芯片接合时被从铜支柱4施加于接合引线2m上时,由电极的高度变化所引起的应力也可以通过较软的树脂层2db的下沉被吸收,使得它可以减少施加到半导体芯片1的应力。
结果,对半导体芯片1的损伤可以被减少并且诸如半导体芯片1中的裂缝的形成或者表面保护膜的剥落之类的麻烦可以被防止。简而言之,可以减少或者防止在倒装芯片接合中对半导体芯片1的损伤。这使得可以改善半导体装置(BGA12)的可靠性。
BGA12及其制造可得到的其它优点类似于实施例的BGA7,从而省略重复描述。
(变型示例3)
在上述实施例中,使用例如主要由铜(Cu)组成的材料作为将半导体芯片1与布线板2电气连接的柱状的或突出的导电部件来进行描述,但是材料不限于此。作为比铜(Cu)软的材料,例如,可以使用主要由金(Au)组成的材料。
当金(Au)和铜(Cu)比较时,由金制成的导电部件自身容易变形(容易变平),使得布线板2的电极(接合引线2m)不一定由用作支撑布线板2的电极(接合引线2m)的绝缘层的双层绝缘层支撑。换句话说,比不包含玻璃布(玻璃纤维)2h的树脂层更硬的材料(例如,预浸料)能被使用作为支撑布线板2的电极(接合引线2m)的绝缘层。
然而当导电部件或电极(接合引线)的高度极大地变化时,导电部件的变形量(变平量)变大。当不期望导电部件的过度变形时,即使导电部件由主要由金(Au)组成的材料制成,使用具有类似于上述实施例的构造的具有绝缘层的布线板2也是优选的。
(变型示例4)
图23是示出要被并入实施例的变型示例4的半导体装置中的布线板的结构的一个示例的截面图。
变型示例4示出要被并入半导体装置中的布线板的变型示例。图23中示出的布线板2是具有两个布线层的所谓的双层板。它具有在核芯层(预浸料)2e的表面侧的布线层2p和在核芯层2e的背面侧的布线层2q。
同样在图23中示出的布线板2中,在布线层2p中形成的多个接合引线(电极)2m在其下方具有树脂层2db,该树脂层2db具有比具有玻璃布2h的核芯层2e低的硬度。同样在下表面2b侧,其中具有多个连接盘(电极)2n的布线层2q和核芯层2e在其之间具有树脂层2w,该树脂层2w具有比核芯层2e低的硬度。
因此,在变型示例4的布线板2中,绝缘层2d由树脂层2db、核芯层2e和树脂层2w组成。接合引线2m由较软的树脂层(不具有玻璃布的层)2db支撑,而连接盘2n由较软的树脂层(不具有玻璃布的层)2w支撑。
同样在具有根据变型示例4的双层的布线结构的变型示例4的布线板2中,接合引线2m在其下方具有较软的树脂层2db。类似于实施例的BGA7,当在倒装芯片接合时负荷经由接合引线2m被施加到树脂层2db时,发生接合引线2m的下沉和树脂层2db的变形。结果,即使发生铜支柱4的高度变化,所有铜支柱4也可以与接合引线2m连接。这意味着即使具有低高度的铜支柱4也可以与接合引线2m连接。
如上所述,与铜支柱4之中的具有比其它铜支柱4更大的高度的铜支柱连接的布线板2的接合引线2m下沉,使得可以防止在其上形成有具有更大高度的铜支柱4的半导体芯片1的焊盘1c正下方的绝缘层中的裂缝67(参考图26)的形成。这使得可以改善BGA7的可靠性。
此外,即使在应力被施加到半导体装置(BGA7)的焊球5等时,该应力也可以通过较软的树脂层2db被缓和并且可以防止对倒装芯片连接的损伤的直接传播。
简而言之,即使在诸如热应力之类的应力被施加到焊球5时,铜支柱4连接的接合引线2m在其下方具有较软的树脂2db,使得应力可以通过较软的树脂层2db的变形被缓和和吸收,使得防止对倒装芯片连接或半导体芯片1的损伤的直接传播。
结果,可以抑制倒装芯片连接的连接故障的产生。
上述半导体装置及其制造可得到的其它优点类似于实施例的BGA7,从而省略重复描述。
(变型示例5)
关于不包含玻璃布的树脂层2db和2fb与包含玻璃布2h的树脂层(预浸料2da和2fa)之间的位置关系,它们的结构不限于如上面在实施例中所述的堆叠结构。如图24所示,不包含玻璃布的树脂层2db和2fb可以被仅仅提供在柱状的(或突出的)导电部件(铜支柱4)要连接的电极(接合引线2m)正下方。
然而,当考虑布线板2的制造效率(步骤数量)时,优选的是采用如实施例描述的其中层(树脂层)2da、2db、2fa和2fb已经被一个接一个地堆叠的堆叠结构。
(变型示例6)
在上述实施例中,BGA已经被描述为半导体装置的一个示例。然而半导体装置不限于BGA并且可以是在其连接盘的表面上具有导电部件的LGA(平面网格阵列)。
(变型示例7)
此外,变型示例可在不背离上述实施例中描述的技术概念的范围的情况下被组合地使用。
Claims (6)
1.一种制造半导体装置的方法,包括:
(a)提供布线板,所述布线板包括:
第一绝缘层,第一绝缘层包括具有玻璃纤维的第一树脂层和没有玻璃纤维的第二树脂层,第二树脂层形成在第一树脂层上而没有布线层被布置在第一树脂层与第二树脂层之间,
第二绝缘层,第二绝缘层包括具有玻璃纤维的第三树脂层,第二绝缘层基本上由第三树脂层组成,
布线层,布线层被布置在第一绝缘层的第一树脂层与第二绝缘层的第三树脂层之间,使得所述布线层与第一树脂层和第三树脂层接触,在所述布线层与第一树脂层之间以及在所述布线层与第三树脂层之间没有中介层,以及
多个接合引线,所述多个接合引线形成在第二树脂层的第一表面上;
(b)在步骤(a)之后,将半导体芯片经由多个导电部件布置在第二树脂层的第一表面上,使得所述半导体芯片的主表面面对第二树脂层的第一表面,所述半导体芯片具有在所述主表面上形成的多个焊盘、以及与所述主表面相对的背面;以及
(c)在步骤(b)之后,将负载施加到所述半导体芯片的所述背面,由此将所述多个导电部件与所述多个接合引线分别电气连接。
2.根据权利要求1所述的制造半导体装置的方法,其中,第二树脂层具有比第一树脂层的厚度小的厚度。
3.根据权利要求1所述的制造半导体装置的方法,其中,所述多个导电部件中的每一个由包括铜作为主要成分的材料形成。
4.根据权利要求1所述的制造半导体装置的方法,其中,所述多个导电部件中的每一个具有柱状结构。
5.根据权利要求1所述的制造半导体装置的方法,还包括:
分别在所述多个导电部件的端面上形成多个焊料材料。
6.根据权利要求1所述的制造半导体装置的方法,
其中,第二树脂层具有比第一树脂层的厚度小的厚度,以及
其中,第三树脂层具有比第一树脂层的厚度大的厚度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013086899A JP6161380B2 (ja) | 2013-04-17 | 2013-04-17 | 半導体装置の製造方法 |
JP2013-086899 | 2013-04-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104112715A CN104112715A (zh) | 2014-10-22 |
CN104112715B true CN104112715B (zh) | 2018-04-10 |
Family
ID=51709455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410153991.7A Expired - Fee Related CN104112715B (zh) | 2013-04-17 | 2014-04-17 | 半导体装置及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20140312498A1 (zh) |
JP (1) | JP6161380B2 (zh) |
KR (1) | KR20140124725A (zh) |
CN (1) | CN104112715B (zh) |
HK (1) | HK1201990A1 (zh) |
TW (1) | TWI600123B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140019173A (ko) * | 2012-08-06 | 2014-02-14 | 삼성전기주식회사 | 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지 |
TWI489176B (zh) * | 2012-12-14 | 2015-06-21 | Elan Microelectronics Corp | 行動電子裝置的螢幕控制模組及其控制器 |
US20150279775A1 (en) * | 2012-12-14 | 2015-10-01 | Elan Microelectronics Corporation | Screen control module of a mobile electronic device and controller thereof |
JP2015222741A (ja) * | 2014-05-22 | 2015-12-10 | 京セラサーキットソリューションズ株式会社 | 多数個取り配線基板およびその製造方法 |
WO2017051872A1 (ja) * | 2015-09-25 | 2017-03-30 | 積水化学工業株式会社 | 接続構造体の製造方法、導電性粒子、導電フィルム及び接続構造体 |
CN107205310B (zh) * | 2017-06-29 | 2019-12-24 | 惠科股份有限公司 | 一种电路板和显示装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1792126A (zh) * | 2003-05-19 | 2006-06-21 | 大日本印刷株式会社 | 双面布线基板和双面布线基板的制造方法以及多层布线基板 |
CN1812081A (zh) * | 2005-01-20 | 2006-08-02 | 太阳诱电株式会社 | 半导体装置及其安装体 |
CN101593736A (zh) * | 2008-05-28 | 2009-12-02 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
CN101939832A (zh) * | 2007-12-17 | 2011-01-05 | 斯盖沃克斯解决方案公司 | 热机械的倒焊芯片的模片焊接 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07336002A (ja) * | 1994-06-08 | 1995-12-22 | Hitachi Chem Co Ltd | 配線板及びその製造法 |
US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
TW383435B (en) * | 1996-11-01 | 2000-03-01 | Hitachi Chemical Co Ltd | Electronic device |
SG76530A1 (en) * | 1997-03-03 | 2000-11-21 | Hitachi Chemical Co Ltd | Circuit boards using heat resistant resin for adhesive layers |
EP1744609B1 (en) * | 1999-06-02 | 2012-12-12 | Ibiden Co., Ltd. | Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board |
DE10020374A1 (de) * | 1999-07-02 | 2001-01-25 | Fujitsu Ltd | Kopfbaugruppe einer Plattenvorrichtung mit einem Kopf-IC-Chip, der durch Ultraschallbonden an eine Aufhängung montiert ist |
US6965160B2 (en) * | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
JP2004179545A (ja) * | 2002-11-28 | 2004-06-24 | Kyocera Corp | 配線基板 |
KR100834591B1 (ko) * | 2003-05-19 | 2008-06-02 | 다이니폰 인사츠 가부시키가이샤 | 양면 배선기판과, 양면 배선기판 제조방법 및 다층배선기판 |
US7144759B1 (en) * | 2004-04-02 | 2006-12-05 | Celerity Research Pte. Ltd. | Technology partitioning for advanced flip-chip packaging |
US20070230150A1 (en) * | 2005-11-29 | 2007-10-04 | International Business Machines Corporation | Power supply structure for high power circuit packages |
KR101014919B1 (ko) * | 2005-12-01 | 2011-02-15 | 스미토모 베이클리트 컴퍼니 리미티드 | 프리프레그, 프리프레그의 제조 방법, 기판 및 반도체 장치 |
JP4929784B2 (ja) * | 2006-03-27 | 2012-05-09 | 富士通株式会社 | 多層配線基板、半導体装置およびソルダレジスト |
CN102176808B (zh) * | 2007-01-29 | 2014-04-09 | 住友电木株式会社 | 层叠体、基板的制造方法、基板及半导体装置 |
JP2008198747A (ja) * | 2007-02-09 | 2008-08-28 | U-Ai Electronics Corp | プリント基板及びプリント基板の製造方法 |
US7893527B2 (en) * | 2007-07-24 | 2011-02-22 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor plastic package and fabricating method thereof |
US8030752B2 (en) * | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
JP2010041045A (ja) * | 2008-07-09 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP5479233B2 (ja) * | 2010-06-04 | 2014-04-23 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5587123B2 (ja) * | 2010-09-30 | 2014-09-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5715835B2 (ja) * | 2011-01-25 | 2015-05-13 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
JPWO2013161527A1 (ja) * | 2012-04-26 | 2015-12-24 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
TWI488273B (zh) * | 2012-07-18 | 2015-06-11 | Chipbond Technology Corp | 半導體製程及其半導體結構 |
JP5990421B2 (ja) * | 2012-07-20 | 2016-09-14 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体パッケージ |
-
2013
- 2013-04-17 JP JP2013086899A patent/JP6161380B2/ja not_active Expired - Fee Related
-
2014
- 2014-03-30 US US14/229,981 patent/US20140312498A1/en not_active Abandoned
- 2014-04-01 TW TW103112076A patent/TWI600123B/zh not_active IP Right Cessation
- 2014-04-14 KR KR1020140044242A patent/KR20140124725A/ko not_active Application Discontinuation
- 2014-04-17 CN CN201410153991.7A patent/CN104112715B/zh not_active Expired - Fee Related
-
2015
- 2015-03-10 HK HK15102431.6A patent/HK1201990A1/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1792126A (zh) * | 2003-05-19 | 2006-06-21 | 大日本印刷株式会社 | 双面布线基板和双面布线基板的制造方法以及多层布线基板 |
CN1812081A (zh) * | 2005-01-20 | 2006-08-02 | 太阳诱电株式会社 | 半导体装置及其安装体 |
CN101939832A (zh) * | 2007-12-17 | 2011-01-05 | 斯盖沃克斯解决方案公司 | 热机械的倒焊芯片的模片焊接 |
CN101593736A (zh) * | 2008-05-28 | 2009-12-02 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140312498A1 (en) | 2014-10-23 |
TWI600123B (zh) | 2017-09-21 |
CN104112715A (zh) | 2014-10-22 |
KR20140124725A (ko) | 2014-10-27 |
JP6161380B2 (ja) | 2017-07-12 |
TW201507073A (zh) | 2015-02-16 |
HK1201990A1 (zh) | 2015-09-11 |
JP2014212174A (ja) | 2014-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10541213B2 (en) | Backside redistribution layer (RDL) structure | |
CN104112715B (zh) | 半导体装置及其制造方法 | |
US10431556B2 (en) | Semiconductor device including semiconductor chips mounted over both surfaces of substrate | |
US7619305B2 (en) | Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking | |
US7880313B2 (en) | Semiconductor flip chip package having substantially non-collapsible spacer | |
US9105552B2 (en) | Package on package devices and methods of packaging semiconductor dies | |
JP5529371B2 (ja) | 半導体装置及びその製造方法 | |
US11515229B2 (en) | Semiconductor package and manufacturing method thereof | |
US20090045524A1 (en) | Microelectronic package | |
JP5619381B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5301126B2 (ja) | 半導体装置及びその製造方法 | |
TWI555101B (zh) | 封裝結構及其製法 | |
KR100772103B1 (ko) | 적층형 패키지 및 그 제조 방법 | |
CN102751203A (zh) | 半导体封装结构及其制作方法 | |
KR20200014673A (ko) | 반도체 패키지 | |
TWI688058B (zh) | 雙晶片記憶體封裝 | |
KR101363993B1 (ko) | 적층 반도체 패키 | |
JP2012138394A (ja) | 半導体装置の製造方法 | |
KR20210076292A (ko) | 반도체 패키지 | |
CN115966537A (zh) | 桥接芯片、扇出型封装结构以及相应的封装方法 | |
JP5352639B2 (ja) | 半導体装置の製造方法 | |
KR20060075432A (ko) | 스택 패키지 | |
JP2009123923A (ja) | 半導体装置及びその製造方法 | |
JP2014135388A (ja) | 半導体装置の製造方法 | |
KR20100020764A (ko) | 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1201990 Country of ref document: HK |
|
CB02 | Change of applicant information |
Address after: Tokyo, Japan Applicant after: Renesas Electronics Corp. Address before: Kanagawa, Japan Applicant before: Renesas Electronics Corp. |
|
COR | Change of bibliographic data | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180410 |