CN1812081A - 半导体装置及其安装体 - Google Patents

半导体装置及其安装体 Download PDF

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Publication number
CN1812081A
CN1812081A CNA2006100003397A CN200610000339A CN1812081A CN 1812081 A CN1812081 A CN 1812081A CN A2006100003397 A CNA2006100003397 A CN A2006100003397A CN 200610000339 A CN200610000339 A CN 200610000339A CN 1812081 A CN1812081 A CN 1812081A
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Prior art keywords
cylindrical portion
mentioned
semiconductor device
melting point
columnar electrode
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CN100423248C (zh
Inventor
井上泰造
北崎健三
重谷寿士
麦谷英儿
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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Abstract

本发明提供一种具有柱状电极的半导体装置，所述柱状电极具有仅与柱状部的上表面接合的球状的低熔点层。当设各低熔点层(24)的体积为A、各柱状部(22)的上表面的面积为B时，通过调整低熔点层(24)的镀敷量和柱状部(22)的截面面积以满足A≤1.3×B1.5的关系，由此，当低熔点层(24)通过软熔形成球状时，可以防止该低熔点层(24)流淌到柱状部(22)的侧表面。

Description

半导体装置及其安装体
技术领域
本发明涉及半导体装置及其安装体，特别是涉及对减小间距有效的半导体装置及其安装体。
背景技术
随着集成电路小型化需求的逐渐扩大，半导体装置的结构，正如CSP(Chip Size Package)所代表的那样，以非常接近于裸芯片的形态构成并通过反转片式安装将该半导体装置接合到配线基板上的方法日益引人注目。
此处，采用上述倒装芯片安装法的半导体装置与配线基板之间的接合，是通过在构成该半导体装置的半导体基板的主面侧所设置的凸起部来进行的，为了以窄间距而配置所述凸起部，必须减小凸起部的体积，以避免邻接的凸起部相互接触。
但是，如果使凸起部的体积减小，半导体基板和配线基板之间的间隙将变小，所以，很难进行向所述间隙内填充树脂的封装以实现稳定接合和提高或确保连接可靠性的目的。
因此，为了确保上述的间隙，以往曾研究了采用支柱状的金属柱的接合凸起部。作为采用了这种支柱型接合凸起部的半导体装置及其安装方法，已知的有如下的文献：
专利文献1：特开平5-136201号公报
专利文献2：特开2002-313993号公报
专利文献3：美国专利第6,592,019号公报
此处，在上述专利文献1中，如该文献的第0020段和图1所示，公开了一种用引线接合法形成具有金属柱的接合凸起部的方法。
另外，在专利文献2中，如该文献的第0002～0007段和图18～图24所示，公开了一种用电镀法形成金属柱、同时在该金属柱的上表面上具有焊珠的接合凸起部的形成方法。
另外，在专利文献3中，如该文献的第7栏第16行～第54行和图1～图3所示，公开了用电镀法形成金属柱以及在其上表面上形成焊锡层并使该焊锡层以原有的状态与配线基板接合的方法、和通过软熔使该焊锡层暂时变为球状后使之与配线基板接合的方法。
但是，在上述专利文献1所公开的方法中，必须在每个端子上形成引线凸起部，因此很难适用于输入输出端子较多的半导体装置，同时很难使各凸起部的高度均匀齐平，因而可以认为，很难将该方法应用于近年来的多引线窄间距型的半导体装置。
另外，在上述专利文献2所公开的方法中，如该文献的第0007段和图22所示，由于产生被树脂覆盖金属柱的上表面的过程，因此在形成焊珠之前必须将金属柱研磨成图23所示的状态，同时，由于是在将该金属柱埋设在树脂内的状态下构成半导体装置，所以，存在着不能确保封装的间隙的课题。
另一方面，在上述专利文献3所公开的方法中，由于用电镀法形成金属柱和焊锡层，并在使该金属柱露出的状态下安装在配线基板上，因此，在使各凸起部的高度均匀化和确保封装间隙方面，可以认为该方法是非常优异的方法。
但是，在该专利文献3中，如该文献的第7栏第47行～第53行所示，没有提及把在金属柱的上表面上形成的焊锡层暂时软熔而形成焊珠时产生的各种问题，所以为了在金属柱上形成精度较高的焊珠，尚需要进行进一步的研究。
因此，本发明的目的在于，提供一种对形成接合凸起部有效的半导体装置及其安装体，其中在所述接合凸起部的柱状部的上表面具有焊珠。
发明内容
为达到上述目的，本发明的第1技术方案为，半导体装置具有多个被设置在半导体基板上的柱状电极，所述半导体装置的特征在于：上述柱状电极具有柱状部和金属球部，所述柱状部由导电材料构成；所述金属球部由熔点比上述柱状部低的导电材料形成，并被接合在上述柱状部的上表面上；当设上述金属球部的体积为A、上述柱状部的上表面的面积为B、在上述柱状部的上表面上形成的起伏部的体积为E时，上述柱状电极具有A-E≤1.3×B1.5的关系。
如上所述，通过以柱状部的上表面面积与在上表面上形成的起伏部之间的关系将金属球部的体积限定在规定的体积以下，使金属球部与柱状部之间的接触面上产生的张力大于施加于金属球部的重力，因此，在低熔点材料通过软熔形成金属球部之际，可以防止该低熔点材料向柱状部的侧表面流淌。
此处，所谓的在柱状部的上表面上形成的起伏部，是指在该柱状部的上端部分划出1条以直角的角度与柱状部的侧表面相交的水平线时从该水平线突出的起伏部分。这样的起伏部分有时在电镀工序中是自然形成的，有时是人为地形成的，通过设定该起伏部分的体积，可以防止低熔点材料向柱状部的侧表面流淌。
当采用这些结构时，上述的柱状部的上表面面积B，可以按其与低熔点层相接触的部分的表面积来考虑。因此，如采用这些结构，能使低熔点层和柱状部之间的接触面积加大，因此可以使低熔点层的体积增加。
其结果是，由于可以使各柱状电极的高度均匀齐平，所以，可以实现这样的结构，即，使各电极相对于配线基板的接合精度提高，同时既能确保封装间隙又能使电极间距尽可能地狭小。
此外，根据本方法，可以形成仅与柱状部的上表面相接合的金属球部而无需对柱状部进行额外的侧表面处理，因此能以简易的结构来构成具有较高可靠性的柱状电极的半导体装置。此外，本发明并不排除对柱状部进行侧表面处理，为了更可靠地防止低熔点材料流淌到柱状部的侧表面，也可以对柱状部进行侧表面处理。
此处，柱状部最好用像铜那样的电阻率较低而熔点高的材料形成，金属球部最好用像焊锡那样的熔点较低且与构成柱状部的材料亲合性良好的材料形成。此外，柱状部也可以用镍、铝、钛等导电材料形成。
另外，本发明的第2技术方案所述的半导体装置为第1技术方案所述的半导体装置，其特征在于，当设上述各柱状电极间的间距的1/2为C、上述金属球部的高度为D时，上述各柱状电极具有D≤C的关系。
这样，通过进一步限定柱状电极的间距和金属球部的高度之间的关系，在将本半导体装置安装到配线基板之际进行软熔时，可以避免邻接的柱状电极间的相互接触。
另外，本发明的第3技术方案为半导体装置的安装体，所述半导体装置具有多个被设置在半导体基板上的柱状电极，上述的设有多个柱状电极的半导体装置通过所述各柱状电极安装在配线基板上，所述半导体装置的安装体的特征在于：上述柱状电极具有柱状部和金属层，所述柱状部由导电材料构成；所述金属层由熔点比上述柱状部低的导电材料形成，并被接合在上述柱状部的上表面上；当设上述低熔点金属层的体积为A，上述柱状部的上表面的面积为B，在上述柱状部的上表面上形成的起伏部的体积为E时，上述柱状电极具有A-E≤1.3×B1.5的关系。
如上所述，通过由柱状部的上表面的面积和在上表面上形成的起伏部之间的关系将金属球部的体积限定在规定的体积以下，可以在防止了低熔点金属向柱状部的侧表面流淌的状态下将半导体装置安装在配线基板上，因此，可以使各柱状电极的高度均匀齐平，其结果是，由于可以使各柱状电极的高度均匀齐平，所以，可以实现这样的结构，即，使各电极相对于配线基板的接合精度提高，同时既能确保封装间隙又能使电极间距尽可能地狭小。
另外，本发明的第4技术方案为根据技术方案3所述的半导体装置，其特征在于：在上述半导体装置和上述配线基板之间，具有以直接与上述柱状部的侧表面相接触的状态进行了填充的封装部。
通过采用这种结构，可以在适当地确保封装间隙的状态下进行半导体装置的窄间距安装。
另外，本发明的第5技术方案为一种半导体装置，其具有多个被设置在半导体基板上的柱状电极，所述半导体装置的特征在于：上述柱状电极具有第1和第2柱状部以及金属球部，所述第1和第2柱状部由导电材料构成；所述金属球部由熔点比上述柱状部低的导电材料形成并被接合在上述第2柱状部的上表面上；上述第2柱状部具有直径小于上述第1柱状部直径的部位，并介于上述金属球部和上述第1柱状部之间。
如上所述，通过将直径较小的柱状部配置在直径较大的柱状部上，同时将金属球部设置在直径较小的柱状部上，在低熔点材料通过软熔形成金属球部之际，至少可以防止该低熔点材料向直径较大的柱状部的侧表面流淌。
其结果是，即使低熔点材料流淌到直径小的柱状部的侧表面，也能使流淌停止在直径大的柱状部的上表面上，因此，可以使各柱状电极的高度均匀齐平，使各电极相对于配线基板的接合精度提高，同时既能确保封装间隙又能使电极间距尽可能地狭小。
此外，根据本方法，可以形成仅与柱状部的上表面相接合的金属球部而无需对柱状部进行额外的侧表面处理，因此能以简易的结构来构成具有较高可靠性的柱状电极的半导体装置。此外，本发明并不排除对柱状部进行侧表面处理，为了更可靠地防止低熔点材料流淌到柱状部的侧表面，也可以对柱状部进行侧表面处理，并且为了获得更可靠的防止流淌效果，对侧表面进行防止流淌处理是有效的。
另外，如上所述，通过以第1和第2这两段来形成柱状部，在用电镀法形成柱状部之际，可以缓和设置在抗蚀剂(resist)上的开口部的长宽比，因此能形成可以被配置在更窄间距中的电极。
如上所述，根据本发明，可以形成具有仅与柱状部的上表面接合的球部的柱状电极。
附图说明
图1是表示本发明第1实施方式的半导体装置的安装结构的剖视图。
图2是表示第1实施方式的半导体装置的第1制造工序的剖视图。
图3是表示第1实施方式的半导体装置的第2制造工序的剖视图。
图4是表示第1实施方式的半导体装置的第3制造工序的剖视图。
图5是表示第1实施方式的半导体装置的第1安装工序的剖视图。
图6是表示第1实施方式的半导体装置的第2安装工序的剖视图。
图7是表示第1实施方式的半导体装置的另一种安装结构的剖视图。
图8是表示连接可靠性较低的柱状电极的状态的剖视图。
图9是表示图4中所示的低熔点层的体积和柱状部的上表面面积之间的关系的剖视图。
图10是表示形成了柱状电极的晶片的软熔工序的侧表面图。
图11是表示按图10的工序形成的半导体装置的电极结构的剖视图。
图12是表示对低熔点层的体积A和柱状部的上表面面积B之间的关系进行了检验时的结果的表。
图13是表示柱状电极的适当的结构例的剖视图。
图14是表示本发明第2实施方式的半导体装置的安装结构的剖视图。
图15是表示第2实施方式的半导体装置的第1制造工序的剖视图。
图16是表示第2实施方式的半导体装置的第2制造工序的剖视图。
图17是表示第2实施方式的半导体装置的第3制造工序的剖视图。
图18是表示第2实施方式的半导体装置的第4制造工序的剖视图。
图19是表示第2实施方式的半导体装置的第1安装工序的剖视图。
图20是表示第2实施方式的半导体装置的第2安装工序的剖视图。
图21是表示第2实施方式的半导体装置的另一种安装结构的剖视图。
图22是表示连接可靠性较低的柱状电极的状态的剖视图。
图23是表示使用了截面为梯形的柱状部时的实施方式的剖视图。
图24是表示对使用了贯通通路的半导体基板的安装例的剖视图。
图25是表示接合到被设置在半导体基板上的电极图案上的例的剖视图。
具体实施方式
以下参照附图，详细地对本发明的实施方式进行说明。此外，本发明并不局限于以下说明的实施方式，而是可以适当地进行变更的。
图1是表示本发明第1实施方式的半导体装置的安装结构的剖视图，如该图所示，本安装结构，是具有将半导体装置10通过柱状电极20安装在配线基板30上的结构的。
半导体装置10包括由硅构成的半导体基板12、在该半导体基板12的主面侧所设置的多个铝电极垫14、和在使该各电极垫14部分地露出的状态下形成的钝化膜16。
柱状电极20包括分别在上述各电极垫14的露出部上形成的由铜构成的柱状部22、和在该柱状部22的上表面上形成的由焊锡构成的低熔点层24。此外，该柱状部最好是以15μm以上的高度形成。
配线基板30由在内层有各种图案的多层基板32、和在该多层基板32的表面上形成的配线图案34构成。
半导体装置10和配线基板30之间的电接合，是通过将位于柱状电极20的前端部的低熔点层24熔融在配线图案34上进行的，在该半导体装置10和配线基板30之间实施封装40，以保护各柱状电极20的接合状态。
图2是表示第1实施方式的半导体装置的第1制造工序的剖视图。当制造本实施方式的半导体装置时，首先，如该图(a)所示，在形成了多个集成电路的晶片13的主面侧，形成多个电极垫14，并在使该各电极垫14的中央部露出的状态下形成钝化膜16。
接着，如该图(b)所示，在钝化膜16上涂敷光致抗蚀剂42，然后，如该图(c)所示，使光致抗蚀剂42与各电极垫14的露出部对应地感光，形成使各电极垫14露出的开口部44。此处，使各开口部44的宽度为比钝化膜16的开口宽度窄的宽度，而且，在不与钝化膜16的端部接触的状态下形成各开口部44。
图3是表示第1实施方式的半导体装置的第2制造工序的剖视图。如该图(a)所示，利用前图中所示的开口部44，在电极垫14上形成柱状部22。该柱状部22的形成是通过镀铜进行的。
接着，如该图(b)所示，利用前图中所示的开口部44，在柱状部22的上表面上形成低熔点层24。此低熔点层24的形成，是通过镀焊锡进行的。
图4是表示第1实施方式的半导体装置的第3制造工序的剖视图。如该图(a)所示，将前图中所示的光致抗蚀剂42除去后，得到在晶片13上形成的多个柱状电极20。然后，如该图(b)所示，通过将低熔点层24加热熔融，将该低熔点层24加工成球状。此加热熔融处理，是通过将晶片13置入软熔炉内并按预定的温度和时间实施加热处理进行的。此外，在软熔之前先涂敷氧化膜除去剂。
图5是表示第1实施方式的半导体装置的第1安装工序的剖视图。如该图所示，在将经过以上说明的一系列工序制成的半导体装置10向配线基板30上安装时，使该半导体装置10的主面侧朝向配线基板30，并将位于柱状电极20的前端的球状的低熔点层24与配线基板30上所设置的配线图案的位置对准。
图6是表示第1实施方式的半导体装置的第2安装工序的剖视图。如该图所示，将在前图所示的工序中已对准了位置的半导体装置10安装在配线基板30上，然后，进行软熔而将低熔点层24熔融固定在配线图案34上。在使各低熔点层24的固定完成后，从由该图中的箭头A指示的方向填充封装树脂，从而得到图1中所示的结构。
图7是表示第1实施方式的半导体装置的另一种安装结构的剖视图。如该图所示，只要是在半导体装置10已被安装在配线基板30上以后，其状态也可以是柱状部22的前端埋设在低熔点层24内的状态。
图8是表示连接可靠性较低的柱状电极的状态的剖视图。如该图(a)所示，当球状的低熔点层24在其与柱状部22的侧表面相接触的状态下被形成时，在各柱状电极20的高度上将产生偏差，其结果是，如该图(b)所示，将产生没有与配线图案34相接合的柱状电极。
为防止产生这种状态，在本实施方式中，在图4所示的形成球状的低熔点层24的工序中，采用如下所述的方法。
图9是表示图4中所示的低熔点层的体积和柱状部的上表面面积之间的关系的剖视图。如该图所示，当设各低熔点层24的体积为A、各柱状部22的上表面的面积为B时，为了满足A≤1.3×B1.5的关系，在上述的用图2和图3已说明的工序中，通过调整开口部44的截面面积和低熔点层24的镀敷量来形成各柱状电极20。
图10是表示形成了柱状电极的晶片的软熔工序的侧表面图。如该图所示，在按上述关系形成了各柱状电极20之后，将已形成了所述各柱状电极20的晶片13的背面侧放置在晶片支承台52上，并以使低熔点层24朝上的状态将该晶片13设置在软熔炉50内。
然后，当在该状态下对低熔点层24进行加热时，虽然向下的重力施加在已熔融的低熔点层24上，但是，因为低熔点层24与柱状部22的上表面面积之间的关系控制着低熔点层24的量，所以，低熔点层24在其不与柱状部22的侧表面相接触的状态下被加工成球状。
图11是表示按图10的工序形成的半导体装置的电极结构的剖视图。如该图所示，当设各低熔点层24的体积为A、各柱状部22的上表面的面积为B时，经过了图10所示的工序的半导体装置10的各柱状电极20，是在满足A≤1.3×B1.5的关系的状态下被形成的，而且，当设各柱状电极22的间距的1/2为C、球状的低熔点层24的高度为D时，上述各柱状电极，具有D≤C的关系。
图12是表示对低熔点层的体积A和柱状部的上表面面积B之间的关系进行了检验时的结果的表。如该图所示，通过改变A和B的值，对低熔点层相对于柱状部侧表面的流淌状况进行了评价，评价结果是，虽然确认了在第1～3条件下可以在不流淌到柱状部侧表面的状态下形成球部，但在第4和第5条件下发生了向侧表面的流淌。图13是表示柱状电极的适当的结构例的剖视图。关于上述的柱状电极，可以采用将柱状电极22的上表面形成为如图(a)所示的上表面山型的结构，也可以采用如图(b)所示的具有起伏的结构，或者如图(c)所示的在中央部具有凸部的结构、如图(d)所示的将上表面部分加宽了的结构、如图(e)所示的以弯曲型形成的结构。
另外，如图(a)、(b)、(c)、(d)、(e)所示，当使柱状电极20的上表面具有山形、起伏、凸部时，若设该图(a)、(b)、(c)、(e)中所示的虚线E′以上的体积为E，则在满足A-E≤1.3×B1.5的关系的状态下形成柱状电极20。此虚线是将以直角的角度与柱状部的侧表面相交的水平线划在该柱状部的上端部分上而得到的线，从该水平线凸起的起伏部分的体积即为E。这种起伏部分有时是通过电镀工序自然形成的，有时是人为地形成的，通过设定该起伏部分的体积，可以防止低熔点材料流淌到柱状部的侧表面。
当采用这些结构时，上述的柱状部22的上表面面积B，可以按其与低熔点层24接触的部分的表面积来考虑。因此，如采用这些结构，能使低熔点层24和柱状部22的接触面积加大，故可以增加低熔点层的体积。
图14是表示本发明第2实施方式的半导体装置的安装结构的剖视图。如该图所示，本安装结构，是具有将半导体装置10通过柱状电极20安装在配线基板30上的结构的。
半导体装置10包括由Si、GaAs、GaN、SiGe等构成的半导体基板12、在该半导体基板12的主面侧所设置的多个铝电极垫14、和在使所述各电极垫14部分地露出的状态下形成的钝化膜16。
柱状电极20包括分别在上述各电极垫14的露出部上形成的由铜、镍、导电膏剂等高熔点材料构成的柱状部22-1和22-2、和在该柱状部22的上表面上形成的由焊锡等构成的低熔点层24。此外，该柱状部最好以15μm以上的高度形成。
此处，以直径互不相同的形状来形成柱状部22-1和22-2，通过将此两种不同形状的主状部22-1和22-2相互重叠构成一个柱状部。柱状部22-2具有比柱状部22-1较小的外径，低熔点层24被设置在此直径较小的表面上。即，将柱状部由若干段来构成，通过沿着从半导体基板12到低熔点金属层24的方向将柱状部的直径做成分段地或连续地减小的结构，在通过软熔等方式形成球状的低熔点金属层24时，可以防止低熔点金属层24流淌到柱状部的侧表面上。
配线基板30由在内层有各种图案的多层基板32、和在该多层基板32的表面上形成的配线图案34构成。
半导体装置10和配线基板30的电接合，是通过将位于柱状电极20的前端部的低熔点层24熔融在配线图案34上进行的，在该半导体装置10和配线基板30之间实施封装40，以保护各柱状电极20的接合状态。
图15是表示第2实施方式的半导体装置的第1制造工序的剖视图。在制造本实施方式的半导体装置时，首先，如该图(a)所示，在形成了多个集成电路的晶片13的主面侧形成多个电极垫14，并在使该各电极垫14的中央部露出的状态下形成钝化膜16。
接着，如该图(b)所示，在钝化膜16上涂敷光致抗蚀剂42-1，然后，如该图(c)所示，使光致抗蚀剂42-1与各电极垫14的露出部对应地感光，形成使各电极垫14露出的开口部44。此处，使各开口部44的宽度为比钝化膜16的开口宽度窄的宽度，而且，最好在不与钝化膜16的端部相接触的状态下形成各开口部44，但各开口部44的宽度也可以形成得比钝化膜16的开口宽度宽。
图16是表示第2实施方式的半导体装置的第2制造工序的剖视图。如该图(a)所示，利用前图中所示的开口部44，在电极垫14上形成柱状部22-1。该柱状部22-1的形成，是通过镀铜、或镀镍、或用印刷法填充导电性膏剂进行的。
接着，如该图(b)所示，在光致抗蚀剂42-1上涂敷光致抗蚀剂42-2，然后，如该图(c)所示，使光致抗蚀剂42-2与各柱状部22-1的露出部对应地感光，形成使各柱状部22-1露出的开口部44。此处，使各开口部44的宽度为比各柱状部22-1的开口宽度窄的宽度，
图17是表示第2实施方式的半导体装置的第3制造工序的剖视图。如该图(a)所示，利用前图中所示的开口部44，在柱状部22-1上形成柱状部22-2。该柱状部22-2的形成，是通过镀铜、或镀镍、或用印刷法填充导电性膏剂进行的。
接着，如该图(b)所示，利用该图(a)中所示的开口部44，在柱状部22-2的上表面上形成低熔点层24。此低熔点层24的形成，通过镀焊锡进行。
图18是表示第2实施方式的半导体装置的第4制造工序的剖视图。如该图(a)所示，将前图中所示的光致抗蚀剂42-1和42-2除去后，得到在晶片13上形成的多个柱状电极20。然后，如该图(b)所示，通过将低熔点层24加热熔融，将该低熔点层24加工为球状。此加热熔融处理，通过将晶片13置入软熔炉内并按预定的温度和时间实施加热处理进行。此外，在软熔之前先涂敷氧化膜除去剂。
图19是表示第2实施方式的半导体装置的第1安装工序的剖视图。如该图所示，在将经过以上已说明的一系列工序制成的半导体装置10向配线基板30上安装时，使该半导体装置10的主面侧朝向配线基板30，并将位于柱状电极20-2的前端的球状的低熔点层24与配线基板30上所设置的配线图案的位置对准。
图20是表示第2实施方式的半导体装置的第2安装工序的剖视图。如该图所示，将在前图所示的工序中已对准了位置的半导体装置10安装在配线基板30上，然后，进行软熔而将低熔点层24熔融固定在配线图案34上。在使各低熔点层24的固定完成后，从由该图中的箭头A指示的方向填充封装树脂，从而得到图14中所示的结构。
图21是表示第2实施方式的半导体装置的另一种安装结构的剖视图。如该图所示，只要是在半导体装置10已被安装在配线基板30上以后，也可以是柱状部22的前端埋设在低熔点层24内的状态。
图22是表示连接可靠性较低的柱状电极的状态的剖视图。如该图(a)所示，当球状的低熔点层24在其与柱状部22的侧表面相接触的状态下形成时，在各柱状电极20的高度上将产生偏差，其结果是，如该图(b)所示，将产生没有与配线图案34相接合的柱状电极。
为防止产生这种状态，在本实施方式中，如图18所示，在柱状部设置直径不同的部位，因此，在形成球状的低熔点层24的工序中，当该低熔点层24熔融时，至少可以防止该低熔点层24流淌扩散到柱状部22-1的侧表面。
图23是表示使用了截面为梯形的柱状部时的实施方式的剖视图。如该图所示，也可以采用靠低熔点层24一侧的直径较小、靠半导体基板12一侧的直径较大的截面为梯形的柱状部22来构成柱状电极20。根据这种结构，当低熔点层24熔融时，可以防止该低熔点层24流淌扩散到柱状部22的侧表面。
图24是表示对使用了贯通通路的半导体基板的安装例的剖视图。如该图所示，也可以采用在贯通于半导体基板12-2的内外的贯通通路51上形成电极垫14-2并在该电极垫上接合低熔点层24的结构。此处，贯通通路51是通过向形成在半导体基板12-2的内部的贯通孔内填充铜或导电膏剂形成的。
图25是表示接合到被设置在半导体基板上的电极图案上的例的剖视图。如该图所示，也可以采用在半导体基板的主面上形成电极垫14-2，然后在已形成的电极垫14-2上形成配线图案34并在该配线图案34上接合低熔点层24的结构。
根据本发明的半导体装置的结构，由于可以形成具有仅被接合在柱状部的上表面上的球状低熔点层的柱状电极，因此，有望应用于更小型的要求具有较窄间距的半导体装置。

Claims (5)

1.一种半导体装置，具有多个被设置在半导体基板上的柱状电极，所述半导体装置的特征在于：
上述柱状电极具有柱状部和金属球部，所述柱状部由导电材料构成；所述金属球部由熔点比上述柱状部低的导电材料形成，并被接合在上述柱状部的上表面上；
当设上述金属球部的体积为A、上述柱状部的上表面的面积为B、在上述柱状部的上表面上形成的起伏部的体积为E时，上述柱状电极具有A-E≤1.3×B1.5的关系。
2.根据权利要求1所述的半导体装置，其特征在于：
当设上述各柱状电极间的间距的1/2为C、上述金属球部的高度为D时，上述各柱状电极具有D≤C的关系。
3.一种半导体装置的安装体，所述半导体装置具有多个被设置在半导体基板上的柱状电极，上述的设有多个柱状电极的半导体装置通过所述各柱状电极安装在配线基板上，
所述半导体装置的安装体的特征在于：
上述柱状电极具有柱状部和金属层，所述柱状部由导电材料构成；所述金属层由熔点比上述柱状部低的导电材料形成，并被接合在上述柱状部的上表面上；
当设上述低熔点金属层的体积为A，上述柱状部的上表面的面积为B，在上述柱状部的上表面上形成的起伏部的体积为E时，上述柱状电极具有A-E≤1.3×B1.5的关系。
4.根据权利要求3所述的半导体装置，其特征在于：
在上述半导体装置和上述配线基板之间，具有以直接与上述柱状部的侧表面相接触的状态进行了填充的封装部。
5.一种半导体装置，具有多个被设置在半导体基板上的柱状电极，所述半导体装置的特征在于：
上述柱状电极具有第1和第2柱状部以及金属球部，所述第1和第2柱状部由导电材料构成；所述金属球部由熔点比上述柱状部低的导电材料形成并被接合在上述第2柱状部的上表面上；
上述第2柱状部具有直径小于上述第1柱状部直径的部位，并介于上述金属球部和上述第1柱状部之间。
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