CN1208820C - 半导体晶片、半导体装置及其制造方法 - Google Patents

半导体晶片、半导体装置及其制造方法 Download PDF

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CN1208820C
CN1208820C CNB021282714A CN02128271A CN1208820C CN 1208820 C CN1208820 C CN 1208820C CN B021282714 A CNB021282714 A CN B021282714A CN 02128271 A CN02128271 A CN 02128271A CN 1208820 C CN1208820 C CN 1208820C
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semiconductor chip
semiconductor
electronic pads
zone
projected electrode
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CN1405867A (zh
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长尾浩一
藤本博昭
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

一种半导体晶片(15)，形成有用第一分离线(16)划分的多个整体芯片区域(17)。在区域(17)上形成了集成电路、电极垫(18)、探测垫(19)，第二分离线(20)通过集成电路以及电极垫(18)与探测垫(19)之间。第二分离线(20)把区域(17)分离为成为半导体芯片的半导体芯片区域(17a)、第一分离线(16)和第二分离线(20)之间的切断区域(17b)。在此，第二分离线(20)是假想线，实际上不会在半导体晶片(15)上形成。几个探测垫(19)通过横切第二分离线(20)的布线(21)与电极垫(18)相连。

Description

半导体晶片、半导体装置及其制造方法
技术领域
本发明涉及一种通过倒装片接合把在上表面上分别形成了半导体集成电路的两个半导体芯片彼此接合后，形成的COC(Chip On Chip)型半导体装置。
背景技术
近年，为了谋求设置了集成电路的半导体装置的低成本化、小型化以及高性能化(高速化、低耗电化)，进行了各种尝试。例如，提出了通过倒装片接合，把设置了具有不同功能的LSI或由不同工艺形成的LSI的两个半导体芯片彼此接合、形成的COC型半导体装置。
下面，说明通过倒装片接合把两个半导体芯片彼此接合的以往的半导体装置及其制造方法。
图11(a)是表示了具有成为以往的半导体装置上搭载的半导体芯片的多个半导体芯片区域的半导体晶片的模式图。图11(b)是放大表示了图11(a)的半导体晶片的上表面的俯视图。
如图11(a)和11(b)所示，多个半导体芯片区域2形成在半导体晶片1上。各半导体芯片区域2由分离线3划分，多个电极垫4形成在各半导体芯片区域2上。通过沿着分离线3切断各半导体芯片区域2，就变成了搭载在以往的半导体装置上的半导体芯片。
这里，形成在半导体芯片区域2上的电极垫4既作为用于进行与外部电连接的外部电极垫使用，也作为用于进行各半导体芯片的电检查的探测垫使用。即一个电极垫兼做外部电极垫和检查电极垫。须指出的是，在各半导体芯片区域2的表面上只图示了电极垫4，省略了其它的布线等的图示。
图12(a)是表示从以往的具有的半导体装置的半导体晶片1切出的半导体芯片2a和其它的半导体芯片5的模式图，图12(b)是以往的半导体装置的剖视图。
如图12(a)和12(b)所示，在半导体芯片5的上表面上形成了在电极垫8上形成的突起电极6和外部电极垫7。另外，突起电极9形成在半导体芯片2a的上表面上的电极垫4上。在以往的半导体装置200中，通过连接突起电极6和突起电极9，用倒装片接合把半导体芯片5和半导体芯片2a接合在一起。这时如图12(a)所示，半导体芯片2a搭载在半导体芯片5的上表面上的用虚线表示的区域上。
如图12(b)所示，在以往的半导体装置200中，绝缘性树脂10填充在半导体芯片5和半导体芯片2a之间。另外，半导体芯片5固定在导线框架的冲模垫11上。半导体芯片5的外部电极垫7和导线框架的内部引线12通过金属细线13电连接。用密封树脂14密封了半导体芯片5、半导体芯片2a、冲模垫11、内部引线12和金属细线13。
下面，说明以往的半导体装置200的制造方法。
首先，在半导体芯片5上的中央部涂抹绝缘性树脂。接着，把半导体芯片2a压在半导体芯片5上，连接半导体芯片5的突起电极6和半导体芯片2a的突起电极9。须指出的是，也可以在通过倒装片接合连接了半导体芯片5和半导体芯片2a后，注入绝缘性树脂。
接着，通过金属细线13连接了半导体芯片5的外部电极垫7和导线框架的内部引线12后，用密封树脂14密封半导体芯片2a、半导体芯片5、冲模垫11、内部引线12和金属细线13。接着，通过形成从密封树脂14伸出的导线框架的外部引线，得到半导体装置200。
可是，在以往的半导体装置200中，有必要在搭载了半导体芯片2a的半导体芯片5的周围设置用于连接金属细线13的外部电极垫7。并且，如图12(a)所示，设置了外部电极垫7的位置要处在搭载了半导体芯片2a的区域S的外侧。因此，必须使半导体芯片5的尺寸大于半导体芯片2a的尺寸。
因此，通过缩小半导体芯片2a的尺寸，缩小半导体芯片5的尺寸，结果，缩小半导体装置的尺寸。可是，因为以下描述的事实，很难缩小半导体芯片2a的尺寸。
形成在半导体晶片1上的半导体芯片区域2在基于探测的电检查之后，只有合格品才被留下。接着，用倒装片接合把通过分离留下的半导体芯片区域2得到的半导体芯片2a接合到半导体芯片5上。
为了进行基于探测的电检查，就需要探测垫，半导体芯片区域2(半导体芯片2a)的几个电极垫4就成为探测垫。探测针在接触探测垫即电极垫4后，有时会滑动。因此，为了使探测针准确地接触探测垫即电极垫4，有必要以比一边为70μm以上的正方形还大的尺寸形成探测垫即电极垫4。因此，半导体芯片2a的尺寸必然变大。因此，很难减小半导体芯片2a的尺寸。
另外，伴随着半导体装置的高性能化(高速化、低耗电化)，由于在半导体芯片区域2(半导体芯片2a)内形成探测垫，所以无法忽略探测垫、电极垫、电极垫的保护电路、突起电极和布线的各静电电容和电感等的影响。
本发明的半导体装置是为了解决所述问题而提出的，其目的在于提供小型、高性能的半导体装置。
发明内容
本发明的半导体晶片具有：分别成为半导体芯片的多个半导体芯片区域和用于把所述多个半导体芯片区域分离为各半导体芯片的切断区域；在所述多个半导体芯片区域上设置了集成电路和连接在所述集成电路上的电极垫；在所述切断区域上设置了连接在所述电极垫上的探测垫。
本发明的半导体晶片中，通过使探测针接触探测垫，检查了半导体晶片后，通过切断，能除去形成了检查后变为不要的探测垫的切断区域。因此，成为半导体芯片的半导体芯片区域的尺寸变小了。因此，根据本发明，得到了比从以往的半导体晶片得到的半导体芯片更小型的半导体芯片。另外，因为得到的半导体芯片中，通过切断除去了探测垫，所以没有必要考虑探测垫的静电电容和电感。因此，本发明的半导体芯片的电极垫等的布线的静电电容和电感比以往的半导体芯片的电极垫等的布线的静电电容和电感小。
可以采用在所述半导体芯片区域的每一个区域上形成的所述电极垫的个数比连接在所述电极垫上的所述探测垫的个数多的结构。
可以采用在所述半导体芯片区域上分别形成的所述电极垫的间隔比连接在所述电极垫上的所述探测垫的间隔小的结构。
由此，能使检查时探测针滑动的方向的探测垫的形状变长。因此，能更准确地进行检查。
可以采用在所述半导体芯片区域的每一个区域上形成的所述电极垫的尺寸比连接在所述电极垫上的所述探测垫的尺寸小的结构。
可以采用沿着所述的半导体芯片区域的一边、两边或三边形成了连接在所述电极垫上的所述探测垫的结构。
所述探测垫的保护电路也可以设置在所述切断区域上。
连接在形成在所述半导体芯片区域的每一个区域上的所述电极垫上的布线最好是用比连接在所述探测垫上的布线更下层的布线层形成的。
由此，能缩短从内部电路到电极垫的布线长度。因此，能降低布线电容。
本发明的半导体装置具有：具有第一集成电路、连接在所述第一集成电路上的第一电极垫、形成在所述第一电极垫上的第一突起电极的第一半导体芯片和具有第二集成电路、连接在所述第二集成电路上的第二电极垫、形成在所述第二电极垫上的第二突起电极的第二半导体芯片；在所述第一半导体芯片的侧端面上，连接在所述第一电极垫上的检查用布线的切断面露出；所述第一突起电极和所述第二突起电极电连接。
根据本发明，在第一半导体芯片中，通过切断除去检查后变为不要的检查用布线，设置了检查用布线的区域也被除去。因此，第一半导体芯片的尺寸比以往的半导体芯片小。因此，能得到比以往的半导体装置小型的半导体装置。另外，因为在第一半导体芯片中，通过切断除去了检查用布线，所以没必要考虑检查用布线的静电容量和电感。因此，本发明的半导体装置的电极垫等布线的静电电容和电感比以往的半导体装置的电极垫等的布线的静电电容和电感小。
根据本发明，能采用在所述第一半导体芯片上不设置探测垫的结构。
在所述第二半导体芯片的周边部上可以形成用于与外部电路相连的外部电极垫。
在所述第一半导体芯片和所述第二半导体芯片之间可以存在绝缘性树脂。
可以通过密封树脂密封了所述第一半导体芯片和所述第二半导体芯片。
本发明的半导体装置的制造方法，包含以下工序：准备具有分别成为第一半导体芯片的多个第一半导体芯片区域和用于把所述多个第一半导体芯片区域分离为各第一半导体芯片的切断区域，并且在所述第一半导体芯片区域上设置了第一集成电路和连接在所述第一集成电路上的第一电极垫，在所述切断区域上设置了连接在所述第一电极垫上的探测垫的第一半导体晶片的工序(a)；使探测针接触所述探测垫，进行所述多个第一半导体芯片的检查的工序(b)；在所述第一电极垫上形成第一突起电极的工序(c)；通过除去所述第一半导体晶片的所述切断区域，从所述多个第一半导体芯片区域形成多个第一半导体芯片的工序(d)；准备具有第二集成电路和连接在所述第二集成电路上的第二电极垫，并且具有分别成为第二半导体芯片的多个第二半导体芯片区域的第二半导体晶片的工序(e)；在所述第二半导体芯片区域的每一个区域上形成了所述第二电极垫上形成第二突起电极的工序(f)；通过加热和加压，电连接所述第一突起电极和所述第二突起电极的工序(g)；把所述第二半导体晶片按所述多个第二半导体芯片区域切断的工序(h)。
根据本发明，在第一半导体芯片中，通过切断，除去检查后变为不要的探测垫。因此，第一半导体芯片的尺寸比以往的半导体芯片小。因此，能得到比以往的半导体装置小型的半导体装置。另外，因为第一半导体芯片通过切断出除去了探测垫，所以在得到的半导体装置中，没必要考虑探测垫的静电电容和电感。因此，根据本发明，得到了电极垫等的布线的静电电容和电感比以往的半导体装置的电极垫等的布线的静电电容和电感小的半导体装置。
在所述工序(g)中，可以向所述第一半导体芯片和所述第二半导体芯片之间提供绝缘性树脂。
在所述工序(c)和所述工序(f)中，可以通过电解电镀法、无电解电镀法、印刷法、浸泡法或接线柱金球焊接法中的任意一种方法，形成所述第一突起电极和所述第二突起电极。
在所述工序(c)中，可以用含锡和银的合金、含锡和铅的合金、锡、镍、铜、铟、金中的任意一种形成所述第一突起电极。
附图说明
下面简要说明附图。
图1(a)是表示形成了多个半导体芯片的半导体晶片的模式图，图1(b)是放大表示图1(a)的半导体晶片的上表面的俯视图。
图2是表示本发明的半导体芯片的俯视图。
图3是表示本发明的半导体芯片的其它例子的俯视图。
图4是表示本发明的半导体芯片的其它例子的俯视图。
图5是表示本发明的半导体芯片的其它例子的俯视图。
图6是表示本发明的半导体装置的结构的图。
图7是表示半导体芯片的探测垫、电极垫以及各布线层的结构的剖视图。
图8是表示半导体芯片的探测垫、电极垫以及各布线层的结构的剖视图。
图9是表示本发明的半导体装置的制造方法的各过程的剖视图。
图10是表示本发明的半导体装置的制造方法的各过程的剖视图。
图11(a)是表示形成了多个半导体芯片的半导体晶片的模式图，图11(b)是放大表示图11(a)的半导体晶片的上表面的俯视图。
图12是表示以往的半导体装置的结构的图。
下面简要说明附图符号。
1、15—半导体晶片；2、17a—半导体芯片区域；2a、17c、22—半导体芯片；3—分离线；4、18—电极垫；5—半导体芯片；6—突起电极；7—外部电极垫；9—突起电极；10—绝缘性树脂；11—冲模垫；12—内部引线；13—金属细线；14—密封树脂；16—第一分离线；17、22a—整体芯片区域；17b—切断区域；19—探测垫；20—第二分离线；21—布线；23、25—突起电极；24—外部电极垫；26—内部电极垫；27—绝缘性树脂；28—冲模垫；29—内部引线；30—金属细线；31—密封树脂；32、33—间隔；34、35—宽度；36—保护电路；37—突起电极；38—通孔；38’—插塞；39、39’—扩散层；41—布线；42—布线层；43—布线层；44—探测针；45—切片胶带；46—注射器；47—脉冲加热工具；51、52、53—绝缘膜；53a—开口部；54—衬底；100、200—半导体装置。
具体实施方式
下面，参照附图，就本发明的实施例的半导体晶片以及使用了它的半导体装置加以说明。
首先，就本实施例的半导体晶片加以说明。图1(a)是表示形成了多个成为半导体芯片的半导体芯片区域的半导体晶片的模式图，图1(b)是放大表示图1(a)的半导体晶片的上表面的俯视图。
如图1(a)和图1(b)所示，本实施例的半导体晶片15形成了由第一分离线16划分的多个整体芯片区域17。在整体芯片区域17上，形成了集成电路(没有图示)、电极垫18、探测垫19，集成电路以及电极垫18与探测垫19之间有第二分离线20。第二分离线20在整体芯片区域17的表面上，位于第一分离线16的内侧，把整体芯片区域17分离为成为半导体芯片的半导体芯片区域17a、第一分离线16和第二分离线20之间的切断区域17b。即整体芯片区域17具有位于第二分离线20的内侧，并且成为半导体芯片的多个半导体芯片区域17a，和第一分离线16和第二分离线20之间的切断区域17b。
在此，第二分离线20是为了便于说明而虚拟的线，实际上不会在半导体晶片15上形成。另外，虽然在本实施例中第二分离线20是直线，但是，其当然也可以是曲线。
一些探测垫19通过横切第二分离线20的布线21与电极垫18相连。
电极垫18在构成半导体装置时，是用于连接从半导体芯片区域17a得到的半导体芯片和别的半导体芯片的电极垫，是用于在两个半导体芯片之间高速传递信号。并且，最好这样设置电极垫18：使其形成在半导体芯片区域17a内的布线和扩散层等的正上方，并且使到电极垫18的布线长度变短。
图2是表示沿着第二分离线20，用回转刀切断、分离的半导体芯片17c的俯视图。
如图2所示，除去形成了探测垫19的切断区域，在半导体芯片17c上留下集成电路(没有图示)、电极垫18、布线21。另外，在半导体芯片17c的侧端面上露出了布线21的切断面。
这样，在本实施例的半导体晶片15中，通过使探测针接触探测垫19而检查了各整体芯片区域17后，通过切断，除去形成了检查后变为不要的探测垫19的切断区域17b。因此，半导体芯片17a的尺寸比以往的半导体芯片区域2小。即能使从本实施例的半导体晶片15得到的半导体芯片17c的芯片尺寸比以往的半导体芯片2a小。
下面，参照附图，说明设置在上述的半导体晶片上的整体芯片区域17的其它例子。图3(a)、3(b)、4(a)、4(b)、5(a)、5(b)是表示形成在半导体芯片22上搭载的半导体芯片17c的整体芯片区域17的其它各种例子的俯视图。
在图3(a)所示的整体芯片区域17中，用于BIST等的检查电路(没有图示)设置在半导体芯片区域17a的内部。由此，能使切断区域17b的探测垫19的个数比电极垫18的个数少。例如，在本实施例的半导体装置100中，当半导体芯片17c是DRAM，并且半导体芯片22包含逻辑电路时，在图3(a)所示的整体芯片区域17中，电极垫18的个数需要约140个，而作为数据线用垫、地址线用垫、控制用垫、电源用垫等，必要的探测垫19的个数约为50个。
这样，通过减少探测垫19的个数，能使探测垫19的间隔32比电极垫18的间隔33大。例如，如果假设半导体芯片17a的面积是20mm2(边长4mm×5mm)，则在半导体芯片区域17a上，能使电极垫18的间隔33为80μm，配置约200个电极垫18。而如果假设半导体芯片区域17a的面积为20mm2，则能以间隔32为300μm配置探测垫19。如上所述，因为能增大探测垫19的间隔32，所以对于电极垫18的宽度34，能增大探测垫19的宽度35。因此，例如，当电极垫18的宽度34为50μm时，能使探测垫19的宽度35为250μm。
另外，如图3所示，能使探测垫19的形状为长方形，使各探测垫19的长边平行于各探测垫19沿着的整体芯片区域17的各边。由此，能抑制整体芯片区域17的尺寸变大，而且，使探测时探测针滑动(擦)的方向(即与各探测垫19沿着的整体芯片区域17的各边平行的方向)的探测垫19的形状变长。因此，能使检查更准确。
如果减少探测垫19的个数，如图3(b)、4(a)、4(b)、5(a)所示，即使不使用整体芯片区域17的四边，也能配置必要的探测垫19。图3(b)至5(a)所示的整体芯片区域17都具有与图3(a)所示的整体芯片区域17几乎相同的结构，只是探测垫19的个数和设置了探测垫19的切断区域17b的位置不同。具体而言，图3(b)表示了设置了探测垫19的切断区域17b位于整体芯片区域17的三边的例子。另外，图4(a)和图4(b)表示了切断区域17b位于整体芯片区域17的两边的例子。图5(a)表示了切断区域17b位于整体芯片区域17的一边的例子。
例如，在图5(a)所示的例子中，如果假设整体芯片区域17的尺寸为5mm×4.15mm，探测垫19的间隔为90μm，则能在位于整体芯片区域17的一边上的切断区域17b上配置宽度35为80μm的约50个探测垫19。
这样，通过减少探测垫19的个数，当在第二分离线20切断，从半导体芯片区域17a得到半导体芯片17c时，除去的切断区域17b的面积变小。因此，能增加从一片半导体晶片15得到的半导体芯片17c的个数，从而能削减半导体芯片17c的制造成本。
另外，在本实施例中，如上所述，能使探测垫19比电极垫18的尺寸大很多。因为通过切断，除去了探测垫19，所以没有必要考虑探测垫19的静电电容和电感。而在以往的半导体芯片2a中，因为电极垫4兼做探测垫，所以很难减小电极垫4的尺寸。因此，本实施例的半导体芯片17c的电极垫18引起的静电电容和电感比以往的半导体芯片2a的电极垫4引起的静电电容和电感小很多。例如，如果假设以往的半导体芯片2a的电极垫4的尺寸是75μm角，本实施例的半导体芯片17c的电极垫18的尺寸为15μm角，则电极垫的面积缩小到1/25，电极垫引起的静电电容在半导体芯片区域整体上减少0.1pF以上。
另外，在本实施例中，在半导体芯片区域17a的内部设置了用于BIST等的检查电路(没有图示)。因此，电极垫18中的一些只用于连接，不进行探测。能把这样的只用于连接的电极垫18配置在离开集成电路的距离尽可能短的位置。由此，能缩短连接电极垫和集成电路的布线，从而能降低该布线引起的静电电容和电感。以往的半导体芯片2a具有设置在半导体芯片2a的端部的连接电极垫4和集成电路的布线。具体而言，与以往的半导体芯片2a相比，本实施例的半导体芯片17c的静电电容在每1mm的布线长度上，减少了0.1pF。
这样，根据本实施例，能得到静电电容和电感的影响非常小的半导体芯片。
另外，在本实施例中，能在切断区域17b内设置用于保护集成电路免受探测时来自整体芯片区域17外部的电涌之影响的保护电路36。例如，如图5(b)所示，把保护电路36配置在探测垫19的旁边。由此，能进一步减小当用第二分离线20分离半导体芯片区域17a时的半导体芯片17c的尺寸。另外，因为通过切断也可除去保护电路36，所以能忽略保护电路36的静电电容和电感。
并且，倒装片接合用的电极垫因为使用突起电极(凸出)进行连接，所以能使电极垫18比一边为70μm的正方形还小。另外，通过倒装片接合，电极垫正下方所受机械应力也变小，故也可将布线及扩散层等配置于电极垫18的正下方。因此，根据本实施例，能把电极垫18、突起电极以及布线的静电电容和电感设计得极小。
如上所述，根据本实施例，通过把半导体晶片15的整体芯片区域17的结构设置为分别设置探测垫19、电极垫18，通过切断除去探测垫的结构，能消除对于整体芯片区域17上形成的探测垫、电极垫的个数、尺寸、间隔等的布线设计上的诸多限制。另外，也能消除对于连接在各电极垫上的布线和电极垫的配置等的布线设计上的诸多限制。
下面，参照图6，说明一下采用从上述的半导体晶片的半导体芯片得到的本实施例的半导体装置。图6(a)是表示制造本实施例的半导体装置时，把从半导体晶片15分离的半导体芯片17c搭载到另一个半导体芯片22上时的样子的图，图6(b)是本实施例的半导体装置的剖视图。
如图6(a)所示，在本实施例的半导体装置100中，通过在第二分离线20切断后分离得到的半导体芯片17c以面朝下的状态搭载在半导体芯片22之上。
如图6(a)和6(b)所示，半导体芯片22具有形成在它的上表面上的内部电极垫26以及外部电极垫24、连接在内部电极垫26以及外部电极垫24上的内部电路(没有图示)。突起电极23形成在内部电极垫26上。这里，突起电极25也形成在半导体芯片17c的电极垫18的上表面上。在本实施例的半导体装置100中，在突起电极23和突起电极25相连的状态下，通过倒装片接合把半导体芯片22和半导体芯片17c接合起来。
在本实施例中，形成在半导体芯片17c的电极垫18的上表面上的突起电极25由锡-银合金形成。锡-银合金的组成为对于锡，银的含量为3.5％，锡-银合金的厚度为30μm左右。锡-银合金也可以再包含铜、铋。也可以用锡-铅合金、锡、铟代替锡-银合金形成突起电极25。
另外，在本实施例中，为了提高半导体芯片17c的电极垫18和突起电极25的密合性并且防止金属扩散，在电极垫18上形成了底障碍金属层(没有图示)。底障碍金属层由从电极垫18一侧按钛、铜、镍、锡-银合金的顺序层叠的层叠膜形成。
另外，在本实施例中，虽然用镍膜形成了突起电极23，但是，也可以用锡-铅合金、锡、铟、金或铜中的任意一种形成。在本实施例中，镍膜的厚度为8μm左右，但是，为了防止氧化，也可以在镍膜的表面上形成0.05μm左右的金箔。
如图6(b)所示，在半导体芯片22和半导体芯片17c之间填充了绝缘性树脂27。这里，绝缘性树脂27的材料在本实施例中是环氧类热硬化型树脂，室温下的粘度是0.3~10Pa·s。并且，为了确保硬化后的绝缘性树脂27的特性，也可以在绝缘性树脂27中添加球形填充剂。另外，绝缘性树脂27的材料也可采用丙烯酸类、酚醛类树脂。
半导体芯片22固定在导线框架的冲模垫28上。另外，通过金属细线30，把半导体芯片22的外部电极垫24和导线框架的内部引线29电连接起来。用密封树脂31把半导体芯片22、半导体芯片17c、冲模垫28、内部引线29、金属细线30密封起来。
如上所述，在本实施例中，从半导体晶片15得到的半导体芯片17c的芯片尺寸比以往的半导体芯片2a小。因此，在本实施例的半导体装置100中，能减小半导体芯片22的尺寸。即根据本实施例，能得到比以往的半导体装置200小的半导体装置。
另外，根据本实施例，作为半导体芯片17c，通过使用图3(a)到图5(b)所示中的任意一个，能消减半导体装置的制造成本。
根据本实施例，能得到半导体芯片17c的静电电容和电感的影响非常小的半导体装置。
下面，就整体芯片区域17的探测垫19、电极垫18和各布线层的结构加以说明。图7和8是表示整体芯片区域17的探测垫19、电极垫18以及各布线层的结构的部分剖视图。
如图7(a)所示，整体芯片区域17中具有：具有形成在上表面上的扩散层39的衬底54、形成在衬底54上的绝缘膜51、52和53。连接以从绝缘膜53的开口部53a露出的形式而设置的探测垫19和电极垫18(突起电极25)的布线21，通过形成在绝缘膜52上的通孔38与连接了形成在衬底54上的扩散层39的布线44相连。
另外，如图7(b)所示，也可以通过绝缘膜52、53把连接探测垫19和电极垫18(突起电极25)的布线21分离，用位于第二分离线20的正下方的由多晶硅形成的布线41连接。由此，能抑制用刀切断后毛边的产生，能防止短路。
如图7(c)所示，也可以在比连接探测垫19和电极垫18的布线43更下层的布线层中形成连接电极垫18(突起电极25)和扩散层39的布线42。由此，与所述图7(a)以及图7(b)相比，能缩短从集成电路到电极垫18的布线长度。因此，能降低布线电容。
另外，如图8所示，也可以采用在探测垫19的正下方形成扩散层39’、通过插塞38’直接连接探测垫19和扩散层39’的布线结构。
下面，参照图9和10，说明一下本发明的半导体装置的制造方法。图9和10是表示本实施例的半导体装置的制造方法的各工序的剖视图。
首先，在图9(a)所示的工序中，准备具有用第一分离线16划分的多个整体芯片区域17的半导体晶片15。在整体芯片区域17上形成了集成电路(没有图示)、电极垫18、探测垫19。几个探测垫19通过横切第二分离线20的布线21与电极垫18相连。接着，通过使探测针44接触半导体晶片15的上表面上的探测垫19，进行各整体芯片区域17的检查。
接着，在图9(b)所示的工序中，在形成在半导体晶片15上的多个整体芯片区域17的上表面上的电极垫18上形成突起电极25。这里，用熔融金属即锡-银合金形成突起电极25。锡-银合金的组成为对于锡，银的含量为3.5％，锡-银合金的厚度为30μm左右。作为由锡-银合金构成的突起电极25的形成方法例如有电解电镀法、无电解电镀法、印刷法、浸泡法或接线柱金球焊接法等。另外，为了提高电极垫18和突起电极25的密合性和防止金属扩散，在电极垫18上，形成按钛、铜、镍、锡-银合金的顺序层叠的层叠膜作为底障碍金属层(没有图示)。并且，锡-银合金也可以再包含铜、铋。另外，也可以用锡-铅合金、锡、铟代替锡-银合金形成突起电极25。
接着，在9(c)所示的工序中，把切片胶带45贴在半导体晶片15的下表面上后，通过以回转刀沿着第二分离线20切断而分离出形成了探测垫19的切断区域17b和形成了电极点18以及集成电路(没有图示)的半导体芯片区域17a，就可形成半导体芯片17c。
接着，在图9(d)所示的工序中，得到半导体芯片17c。
接着，图10(a)所示的工序中，准备具有用分离线(没有图示)划分并且分离的多个成为半导体芯片22的整体芯片区域22a的半导体晶片(没有图示)。并且，这里，为了简单，只示意性地表示了整体芯片区域22a。在各整体芯片区域22a上形成了在上表面上形成的内部电极垫26和外部电极垫24、连接在内部电极垫26和外部电极垫24上的内部电路(没有图示)。接着，在各整体芯片区域22a的上表面上的内部电极垫26上形成突起电极23。在本实施例中，使用镍膜形成突起电极23。这时，镍膜的厚度为8μm左右，为了防止氧化，在镍膜的表面也可以用0.05μm左右的厚度形成金。用电解电镀法、无电解电镀法、印刷法、浸泡法或接线柱金球焊接法等作为由镍和金构成的突起电极25的形成方法。另外，除了镍，也可以用锡-银合金、锡-铅合金、锡、铟、金或铜中的任意一种作为形成突起电极23的熔融金属材料。
接着，在图10(b)所示的工序中，在整体芯片区域22a的上表面上涂抹绝缘性树脂27。在本实施例中，涂抹环氧类热硬化型树脂作为绝缘性树脂27的材料。绝缘性树脂27的材料最好使用室温下的粘度为0.3~10Pa·s的材料。并且，为了确保硬化后的绝缘性树脂27的特性，也可以在绝缘性树脂27的材料中添加球形填充剂。另外，可以用例如丙烯酸类、酚醛类树脂作为绝缘性树脂27的材料，也可以用热硬化性树脂、热可塑性树脂、2液混合的常温硬化性树脂、UV硬化性树脂和热硬化性树脂的并用中的任意一种。在本实施例中，作为绝缘性树脂27的供给方法，使用分配装置把绝缘性树脂27从注射器46滴到整体芯片区域22a的突起电极23上。此外，也可以根据整体芯片区域22a的形状和尺寸分多次滴下。也可以用基于复制法和印刷法的方法作为绝缘性树脂27的供给方法。
接着，在图10(c)所示的工序中，一边以整体芯片区域22a的突起电极23的熔点温度和半导体芯片17c的突起电极25的熔点温度中较低的熔点温度进行加热，一边把半导体芯片17c按压到整体芯片区域22a上。由此，熔融的突起电极23或25发生机械变形，突起电极23或25的表面氧化膜被破坏，突起电极23和突起电极25通过金属扩散容易地接合在一起。
在本实施例中，使用脉冲加热工具47，在221~300℃的温度下，进行1~3秒的加热和按压。当用锡-银合金形成了整体芯片区域22a的突起电极23时，最好通过用脉冲加热工具47，在183~250℃的温度下进行加热和按压，把半导体芯片17c接合到整体芯片区域22a上。当用锡形成了整体芯片区域22a的突起电极23时，最好通过用脉冲加热工具47，在290~400℃的温度下进行加热和按压，把半导体芯片17c按压到整体芯片区域22a上。当用铟形成了整体芯片区域22a的突起电极23时，最好通过用脉冲加热工具47，在190℃~250℃的温度下进行加热和按压，把半导体芯片17c按压到整体芯片区域22a上。
接着，在解除了基于脉冲加热工具47的加热和按压后，用热硬化炉使绝缘性树脂27热硬化。然后，把切片胶带贴在半导体晶片的下表面上后，通过以回转刀沿着分离线20切断而分离各整体芯片区域22a，来形成接合了半导体芯片17c的半导体芯片22。
接着，如图10(d)所示，用金属细线30连接了半导体芯片22的外部电极垫24和导线框架的内部引线29后，用密封树脂31把半导体芯片17c、半导体芯片22、冲模垫28、内部引线29、金属细线30密封起来。接着，通过形成从密封树脂31伸出的导线框架的外部引线，得到半导体装置100。
须指出的是，在本实施例中，虽然是在图10(c)所示的工序中分离各整体芯片区域22a，但是并不局限于此。例如，也可以在图10(a)所示的工序中分离各整体芯片区域22a而形成半导体芯片22，其后，再同样进行图10(b)以后的工序。
通过把本实施例中得到的半导体芯片17c和半导体芯片22构成的COC型半导体装置100搭载到导线框架、印刷电路板等上，也能形成半导体封装。
并且，在本实施例中，作为半导体芯片17c和半导体芯片22的组合，例如可以列举出包含DRAM等存储器的半导体芯片和包含微型电子计算机等逻辑电路的半导体芯片的组合、包含彼此不同的逻辑电路的半导体芯片的彼此的组合、或使用化合物半导体衬底制造的半导体芯片和使用硅衬底制造的半导体芯片的组合。另外，也可以把以彼此不同的工艺形成的两个半导体芯片、或把以一种工艺制造一大面积半导体芯片二分而成的两个半导体芯片组合在一起。
根据本发明，能提供小型、高性能的半导体装置。

Claims (16)

1.一种半导体晶片，具有：分别成为半导体芯片的多个半导体芯片区域和用于把所述多个半导体芯片区域分离为各半导体芯片的切断区域；
在所述多个半导体芯片区域上设置了集成电路和连接在所述集成电路上的电极垫；
在所述切断区域上设置了连接在电极垫上的探测垫。
2.根据权利要求1所述的半导体晶片，其特征在于：在所述半导体芯片区域的每一个区域上形成的所述电极垫的个数比连接在所述电极垫上的所述探测垫的个数多。
3.根据权利要求1所述的半导体晶片，其特征在于：在所述半导体芯片区域上分别形成的所述电极垫的间隔比连接在所述电极垫上的所述探测垫的间隔小。
4.根据权利要求1所述的半导体晶片，其特征在于：在所述半导体芯片区域的每一个区域上形成的所述电极垫的尺寸比连接在所述电极垫上的所述探测垫的尺寸小。
5.根据权利要求1所述的半导体晶片，其特征在于：沿着所述的半导体芯片区域的一边、两边或三边形成了连接在所述电极垫上的所述探测垫。
6.根据权利要求1所述的半导体晶片，其特征在于：所述探测垫的保护电路设置在所述切断区域上。
7.根据权利要求1所述的半导体晶片，其特征在于：连接在形成在所述半导体芯片区域的每一个区域上的所述电极垫上的布线是用比连接在所述探测垫上的布线更下层的布线层形成的。
8.一种半导体装置，其特征在于：具有：具有第一集成电路、连接在所述第一集成电路上的第一电极垫、形成在所述第一电极垫上的第一突起电极的第一半导体芯片和具有第二集成电路、连接在所述第二集成电路上的第二电极垫、形成在所述第二电极垫上的第二突起电极的第二半导体芯片；
在所述第一半导体芯片的侧端面上，连接在所述第一电极垫上的检查用布线的切断面露出；
所述第一突起电极和所述第二突起电极电连接。
9.根据权利要求8所述的半导体装置，其特征在于：在所述第一半导体芯片上不设置探测垫。
10.根据权利要求8所述的半导体装置，其特征在于：在所述第二半导体芯片的周边部上形成了用于与外部电路相连的外部电极垫。
11.根据权利要求8所述的半导体装置，其特征在于：在所述第一半导体芯片和所述第二半导体芯片之间存在绝缘性树脂。
12.根据权利要求8所述的半导体装置，其特征在于：通过密封树脂密封了所述第一半导体芯片和所述第二半导体芯片。
13.一种半导体装置的制造方法，包含以下工序：
准备具有分别成为第一半导体芯片的多个第一半导体芯片区域和用于把所述多个第一半导体芯片区域分离为各第一半导体芯片的切断区域，并且在所述第一半导体芯片区域上设置了第一集成电路和连接在所述第一集成电路上的第一电极垫，在所述切断区域上设置了连接在所述第一电极垫上的探测垫的第一半导体晶片的工序(a)；
使探测针接触所述探测垫，进行所述多个第一半导体芯片的检查的工序(b)；
在所述第一电极垫上形成第一突起电极的工序(c)；
通过除去所述第一半导体晶片的所述切断区域，从所述多个第一半导体芯片区域形成多个第一半导体芯片的工序(d)；
准备具有第二集成电路和连接在所述第二集成电路上的第二电极垫，并且具有分别成为第二半导体芯片的多个第二半导体芯片区域的第二半导体晶片的工序(e)；
在所述多个第二半导体芯片区域的每一个区域上形成的所述第二电极垫上形成第二突起电极的工序(f)；
通过加热和加压，电连接所述第一突起电极和所述第二突起电极的工序(g)；
把所述第二半导体晶片按所述多个第二半导体芯片区域切断的工序(h)。
14.根据权利要求13所述的半导体装置的制造方法，其特征在于：在所述工序(g)中，向所述第一半导体芯片和所述第二半导体芯片之间提供绝缘性树脂。
15.根据权利要求13所述的半导体装置的制造方法，其特征在于：在所述工序(c)和所述工序(f)中，通过电解电镀法、无电解电镀法、印刷法、浸泡法或接线柱金球焊接法中的任意一种方法，形成所述第一突起电极和所述第二突起电极。
16.根据权利要求13所述的半导体装置的制造方法，其特征在于：在所述工序(c)中，用含锡和银的合金、含锡和铅的合金、锡、镍、铜、铟、金中的任意一种形成所述第一突起电极。
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