CN1604312A - 倒装芯片安装电路板、其制造方法和集成电路装置 - Google Patents

倒装芯片安装电路板、其制造方法和集成电路装置 Download PDF

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CN1604312A
CN1604312A CNA2004100833115A CN200410083311A CN1604312A CN 1604312 A CN1604312 A CN 1604312A CN A2004100833115 A CNA2004100833115 A CN A2004100833115A CN 200410083311 A CN200410083311 A CN 200410083311A CN 1604312 A CN1604312 A CN 1604312A
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solder mask
circuit board
semiconductor element
bonding parts
plate
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兼行智彦
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TDK Corp
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TDK Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

本发明公开了一种倒装芯片安装电路板(10)，在安装半导体元件芯片(20)的板(12)上形成导体图形(14)，导体图形(14)具有将与半导体元件芯片(20)的电极接合的多个接合部分(14a)。此外，在板(12)上形成阻焊层(16)，使得其与两个相邻的接合部分(14a)隔开一预定距离，并且使其将相邻的接合部分(14a)彼此隔开。

Description

倒装芯片安装电路板、其制造方法和集成电路装置
                      技术领域
本发明涉及用于在其上安装半导体元件芯片的倒装芯片安装电路板、其制造方法和集成电路装置。
                      背景技术
进来，随着减小电子装置尺寸的要求，需要电路模块的高密度封装。为了这种需要，电路板从两面布线型变到多级互连型，并且有源元件日益微型化。此外，半导体器件从塑料模制半导体转变到裸芯片半导体，并且作为裸芯片安装方法之一，发展了倒装芯片安装，如在未审日本专利申请特开No.平6-151506、未审日本专利申请特开No.平8-181239和未审日本专利申请特开No.2000-77471中所公开的那样。
现在，将参考附图说明用于倒装芯片安装的常规电路板。图5示出了常规电路板110的平面图。图6示出了其上倒装芯片安装了半导体元件芯片120的电路板110的局部横截面图。
如图5和图6所示，导体图形114形成在电路板110的表面上。在电路板110的安装区域118(图5中由点划线包围的区域)上安装半导体元件芯片120。如后面将描述的那样，形成导体图形114，使得待安装的半导体元件芯片120的凸起电极124与导体图形114的端部附近的部分重叠。此外，如图5和6所示，涂覆阻焊层116，使得除了用于安装半导体元件芯片120的安装区域118之外，阻焊层116覆盖电路板110的表面。
在电路板110上通过下列工序倒装芯片安装半导体元件芯片120。
首先，将半导体元件芯片120定位，并且放置在电路板110上。注意：通过使用掩模，预先在待放置的半导体元件芯片120的凸起电极124上形成焊料凸起122。因此，如图6所示，定位半导体元件芯片120，使得其焊料凸起122与电路板110上的导体图形114的接合部分114a重叠。
此后，在电路板110上放置半导体元件芯片120的同时，通过回流等熔融焊料凸起122，并且机械地和电气地连接半导体元件芯片120和电路板110。接着，将未充满(underfill)树脂126填充到半导体元件芯片120和电路板110之间的空间中，然后硬化。结果，得到了电路板110，在电路板110上倒装芯片安装了半导体元件芯片120。
未审日本专利申请特开No.平8-181239公开了一种结构，其中形成阻焊层116，使得阻焊层116覆盖除导体图形114的接合部分114a之外的电路板110的几乎整个表面。例如，如图7所示，存在这样一种封装，其中通过与上述工序相同的工序在电路板110上倒装芯片安装半导体元件芯片120。在电路板110上的阻焊层116中形成开口116a，并且通过开口116a露出接合部分114a。
由于倒装芯片安装不需要用于连接的布线等，因此可以减小器件的尺寸。然而，最近，产品尺寸减小越来越加速，需要突起之间的间隔为300μm或者更小的半导体器件。在这种情况下，图5至图7所示的常规电路板在更进一步降低尺寸上有一个问题。
例如，如果接合部分114a之间的间隔、即突起122之间的间隔为300μm或者更小，图6所示的其中阻焊层不形成在接合部分114a之间的结构在进行热冲击可靠性测试等之后会发生许多短路。这些短路被认为是由于突起122很可能由于阻焊层116不形成在其间而扩散导致的。
另一方面，图7所示的其中形成阻焊层116使得其几乎完全覆盖导体图形114的结构很可能引起接触失效。这被认为是由于阻焊层116很可能留在与凸起122接合的导体图形114的接合部分上而导致的。如果由导体图形114形成的电极的宽度大约为50至80μm，接触失效就会频繁出现。
如上所述，常规电路板容易引起短路或者失效，这会毁坏高的安装效率(产量)和产品可靠性。
                      发明内容
考虑上述情况，本发明的目的是提供一种倒装芯片安装电路板、该电路板的制造方法和集成电路装置，该电路板能够在保持有高产量和可靠性的情况下减少其尺寸。
本发明的另一个目的是提供一种倒装芯片安装电路板、这种电路板的制造方法和集成电路装置，该电路板能够防止相邻凸起之间的短路，并且可以在电路板自身和安装在其上的元件之间实现理想的凸起-电极接触。
为了实现上述目的，根据本发明第一方面的倒装芯片安装电路板包含：
板(12)，其上将安装半导体元件芯片；
导体图形(14)，其设置在板(12)上，并且包括将与该半导体元件芯片的电极接合的多个接合部分；以及
阻焊层(16)，设置该阻焊层，使得其与多个接合部分分离，并且其将多个接合部分之中相邻两个接合部分彼此隔开。
为了实现上述目的，根据本发明第二方面的倒装芯片安装电路板的制造方法包含以下步骤：
制备其上将安装半导体元件芯片的板；
在板上形成导体图形，该导体图形具有将与半导体元件芯片的电极接合的多个接合部分；以及
形成阻焊层，设置该阻焊层，使得其与多个接合部分分离，并且其将多个接合部分之中相邻两个接合部分彼此隔开。
为了实现上述目的，根据本发明第三方面的集成电路装置包含：
板；
设置在板上的导体图形；
半导体元件芯片，其电极与导体图形接合；
具有阻焊层的倒装芯片安装电路板，设置该阻焊层，使得其与在导体图形和电极接合处的多个接合部分分离，并且其将多个接合部分之中相邻两个接合部分彼此隔开。
                       附图说明
通过阅读下面的详细描述和附图，本发明的这些目的和其它目的及优点将变得更加显而易见，其中：
图1是根据本发明实施例的倒装芯片安装电路板的平面图；
图2是在根据本发明实施例的倒装芯片安装电路板上安装半导体元件芯片的平面图；
图3是倒装芯片安装电路板在其上安装了半导体元件芯片的状态下的横截面图；
图4是显示根据本发明的倒装芯片安装电路板的修改例的视图；
图5是常规倒装芯片安装电路板的平面图；
图6是常规倒装芯片安装电路板在其上安装了半导体元件芯片的情况下的横截面图；
图7是常规倒装芯片安装电路板在其上安装了半导体元件芯片的状态下的横截面图。
                     具体实施方式
下面将参考附图详细说明根据本发明实施例的倒装芯片安装电路板、其制造方法和集成电路装置。
图1示出了根据本发明实施例的倒装芯片安装电路板10的结构的例子。在图1中，为了更容易理解，将在其上安装半导体元件芯片20的区域描述作为安装区域18(图1中由点划线表示的区域)。此外，在图1中，为了更容易理解，偏移阻焊层16的端部和板12的端部。然而，阻焊层16实际上形成在板12的几乎整个表面上。
倒装芯片安装电路是通过在倒装芯片安装电路板10上安装半导体元件芯片20得到的电路。集成电路装置是具有该倒装芯片安装电路的装置。
如图1所示，根据本实施例的倒装芯片安装电路板10包含板12、导体图形14和阻焊层16。
板12例如由印刷电路板构成。
导体图形14例如由铜构成，并且利用预定图形通过蚀刻等形成在板12的表面上。通过阻焊层16中的开口16a露出在导体图形14端部附近的导体图形14的一部分。形成该部分，使得其与设置在后面将描述的半导体元件芯片20上的凸起22重叠。在图1所示的例子中，导体图形14在端部的接合部分14a处接合到半导体元件芯片20的凸起22上。
如后面将描述的，阻焊层16具有与接合部分14a隔开预定宽度的开口16a，并且形成阻焊层16，使得覆盖包含用于安装半导体元件芯片20的安装区域18(图1中由点划线包围的区域)的板12的几乎整个表面。结果，相邻接合部分14a由阻焊层16隔开。在本说明书中，“相邻”意味着部件在其间具有最短的相对距离。
图2示出了将要安装在电路板10上的半导体元件芯片20。
半导体元件芯片20包括凸起22和凸起电极24。
凸起电极24例如由铝等构成，并且设置凸起电极24，使得其彼此隔开预定宽度。
凸起22由金等构成，并且通过印刷、镀覆、汽相淀积等形成在凸起电极24上，使其为具有预定半径的球形。
图3示出了其上安装半导体元件芯片20的电路板10的横截面图，如沿着图1的A-A线所截取的那样。
如图3所示，安装半导体元件芯片20，使得凸起22进入阻焊层16的开口16a中。凸起22接合到半导体元件芯片20的凸起电极24上，并且接合到导体图形14上，用于将它们彼此电连接。
半导体元件芯片20和电路板10通过凸起22插入地(interveningly)支撑，并且它们之间的空间由未充满树脂26密封。半导体元件芯片20和电路板10通过未充满树脂26彼此牢固地固定。
根据本实施例，如图3所示，在相邻接合部分14a之间设置阻焊层16，使得其与两个相邻接合部分14a隔开预定距离。在下面的说明中，相对于接合部分14a，形成阻焊层16，但是，可以相对于凸起22，形成阻焊层16。
阻焊层16和相邻接合部分14a的每一个之间的距离a1和a2由如后面将描述的布图阻焊层16时的掩模匹配精度确定，但是优选为30μm或者更多。
在本例子中，考虑到布图时阻焊层16向导体图形14偏移大约30μm的可能性，所以形成阻焊层16，使得其离接合部分14a具有30μm或者更多的裕度。
据此，接合部分14a之间的距离“c”和阻焊层16的宽度“b”之间的差(差＝a1+a2)优选为60μm或者更多。换句话说，优选地设定阻焊层16的宽度“b”比相邻接合部分14a之间的距离“c”小60μm或者更多。
此外，换句话说，优选地设定阻焊层16的开口16a的宽度“d”比接合部分14a的最大宽度“e”大60μm或者更多。
现在，说明根据本实施例的倒装芯片安装电路板10的制造方法和使用倒装芯片安装电路板10的倒装芯片安装方法。本发明并不限于下面所描述的例子，而是可以包含其它例子，只要通过这些方法能够得到相同的效果即可。
首先，制备板12，在板12上形成铜等的导体膜。接着，布图导体膜，以便具有预定形状，由此形成导体图形14。
接着，在板12上形成阻焊层16，并且通过布图在阻焊层16中形成开口16a。此时，优选地，形成开口16a的宽度“d”，使其比如上所述的接合部分14a的最大宽度“e”大60μm或者更多。
结果，形成了根据本实施例的倒装芯片安装电路板10。
在倒装芯片安装时，通过定位使得印刷在电路板10上的凸起22接触通过开口16a露出的导体图形14，从而在电路板10上安装半导体元件芯片20。在该状态下，通过应用热处理例如回流工艺等熔融凸起22，由此机械地和电气地连接半导体元件芯片20和导体图形14。
此后，在倾斜的热板上将未充满树脂26浇入半导体元件芯片20和电路板10之间的空间中。然后，从热板取出其上安装了半导体元件芯片20的电路板10，并且固化未充满树脂20。
通过上述工艺，将半导体元件芯片20牢固地固定到电路板10上。通过下面的这些步骤，在电路板10上倒装芯片安装半导体元件芯片20。
如上所述，根据本实施例，形成阻焊层16，使得相邻的接合部分14a彼此分隔开，如图2所示。在接合部分14a之间的间隔变细降到300μm后者更小的情况下，与在接合部分14a之间没有阻焊层16的结构相比，该结构更可以防止凸起22扩散，由此抑制并且减少凸起22之间的短路。
此外，根据本实施例，形成阻焊层16，使得与接合部分14a隔开预定的距离，例如30μm或者更大。考虑阻焊层16的可能的偏移，来设置该距离，该偏移取决于布图阻焊层16时的掩模匹配精度。即，在本例中，在考虑布图时阻焊层16可能向导体图形14偏移大约30μm的可能性的情况下，形成阻焊层16，使其离接合部分14a具有30μm或者更大的裕度。通过考虑掩模匹配精度形成开口16a，能够防止凸起22和导体图形14之间由于形成的阻焊层16与凸起22重叠而导致的接触失效。结果，可以减少安装失败。
因此，根据本实施例，能够减少凸起22之间的短路和凸起22的接触失效，由此提高产量和可靠性。
此外，由于阻焊层16具有宽度比接合部分14a的宽度大预定程度的开口16a，因此安装时可以容易地将凸起22引入到开口16a中，从而提高安装效率。
本发明并不限于上述实施例，而是可以各种方式进行修改和应用。例如，根据上述实施例，导体图形14与凸起22直接接合。然而，可以提供与导体图形14电连接的连接电极层，并且可以将凸起22与其接合。
根据上述实施例，在阻焊层16中形成了具有矩形的开口16a。然而，开口的形状并不限于此，而可以是其它多边形或者可以是如图4所示的圆形。在将开口16a形成为圆形的情况下，可以更容易地将凸起22引入到开口16a中，这是因为凸起22通常是球形的。这样提高安装效率。具有圆形开口16a的结构对于安装其中以交错状态设置凸起的半导体元件芯片20来说尤其有效。
根据上述实施例，阻焊层16与接合部分14a隔开30μm或者更大。然而，通过掩模匹配精度，确定该距离(裕度)。据此，如果利用高精度掩模布图可以实现的话，那么该距离可以小于30μm。
此外，根据上述实施例，阻焊层16的开口16a的宽度基于接合部分14a而设定。然而，凸起22的宽度“e”可以用作该基础。
也在这种情况下，阻焊层16和凸起22之间的距离也通过布图阻焊层16时的掩模匹配精度确定。例如，在当布图阻焊层16时阻焊层16可以向着导体图形14偏移大约30μm的情况下，可以形成阻焊层16使其离凸起22具有30μm或者更大的裕度。
此外，由于回流工艺之后改变了凸起22的宽度，因此可以将安装之前凸起22的宽度，即在凸起是球形的情况下该球的直径，作为基础。
根据本发明，能够提供一种倒装芯片安装电路板、其制造方法和集成电路装置，该电路板可以在保持其高产量和可靠性的情况下降低尺寸。
此外，根据本发明，能够提供一种倒装芯片安装电路板、其制造方法和集成电路装置，该电路板能够防止相邻凸起的短路，并且能够实现电路板自身和其上安装的元件之间的理想的凸起-电极接触。
在不偏离本发明的精神和范围的情况下，可以对其进行各种修改和变化。上述实施例的目的是说明本发明，而不是限制本发明的范围。本发明的范围由附加的权利要求而不是实施例示出。在本发明权利要求的等效意义内进行的各种修改都应认为在本发明的范围内。

Claims (13)

1、一种倒装芯片安装电路板(10)，包含：
板(12)，其上将安装半导体元件芯片；
导体图形(14)，其设置在所述板(12)上，并且包括将与该半导体元件芯片的电极接合的多个接合部分；以及
阻焊层(16)，设置该阻焊层(16)，使得其与所述多个接合部分分开，并且其将所述多个接合部分之中相邻两个结合部分彼此分隔开。
2、根据权利要求1的倒装芯片安装电路板，
其中，所述阻焊层(16)具有比所述多个接合部分(14a)之中相邻两个结合部分之间的间隔窄的宽度。
3、根据权利要求2的倒装芯片安装电路板，
其中，所述阻焊层(16)的宽度比所述多个接合部分(14a)之中相邻两个接合部分之间的间隔小60μm或者更多。
4、根据权利要求1的倒装芯片安装电路板，
其中，所述阻焊层(16)与所述多个接合部分(14a)隔开30μm或者更多。
5、根据权利要求1的倒装芯片安装电路板，
其中，所述阻焊层(16)具有形成为围绕所述接合部分(14a)的多个开(16a)。
6、根据权利要求5的倒装芯片安装电路板，
其中，所述开口(16a)形成为矩形。
7、根据权利要求5的倒装芯片安装电路板，
其中，所述开口(16a)形成为圆形。
8、一种倒装芯片安装电路板(10)，包含：
板(12)，其上将安装半导体元件芯片；
导体图形(14)，其设置在所述板(12)上，并且包括将与该半导体元件芯片的电极接合的多个接合部分；以及
阻焊层，形成该阻焊层，使得其覆盖所述板(12)，并且该阻焊层包括多个开口，形成所述多个开口，使得它们在对应于所述多个接合部分的位置处比所述多个接合部分大预定的宽度。
9、一种倒装芯片安装电路板(10)，包含：
板(12)，其上将安装半导体元件芯片；
导体图形(14)，其设置在所述板(12)上，并且包含将与该半导体元件芯片的电极接合的多个接合部分；以及
阻焊层，形成在所述板(12)上，使得其围绕所述导体图形(14)的所述多个接合部分。
10、一种倒装芯片安装电路板，包括：
板，其上将安装具有多个凸起的半导体元件芯片；
导体图形，设置在所述板上，并且包括将与所述半导体元件芯片的多个凸起接合的多个接合部分；和
阻焊层，形成该阻焊层，使得其覆盖所述板，并且包括多个开口，形成所述多个开口，使得它们在接合凸起的位置比所述多个凸起大预定的宽度。
11.一种倒装芯片安装电路板，包括：
板，其上将安装具有多个凸起的半导体元件芯片；
导体图形，设置在所述板上，并且包括将与所述半导体元件芯片的多个凸起接合的多个接合部分；和
阻焊层，相应地形成在所述板上将与所述凸起接合的位置，并且形成为围绕所述凸起。
12、一种倒装芯片安装电路板的制造方法，包含以下步骤：
制备其上将安装半导体元件芯片的板；
在所述板上形成导体图形，该导体图形具有将与半导体元件芯片的电极接合的多个接合部分；和
形成阻焊层，设置该阻焊层，使得其与所述多个接合部分分离，并且使其将所述多个接合部分之中相邻两个接合部分彼此隔开。
13、一种集成电路装置，包括：
板；
设置在所述板上的导体图形；
半导体元件芯片，其电极与所述导体图形接合；
具有阻焊层的倒装芯片安装电路板，设置该阻焊层，使其与接合所述导体图形和所述电极的多个接合部分分离，并且其将所述多个接合部分之中相邻两个接合部分彼此隔开。
CNA2004100833115A 2003-09-30 2004-09-29 倒装芯片安装电路板、其制造方法和集成电路装置 Pending CN1604312A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102413629A (zh) * 2011-07-27 2012-04-11 大唐移动通信设备有限公司 一种印制电路板及其制造方法

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853001B2 (en) 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
TWI358776B (en) * 2003-11-08 2012-02-21 Chippac Inc Flip chip interconnection pad layout
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
KR101249555B1 (ko) * 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20060216860A1 (en) * 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US7901983B2 (en) 2004-11-10 2011-03-08 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
US8076232B2 (en) 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
JP2006100552A (ja) * 2004-09-29 2006-04-13 Rohm Co Ltd 配線基板および半導体装置
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
JP4533248B2 (ja) * 2005-06-03 2010-09-01 新光電気工業株式会社 電子装置
KR101134168B1 (ko) * 2005-08-24 2012-04-09 삼성전자주식회사 반도체 칩 및 그 제조 방법과, 그를 이용한 표시 패널 및그 제조 방법
JP4971769B2 (ja) * 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
JP4758813B2 (ja) * 2006-04-26 2011-08-31 新光電気工業株式会社 実装基板
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
JP5091469B2 (ja) * 2006-12-05 2012-12-05 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US20090250814A1 (en) * 2008-04-03 2009-10-08 Stats Chippac, Ltd. Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
US7897502B2 (en) * 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8198186B2 (en) * 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
JP5433543B2 (ja) * 2010-09-27 2014-03-05 ローム株式会社 半導体装置
TWI536617B (zh) * 2012-02-17 2016-06-01 鴻海精密工業股份有限公司 發光二極體燈條及其製造方法
US10431533B2 (en) * 2014-10-31 2019-10-01 Ati Technologies Ulc Circuit board with constrained solder interconnect pads

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577490B2 (en) * 2000-12-12 2003-06-10 Ngk Spark Plug Co., Ltd. Wiring board
US6770965B2 (en) * 2000-12-28 2004-08-03 Ngk Spark Plug Co., Ltd. Wiring substrate using embedding resin
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
JP2004186422A (ja) * 2002-12-03 2004-07-02 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102413629A (zh) * 2011-07-27 2012-04-11 大唐移动通信设备有限公司 一种印制电路板及其制造方法

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