CN1197145C - 凸块形成方法、半导体装置及其制造方法和半导体芯片 - Google Patents
凸块形成方法、半导体装置及其制造方法和半导体芯片 Download PDFInfo
- Publication number
- CN1197145C CN1197145C CNB011412437A CN01141243A CN1197145C CN 1197145 C CN1197145 C CN 1197145C CN B011412437 A CNB011412437 A CN B011412437A CN 01141243 A CN01141243 A CN 01141243A CN 1197145 C CN1197145 C CN 1197145C
- Authority
- CN
- China
- Prior art keywords
- pad
- metal level
- projection
- resist layer
- scolder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 62
- 230000015572 biosynthetic process Effects 0.000 title claims description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 205
- 239000002184 metal Substances 0.000 claims abstract description 205
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000007772 electroless plating Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 238000005755 formation reaction Methods 0.000 description 52
- 239000000243 solution Substances 0.000 description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 22
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 14
- 229910052725 zinc Inorganic materials 0.000 description 14
- 239000011701 zinc Substances 0.000 description 14
- 239000000155 melt Substances 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000010436 fluorite Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 208000007578 phototoxic dermatitis Diseases 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
- H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
本发明涉及具有高可靠性、适合于狭窄间距的凸块形成方法、半导体装置及其制造方法、半导体芯片、电路基板及电子设备。本发明的凸块形成方法包括以在垫片12上具有贯通孔22的方式形成抗蚀剂层20、配合贯通孔22的形状形成与垫片12电连接的金属层(凸块34)的工序,把金属层(凸块34)形成为具有用于容纳焊料40的区域(凹部36)的形状。
Description
技术领域
本发明涉及凸块形成方法、半导体装置及其制造方法、半导体芯片、电路基板及电子设备。
发明的背景
有在半导体芯片的垫片上适用非电解电镀等形成金属凸块的方法。该半导体芯片例如在金属凸块上设置焊锡,通过熔化该焊锡,电连接于基板的配线图案(引线)。这样,与通过加热和加压引线实现垫片连接的形态不同,由于可通过焊锡熔化来连接,能够抑制施加在半导体芯片的面上的压力。由此,例如,不仅半导体芯片的端部,在元件形成区域上也可配置垫片,所以可以以宽间距配置很多垫片。另外,通过使用焊锡,与形成金凸块相比,可低成本地制造半导体装置。
但是,根据该形态,各个垫片的焊锡因与配线图案连接时熔化而流向相邻的垫片,有时引起垫片之间的短路。这仅通过减少设置在各垫片上的焊锡的数量是不能解决的。
本发明正是为解决这个问题,其目的涉及具有高可靠性、适合于狭窄间距的凸块形成方法、半导体装置及其制造方法、半导体芯片、电路基板及电子设备。
发明概述
(1)本发明的凸块形成方法包括:以具有贯通孔的方式在垫片上形成抗蚀剂层、配合贯通孔的形状形成与所述垫片电连接的金属层的工序,把所述金属层形成为具有用于容纳焊料的区域的形状。
根据本发明,配合贯通孔的形状把金属层形成为规定形状。金属层具有容纳焊料的区域。这样,焊料进入金属层的区域中,难以扩散到金属层外侧。即,例如防止了金属层上熔化的焊料流入相邻的垫片。因此,垫片之间不短路,可提高后面的制造成品率。
(2)在该凸块形成方法中,可以以在所述贯通孔的内侧面上具有突起的方式形成所述抗蚀剂层。
这样,可在金属层的侧面形成凹部。从而,焊料进入金属层的凹部,焊料难以扩散到外侧。
(3)在该凸块形成方法中,可以是以在所述贯通孔的中央部位残留下一部分所述抗蚀剂层的方式形成所述抗蚀剂层。
这样,可在金属层的中央部位形成容纳焊料的区域。由此,焊料进入金属层的中央部位区域,焊料难以扩散到外侧。
(4)该凸块形成方法中,可在所述抗蚀剂层中形成多个所述贯通孔,把所述多个贯通孔形成为至少一部分与1个所述垫片平面重合,通过配合各个所述贯通孔形成所述金属层,在1个所述垫片上的相邻的所述金属层之间设置所述区域。
这样,通过使焊料进入在1个垫片的相邻金属层之间设置的区域中,而使焊料难以扩散到外侧。
(5)该凸块形成方法中,所述金属层可包括第一和第二金属层,在形成了所述抗蚀剂层的状态下形成所述第一金属层,在所述第一金属层上还形成所述第二金属层。
这样,例如在把比第一金属层更容易粘附焊料的材料作为第二金属层使用的情况下,可仅在金属层的上面设置焊料。即可更可靠地防止焊料扩散到金属层外侧。
(6)该凸块形成方法中,所述金属层可包括第一和第二金属层,在形成了所述抗蚀剂层的状态下形成所述第一金属层,在去除所述抗蚀剂层后覆盖所述第一金属层的表面形成所述第二金属层。
这样,可防止第一金属层的表面氧化。
(7)该凸块形成方法中,可用绝缘膜覆盖所述垫片,把所述抗蚀剂层形成在所述绝缘膜上,在所述抗蚀剂层中形成所述贯通孔后,在所述绝缘膜上形成至少露出所述垫片的一部分的开口部,在形成了所述抗蚀剂层的状态下在所述垫片上形成所述第一金属层。
这样,使用一次形成的抗蚀剂层的贯通孔,在绝缘膜中形成开口部,形成与垫片电连接的金属层,从而可用简单工序形成凸块。
(8)该凸块形成方法中,所述第一和第二金属层可通过非电解电镀形成。
(9)该凸块形成方法中,所述第一金属层可由含镍材料形成。
(10)该凸块形成方法中,所述第二金属层可由含金的材料形成。
(11)本发明的半导体装置制造方法,包括:将在半导体芯片的多个垫片上设置的按具有用于容纳焊料的区域的形状形成的多个金属层和多个引线经所述焊料接合的工序,熔化所述焊料时,使所述焊料进入所述金属层的所述区域中,以防止其扩散到相邻的垫片。
根据本发明,使金属层与引线之间设置的焊料进入金属层的区域中而难以扩散到外侧。即,防止了金属层上熔化的焊料流入相邻的垫片。因此,垫片之间不短路,可提高后面的制造成品率。
(12)该半导体装置制造方法中,所述金属层在侧面上可具有至少一个凹部,以使所述焊料进入所述凹部中。
这样,通过焊料进入金属层侧面的凹部中而难以扩散到外侧。
(13)该半导体装置制造方法中,所述金属层可形成为在中央部位具有沿所述金属层的高度方向凹陷而成的凹部,以使所述焊料进入所述凹部中。
这样,通过焊料进入沿金属层高度方向凹陷而成的凹部中而难以扩散到外侧。
(14)在该半导体装置制造方法中,可在1个所述垫片上连续形成2个以上的所述金属层,以使所述焊料进入1个所述垫片上的相邻的所述金属层之间。
这样通过焊料进入1个垫片上相邻的所述金属层之间而难以扩散到外侧。
(15)本发明的半导体装置用上述半导体装置的制造方法制造。
(16)本发明的半导体芯片,具有多个垫片,在各个所述垫片上设置以具有用于容纳焊料的区域的形状形成的金属层。
(17)该半导体芯片中,所述金属层可在侧面上具有至少一个凹部。
(18)该半导体芯片中,所述金属层可在中央部位具有沿所述金属层的高度方向凹陷而成的凹部。
(19)该半导体芯片中,可在1个所述垫片上形成2个以上的所述金属层。
(20)本发明的半导体装置,包括:具有多个垫片的半导体芯片、设置在各个所述垫片上以具有用于容纳焊料的区域的形状形成的金属层、多个引线,各个所述金属层经所述引线和所述焊料之一接合,所述焊料的一部分进入所述区域中。
根据本发明,部分焊料进入金属层的区域中,焊料难以扩散到金属层外侧。即,防止了金属层上熔化的焊料流入相邻的垫片。因此,垫片之间不短路,可提供可靠性高的半导体装置。
(21)该半导体装置中,所述金属层可在侧面上具有至少一个凹部,所述焊料的一部分进入所述凹部中。
(22)该半导体装置中,所述金属层可在中央部位具有沿所述金属层的高度方向凹陷而成的凹部,所述焊料的一部分进入所述凹部中。
(23)该半导体装置中,可在1个所述垫片上形成2个以上的所述金属层,所述焊料的一部分进入1个所述垫片上的相邻的所述金属层之间。
(24)本发明的电路基板,装载上述半导体装置。
(25)本发明的电子设备,具有上述半导体装置。
附图的简要说明
图1是表示适用本发明的第一实施例的凸块形成方法的图;
图2是表示适用本发明的第一实施例的凸块形成方法的图;
图3(A)~3(C)是表示适用本发明的第一实施例的凸块形成方法的图;
图4(A)~4(C)是表示适用本发明的第一实施例的凸块形成方法的图;
图5是表示适用本发明的第一实施例的凸块形成方法的图;
图6(A)~6(C)是表示适用本发明的第一实施例的变形例的凸块形成方法的图;
图7是表示适用本发明的第一实施例的半导体装置及其制造方法的图;
图8是表示适用本发明的第二实施例的凸块形成方法的图;
图9(A)~9(C)是表示适用本发明的第二实施例的凸块形成方法的图;
图10是表示适用本发明的第二实施例的凸块形成方法的图;
图11是表示适用本发明的第二实施例的变形例的凸块形成方法的图;
图12(A)和12(B)是表示适用本发明的第三实施例的凸块形成方法的图;
图13是表示安装适用本发明的实施例的半导体装置的电路基板的图;
图14是表示具有适用本发明的实施例的半导体装置的电子设备的图;
图15是表示具有适用本发明的实施例的半导体装置的电子设备的图。
实施例
下面参考附图说明本发明的最佳实施例。其中,本发明并不限定于下面的
实施例。
(第一实施例)
图1~图6(C)是表示适用本发明的第一实施例的凸块形成方法的图。本实施例中,说明在半导体芯片上形成凸块的例子,但本发明的凸块形成方法并不限定于此,可适用在引线上形成凸块的方法。引线可以是在基板上形成的配线图案。这种情况下,配线图案的脊(land)与垫片相当。本发明还可在半导体晶片上形成的垫片上形成凸块时适用。
本实施例中,如图1所示,准备半导体芯片10。半导体芯片10多是长方体(包括立方体),但也可形成为例如球状。半导体芯片10的厚度不限定,可使用磨薄形成的半导体芯片10。
半导体芯片10具有多个垫片12。垫片12成为在内部形成的集成电路的电极。垫片12一般形成在形成半导体芯片10的集成电路的面的一侧上。这种情况下,垫片12可形成在集成电路区域的外侧,或形成在集成电路的区域的内侧。垫片12一列或多列地并排形成在半导体芯片10的端部或中央部位。或者垫片12多行多列地并排形成在半导体芯片10的面上,形成矩阵状。
垫片12的平面形状可以是矩形或圆形。垫片12多由包含铝的成分形成,也可由包含铜等的成分构成。
在形成半导体芯片10的垫片12的面上形成绝缘膜14。本实施例中,如图所示,绝缘膜14覆盖各垫片12形成。即,半导体芯片10可使用各垫片12不从绝缘膜14露出的状态。本实施例中,使用为从绝缘膜14露出各垫片12而形成的抗蚀剂层,在垫片12上形成凸块。
绝缘膜14可用单层或多层形成。绝缘膜14厚度不限定。绝缘膜14也叫作钝化膜。绝缘膜14例如由SiO2、SiN或聚合树脂等形成。
本实施例的半导体装置的制造方法使用上述半导体芯片10进行下面的工序。下面说明的内容同样适用于半导体晶片的处理。
如图2和图3(A)所示,半导体芯片10上形成抗蚀剂层20。图2是半导体芯片10的平面图。图3是半导体芯片10的剖面图。在形成半导体芯片10的垫片12的面上,即在绝缘膜14上形成抗蚀剂层20。抗蚀剂层20的厚度可根据后面形成的凸块的高度自由确定。抗蚀剂层20可按例如20μm左右的厚度设置。
抗蚀剂层20在垫片12的上方,即在绝缘膜14上有贯通孔22。具体说,贯通孔22至少一部分(一部分或全部)与垫片12平面重合地形成。贯通孔22与垫片12部分重合,则在贯通孔22形成的凸块可电连接于垫片12。
本实施例中,如图2所示,把贯通孔22形成为在内侧面上具有突起。换言之,与抗蚀剂层20的贯通孔22相接的壁面上形成多个突起。抗蚀剂层20的突起部24形成1个或多个。贯通孔22的平面形状可以是从垫片12的类似形状开始在每个边上向内侧使抗蚀剂层20的一部分突起而形成的形状。或者,贯通孔22的平面形状也可以是从圆形的平面形状开始向着内侧使抗蚀剂层20的一部分突起而形成的形状。通过形成抗蚀剂层20的突起部24,凸块的侧面上形成凹部36(见图5)。贯通孔22也可以相同平面形状在抗蚀剂层20的厚度方向上贯通形成。
作为抗蚀剂层20的形成方法,可应用光刻技术。即,经未示出的掩模在感光性抗蚀剂层20上照射能量并显像形成贯通孔22。掩模的形状若形成为抗蚀剂层20在贯通孔22内侧突起,则可把贯通孔22形成为规定形状。抗蚀剂层20可以是正型或负型抗蚀剂。
或者通过蚀刻非感光性抗蚀剂层20,把贯通孔22形成为规定形状。抗蚀剂层20若把贯通孔22形成为规定形状,可适用丝网印刷或喷墨方式形成。
如图所示,贯通孔22不超出垫片12的外周形成。这样,各垫片12之间的间距即使非常狭窄,也形成相邻的垫片12不会短路的凸块。或者,贯通孔22可形成为超出垫片12的外周。或者,贯通孔22可形成为在其外周的一部分上与垫片12的外周交错。
如图3(B)所示,经抗蚀剂层20的贯通孔22去除部分绝缘膜14。即,去除贯通孔22内的部分绝缘膜14,形成露出垫片12的至少一部分(部分或全部)的开口部26。开口部26可通过蚀刻形成。蚀刻方式可以是化学或物理的,其组合也可以。蚀刻特性可以是各向同性或各向异性。在适用各向同性蚀刻的情况下,超出贯通孔22的外周,形成绝缘膜14的开口部26。绝缘膜14的开口部26可不超出垫片12的外周形成,或者超出垫片12的外周形成。从垫片12的开口部26露出部分的大小不限,例如可以是一边为20μm左右的角形。
如图3(C)所示,配合贯通孔22的形状形成第一金属层30。具体说,沿着贯通孔22的内面形成第一金属层30。第一金属层30灌满贯通孔22与抗蚀剂层20的表面成为同一平面。或者,第一金属层30可超出抗蚀剂层20的表面,也可在其表面高度以下。无论哪种情况,通过沿着贯通孔22的内面形成第一金属层30,可把第一金属层30形成为规定形状。
由于贯通孔22连通绝缘膜14的开口部26,通过在贯通孔22形成第一金属层30,可形成与垫片12电连接的凸块。如图所示第一金属层30为单层,也可形成多层。第一金属层30是含镍材料的,作为第一金属层30若使用镍层,则可用较短时间形成,并且形成低成本的凸块。或者,可用含金的材料形成第一金属层30。
第一金属层30可用非电解电镀形成。下面表示在铝构成的垫片12上形成镍层(第一金属层30)的方法。
通过锌酸盐处理把垫片12的表面(铝)置换为锌。更具体说,各垫片12的表面上设置碱性锌溶液,把铝置换为锌。这种情况下,可把半导体芯片10浸渍到碱性锌溶液中。因此,最好预先把抗蚀剂层20在100到200度左右加热几分钟。由此,可提高抗蚀剂层20对强碱性溶液的耐蚀性。即,难以溶解抗蚀剂层20。为防止抗蚀剂层20热变形,可对抗蚀剂层20照射紫外线。紫外线最好以254nm为主波长,照射量可通过抗蚀剂层20的厚度调整。紫外线照射时,如果一边在减压下使抗蚀剂层20中包含的溶剂挥发一边进行照射更为有效。紫外线照射时,把抗蚀剂层20等在100到200度左右加热也是有效的。
把垫片12浸渍到碱性锌溶液之前,最好预先溶解芯片10的绝缘膜14的残余。另外,通过把半导体芯片10浸渍到弱氟酸溶液中,可溶解绝缘膜14的残余。在溶解绝缘膜14的残余后,把垫片12浸渍到碱性溶液,去除垫片12的露出部的氧化膜。这样一来,可确实露出垫片12的表面,把垫片12的表面的铝置换为锌。
垫片12的表面上析出锌时,可把垫片12浸渍到碱性锌溶液后,通过硝酸溶解置换的锌,再次浸渍到碱性锌溶液,以在垫片12上析出锌。这样,能在垫片12的表面上确实形成锌。
接着,把垫片12浸渍到非电解镍溶液中,通过贯通孔22形成镍层(第一金属层30)。这种情况下,可加热溶液。例如,PH4.5的非电解镍溶液加热到90度,在该溶液中把半导体芯片10浸渍45分钟左右,可形成厚度为20μm左右的镍层(第一金属层30)。第一金属层30厚度可在第一贯通孔22的高度以下,也可超出该高度形成。第一金属层30厚度由垫片12浸渍在溶液中的时间等自由确定。
垫片12和第一金属层30之间可以有其他金属层。例如,通过锌酸盐处理在垫片12上形成第一金属层30时,铝(垫片12)上的锌层部分残留,使第一金属层30和垫片12之间存有锌层。
或者与上述不同,也可设置包含钯等的还原剂的溶液,之后通过设置非电解镍溶液,以钯为核形成镍层(第一金属层30)。
根据至此的工序,残留为露出各垫片12而形成的抗蚀剂层20,在贯通孔22中形成第一金属层30。即,由于使用一次形成的抗蚀剂层20在绝缘膜14中形成开口部26,并形成与垫片12连接的第一金属层30,所以可用简单工序形成凸块。
如图4(A)所示,形成第一金属层30后,去除抗蚀剂层20。第一金属层30在上述工序中通过贯通孔22与其形状配合地形成。
如图4(B)所示,必要时,在第一金属层30的表面上形成第二金属层32。如图所示,第二金属层32可以是单层或多层。第二金属层32配合第一金属层30的形状形成。即,为不掩埋第一金属层30的凹部,最好第二金属层32较薄地形成。第二金属层32覆盖第一金属层30的表面形成。这样,防止第一金属层30的表面氧化。最好第二金属层32至少表面由含金的材料形成。
第二金属层32可用非电解电镀形成。例如,半导体芯片10浸渍到非电解金电镀溶液中,在镍层(第一金属层30)的表面上形成金属层(第二金属层32)。金属层(第二金属层32)只要形成在第一金属层30的表面上即可,其厚度无关紧要。例如,金层(第二金属层32)可以0.15μm左右厚度形成。
通过非电解电镀形成第一、第二金属层30、32时,把半导体芯片10浸渍到希望的溶液中的情况下,半导体芯片10的侧面和里面最好预先用保护膜覆盖。作为保护膜,可使用抗蚀剂层。这种情况下的抗蚀剂层可以是非感光性抗蚀剂。抗蚀剂层在半导体芯片10的侧面和里面上以2μm左右厚度形成。这样通过形成保护膜,防止通过浸渍到溶液生成的的半导体芯片10的各垫片12的电位变化。即,非电解电镀各垫片12的金属析出等处理可均匀化。
另外,把半导体芯片10浸渍到希望的溶液期间,最好避光进行。这样,可防止半导体芯片10的各垫片的电位变化。
这样一来,如图4(C)所示,形成第一和第二金属层30,32构成的凸块34。如图所示,第二金属层32上还可设置焊料40。焊料40设置在各个第二金属层32上。焊料40可以是焊锡。例如,通过把凸块34的上面(第二金属层32的一部分)浸渍到焊锡溶液中,在凸块34上形成焊锡球(焊料40)。焊锡由于附着于金属层(第二金属层32)而容易在凸块34上设置焊锡(焊料40)。焊锡例如由含锡和银材料形成。焊锡球(焊料40)的高度不限定,例如是15μm左右。半导体芯片10上设置焊料40的情况下,包含第一和第二金属层30,32和焊料40,也可叫作凸块。
图5是与凸块34(第一和第二金属层30,32)的半导体芯片10的平面视图平行的剖面图。如图所示,凸块34在侧面上有至少一个凹部36(容纳焊料40的区域)。具体说,通过第一金属层30配合贯通孔22的形状形成,而能借助抗蚀剂层20的突起部24(参考图2)使第一金属层30在一部分上按凹坑形成。第二金属层32配合第一金属层30的形状形成,第一金属层30的凹部部分作为凸块34的凹部36形成。
这样,凸块34上熔化焊料40时,焊料40进入凸块34的凹部36中。凹部36向着凸块34的内侧形成,所以可把焊料40吸收到凸块34的内侧。由此,防止在凸块34上设置的焊料40中的熔化的从凸块34流出的部分扩散到与半导体芯片10的面平行的方向(横向)上,从而可吸收到凸块34的高度方向(纵向)。因此,即使各垫片12之间间距狭窄,也不会向相邻的垫片12上流入焊料40,即不会短路,可使用焊料40。
如图所示,凸块34的凹部36也可以向着中央部位三角形的顶点以凹坑形成。或者向着凸块34的中央部位,以四角形或半圆形形状的凹坑形成,也可按其他形状形成。半导体芯片10的平面视图中,凸块34的一边为20微米左右,各垫片12的间距为40微米左右的情况下,凸块34的凹部36向着中央部位从端部开始以5微米左右的凹坑形成。这样,能有效吸收焊料40。
与图示的例子不同,凸块34的凹部36可仅在面向相邻的垫片12(凸块34)的侧上形成。例如,垫片12在半导体芯片10的端部形成1列的情况下,1个垫片12上的凸块34中,仅在朝向两邻的侧面上形成凹部36。由此,通过防止焊料40扩散到凸块34上的相邻的垫片12的方向上,可防止各垫片12的短路。各垫片12形成为例如矩阵状时,凸块34上的凹部36最好形成在所有侧上。
图6(A)~6(C)表示本实施例的变形例的凸块形成方法。本变形例中,第二金属层33的形式与上述不同。
如图6(A)所示,通过抗蚀剂层20的贯通孔22形成第二金属层33。即,在形成了抗蚀剂层20的状态下,在第一金属层30上面形成第二金属层33。第二金属层33至少表面用含金的材料形成。金层(第二金属层33)形成0.1微米左右。第二金属层33可用非电解电镀形成,用其他形成方法和形式如上所述。
如图6(B)所示,形成第二金属层33后,去除抗蚀剂层20。第一和第二金属层30,33在贯通孔22中配合其形状形成。
如图6(C)所示,形成在第一金属层30上面形成第二金属层33而构成的凸块35。换言之,凸块35仅在上面有例如金属层(第二金属层33)。由此,例如通过把凸块34浸渍在焊锡溶液中,仅凸块35的上面形成焊锡球(焊料40)。即,凸块35的侧面上不形成金属层(第二金属层33),熔化焊锡(焊料40)时,可更确切地防止焊锡从凸块35的侧面向横向扩散。
在上述的例子中,原样使用为了各垫片12从绝缘膜14露出来而使用的抗蚀剂层20来形成凸块34,但可与此不同,在剥离抗蚀剂层后,再重新形成抗蚀剂层来形成凸块34。这种情况下,首先形成的使绝缘膜14开口的抗蚀剂层的贯通孔可以是简单的角形或圆形。可通过把后面形成的形成金属层(例如第一金属层30)的抗蚀剂层形成为具有上述贯通孔22,来形成具有凹部36的凸块34。
根据本实施例的凸块形成方法,配合贯通孔22的形状把金属层(凸块34)形成规定形状。金属层(凸块34)具有容纳焊料40的区域。这样,焊料40进入到金属层(凸块34)的区域中,难以扩散到金属层(凸块34)外侧。即,例如防止金属层(凸块34)上熔化的焊料40流向相邻的垫片12。因此,垫片12之间不短路,后面的制造中成品率提高。
在由含铜材料构成垫片12的情况下,例如在铜上形成镍层(第一金属层30)的情况下,可在垫片12上设置包括钯等的还原剂的溶液,之后通过设置非电解电镀溶液,以靶为核形成镍层(第一金属层30)即可。
至此记载的技术和溶液只是一例,并不限定于此,例如非电解电镀使用的金属,也可以使用铜。
本实施例的半导体制造方法如图7所示,包括经焊料40将与半导体芯片10的多个垫片12连接而设置的金属层(第一和第二金属层30,32)和多个引线(配线图案52)接合起来的工序。这里金属层具有容纳焊料40的区域。金属层是通过上述形成方法形成凹部36的凸块34(第一和第二金属层30,32)。即容纳焊料40的区域与凸块34的凹部36相当。
各个凸块34经引线和焊料40之一电连接。引线是形成在基板50上的配线图案52。这种情况下,半导体芯片10可倒装焊接在基板50上。凸块34可与配线图案52的脊接合。
凸块34在与配线图案52接合时,通过凹部36吸收熔化的焊料40。更具体说,焊料40进入凸块34的凹部36中以防止扩散到相邻的垫片12(凸块34)。换言之,防止焊料40中的熔化的从凸块34流出的部分扩散到与半导体芯片10的面平行的方向(横向)上,从而可吸收到凸块34的高度方向(纵向)。因此,各垫片12之间不会短路,可提高半导体装置制造的成品率。
焊料40设置在半导体芯片10的凸块34侧后,将凸块34和配线图案52(脊)接合。或者预先在基板50的配线图案52(脊)上涂布,通过熔化时的焊料40的表面张力,将凸块34和配线图案52(脊)接合。
引线除上述之外可以是适用TAB技术时的内引线。还可以是能经焊料40接合的所有导电部件。
本实施例的半导体装置具有含多个垫片12的半导体芯片10、与各个垫片12连接的金属层(凸块34)、多个引线(配线图案52)。金属层具有焊料40进入内侧的区域。各个金属层经引线和焊料40之一接合。此时,在各金属层有容纳焊料40的区域。这里,金属层可以是上述的凸块34。焊料40的一部分进入到凸块34的凹部36中。其他结构如上所述。另外,引线可以是基板50上形成的配线图案52。
也可以在基板50上形成与配线图案52连接的外部端子54。例如经基板50上形成的图未示出的通孔形成与配线图案52连接的外部端子54。外部端子54可用焊锡球形成。或者,适用不主动形成外部端子54,在电路基板的配线图案上涂布焊锡油,通过熔化时的表面张力把半导体装置安装到电路基板上的方式。
根据本实施例,焊料40的一部分进入金属层(凸块34)的区域(凹部36)中,从而焊料40难以扩散到金属层外侧。即,可防止金属层上的熔化的焊料40流向相邻的垫片12。因此,垫片12之间不会短路,可提供可靠性提高的半导体装置。
(第二实施例)
图8~11是表示适用本发明的第二实施例的凸块形成方法的图。本实施例中,金属层(凸块74)的形成方法和形式不同。下面的实施例中,尽可能使用上述第一实施例中说明的内容。
如图8和图9(A)所示,半导体芯片10上形成抗蚀剂层60。抗蚀剂层60具有至少一部分(部分或全部)与1个垫片12平面重合的多个贯通孔62。多个贯通孔62可配置在垫片12的内侧,或者配置成从垫片12的外周伸出。为形成多个贯通孔62,垫片12的内侧上残留抗蚀剂层60的一部分64来形成。各个贯通孔62的形状如图所示可为矩形,或者也可以是圆形,并不特别限定。抗蚀剂层60的一部分64用于以后在金属层(第一和第二金属层70,72)形成区域76,按可使焊料40进入的那种程度的大小形成。此外,贯通孔62的配置和数目可考虑进入焊料40的大小自由确定。
如图9(B)所示,经抗蚀剂层60的多个贯通孔62去除绝缘膜14的一部分。具体说,通过各个贯通孔62,对于1个垫片12,绝缘膜14上形成多个开口部66。换言之,对于1个垫片12,形成多个露出的部分。因此,1个垫片12上形成与其连接的多个凸块。垫片12的多个露出的部分的大小不限定,例如按一边为20微米大小的角形形成1个露出部分。
如图9(C)所示,形成第一和第二金属层70,72。例如,可通过各个贯通孔62形成第一金属层70,之后去除抗蚀剂层60,覆盖第一金属层70表面形成第二金属层72。这样,形成包含第一和第二金属层70,72的凸块74。通过在1个垫片12上形成多个贯通孔62,可在1个垫片12上形成多个凸块74。
从而,如图所示,1个垫片12的相邻的凸块74之间形成区域76。具体说,通过残留抗蚀剂层60的一部分64形成凸块74的区域76。在去除抗蚀剂层60后形成第二金属层72时,最好第二金属层72按不掩埋区域76的程度形成得很薄。
第一和第二金属层70,72的形成方法以及其他结构可与上述相同。在本实施例中,也可如上述实施例所示,将第一金属层70形成为在侧面上至少具有1个凹部(参考图5)。
凸块74上可设置焊料80。焊料80可以是焊锡,与上述相同。可通过浸渍到焊锡溶液中在各个凸块74上设置焊锡。由此,通过在1个垫片12上形成多个凸块74,减少在凸块74上设置的焊锡,在与引线接合时,能抑制多余的焊锡的流出。
图10是与凸块74(第一和第二金属层70,72)的半导体芯片10的平面视图平行的横剖面图。1个垫片12上的相邻凸块74之间形成的区域76具有焊料80可进入的大小。区域76可根据抗蚀剂层60的贯通孔62的数目和配置自由确定。
根据本实施例,凸块74上熔化焊料80时,可防止焊料80扩散到凸块74外侧。具体说,通过1个垫片12的相邻的凸块74之间的区域76可吸收熔化流向凸块74外侧的焊料80的一部分。即,防止熔化的焊料80扩散到与半导体芯片10的面平行的方向(横向)上,从而可在凸块74的高度方向(纵向)上吸收。
图11是表示本实施例的变形例的凸块形成方法的图。如图所示,第二金属层73可在第一金属层70的上面形成。第二金属层73可通过抗蚀剂层60的多个贯通孔62形成。由此,凸块75的侧面上不形成金属层(第二金属层73),在熔化焊锡(焊料40)时,可确实防止焊锡从凸块75的侧面横向扩散。
(第三实施例)
图12(A)和图12(B)是表示适用本发明的第三实施例的凸块形成方法的图。本实施例中,金属层(凸块100)的形成方法和形式不同。
如图12(A)所示,在半导体芯片10上形成抗蚀剂层90。抗蚀剂层90具有至少一部分(部分或全部)与垫片12平面重合的贯通孔92。在半导体芯片10的平面视图中,把抗蚀剂层90的贯通孔92形成为在其中央部位残留一部分抗蚀剂层90。例如,把贯通孔92形成为包围中央部位(抗蚀剂层90的一部分94)的环状(环状)。
贯通孔92的形状可以是角形环状或是圆环状。抗蚀剂层90的一部分94用于形成以后形成的凸块100(包含第一和第二金属层)的区域(凹部102)。抗蚀剂层90的一部分94形成为凸块100确实可与垫片12连接的程度那样小,后面作为凸块100的凹部102,最好将其形成为可使焊料进入的程度那样大。
图12(B)是与凸块100的半导体芯片10的平面视图平行的横剖面图。凸块100在半导体芯片10的平面视图中形成为环状,在中央部位具有凹部102。凹部102是沿着凸块100的高度方向凹陷而成的。作为凹部102的底面,露出垫片12的一部分。凹部102的形状可以是圆形或角形。凹部102可以是1个或形成多个。
根据本实施例,通过凸块100的凹部102,可吸收熔化流向凸块100外侧的焊料的一部分。即,防止熔化的焊料扩散到与半导体芯片10的面平行的方向(横向)上,从而可在凸块74的高度方向(纵向)上吸收。通过在凸块100的中央部位形成凹部102,防止熔化的焊料偏向任一方向流向外侧。即可大致均匀地吸收多余的焊料。
可把上述实施例之一用于本实施例。即在本实施例中,在凸块100的侧面至少有1个凹部,或者把多个凸块100形成在1个垫片12上,或者组合它们来形成凸块。
图13表示安装本实施例的半导体装置1的电路基板200。电路基板200一般使用玻璃环氧基板、聚合膜等的有机基板、液晶显示基板等的玻璃基板。电路基板200上把例如铜等构成的配线图案形成为希望的电路,通过这些配线图案和半导体装置1的外部端子54机械连接,实现它们的电接通。
作为具有适用本发明的半导体装置1的电子设备,图14表示出笔记本电脑300,图15表示出便携电话400。
Claims (12)
1.一种凸块形成方法,其特征在于,包括:以具有贯通孔的方式在垫片上形成抗蚀剂层、配合贯通孔的形状形成与所述垫片电连接的金属层的工序,
以在所述贯通孔的内侧面上具有突起的方式形成所述抗蚀剂层。
2.一种凸块形成方法,其特征在于,包括:
以具有贯通孔的方式在垫片上形成抗蚀剂层的工序;
在形成了所述抗蚀剂层的状态下,配合贯通孔的形状形成与所述垫片电连接的第一金属层的工序,和
在形成了所述抗蚀剂层的状态下,在所述第一金属层上还配合贯通孔的形状形成与所述垫片电连接的第二金属层;
把所述第一和第二金属层形成为具有用于容纳焊料的区域的形状。
3.一种凸块形成方法,其特征在于,包括:
以具有贯通孔的方式在垫片上形成抗蚀剂层的工序;
在形成了所述抗蚀剂层的状态下,配合贯通孔的形状形成与所述垫片电连接的第一金属层的工序;
在去除所述抗蚀剂层后覆盖所述第一金属层的表面形成所述第二金属层;去除所述抗蚀剂层的工序;和
把所述第二和第二金属层形成为具有用于容纳焊料的区域的形状。
4.根据权利要求2或3的凸块形成方法,其特征在于,用绝缘膜覆盖所述垫片,把所述抗蚀剂层形成在所述绝缘膜上,在所述抗蚀剂层中形成所述贯通孔后,在所述绝缘膜上形成至少露出所述垫片的一部分的开口部,在形成了所述抗蚀剂层的状态下在所述垫片上形成所述第一金属层。
5.根据权利要求2或3的凸块形成方法,其特征在于,所述第一和第二金属层通过非电解电镀形成。
6.根据权利要求2或3的凸块形成方法,其特征在于,所述第一金属层由含镍材料形成。
7.根据权利要求2或3的凸块形成方法,其特征在于,所述第二金属层由含金的材料形成。
8.一种半导体装置的制造方法,其特征在于,包括:将在半导体芯片的多个垫片上设置的侧面上具有至少一个凹部的多个金属层和多个引线经所述焊料接合的工序,
在熔化所述焊料时,使所述焊料进入所述凹部中。
9.一种半导体芯片,其特征在于,具有多个垫片,和在各个所述垫片上形成、并在侧面上具有至少一个凹部的金属层。
10.一种半导体装置,其特征在于,包括:具有多个垫片的半导体芯片;设置在各个所述垫片上、并在侧面上以具有至少一个凹部的形状形成的金属层;和多个引线,各个所述金属层经任一所述引线和所述焊料接合,所述焊料的一部分进入所述凹部中。
11.一种装载半导体装置的电路基板,其特征在于,该半导体装置包括:具有多个垫片的半导体芯片;设置在各个所述垫片上、并在侧面上以具有至少一个凹部的形状形成的金属层;和多个引线,各个所述金属层经任一所述引线和所述焊料接合,所述焊料的一部分进入所述凹部中。
12.一种具有半导体装置的电子设备,其特征在于,该半导体装置包括:具有多个垫片的半导体芯片;设置在各个所述垫片上、并在侧面上以具有至少一个凹部的形状形成的金属层;和多个引线,各个所述金属层经任一所述引线和所述焊料接合,所述焊料的一部分进入所述凹部中。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP267076/2000 | 2000-09-04 | ||
JP2000267076A JP3700563B2 (ja) | 2000-09-04 | 2000-09-04 | バンプの形成方法及び半導体装置の製造方法 |
JP267076/00 | 2000-09-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1359147A CN1359147A (zh) | 2002-07-17 |
CN1197145C true CN1197145C (zh) | 2005-04-13 |
Family
ID=18754052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011412437A Expired - Fee Related CN1197145C (zh) | 2000-09-04 | 2001-09-04 | 凸块形成方法、半导体装置及其制造方法和半导体芯片 |
Country Status (4)
Country | Link |
---|---|
US (3) | US20020033531A1 (zh) |
JP (1) | JP3700563B2 (zh) |
CN (1) | CN1197145C (zh) |
TW (1) | TW506087B (zh) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3700563B2 (ja) * | 2000-09-04 | 2005-09-28 | セイコーエプソン株式会社 | バンプの形成方法及び半導体装置の製造方法 |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
JP2003203940A (ja) * | 2001-10-25 | 2003-07-18 | Seiko Epson Corp | 半導体チップ及び配線基板並びにこれらの製造方法、半導体ウエハ、半導体装置、回路基板並びに電子機器 |
CN1309067C (zh) * | 2003-09-24 | 2007-04-04 | 财团法人工业技术研究院 | 弹性凸块结构及其制造方法 |
JP2005223268A (ja) * | 2004-02-09 | 2005-08-18 | Seiko Epson Corp | 薄膜トランジスタの製造方法、ディスプレイの製造方法及びディスプレイ |
CN100361297C (zh) * | 2004-03-03 | 2008-01-09 | 友达光电股份有限公司 | 薄膜晶体管基板及制造方法 |
JP4646296B2 (ja) * | 2004-07-30 | 2011-03-09 | コーア株式会社 | 電子部品 |
WO2006051916A1 (ja) * | 2004-11-12 | 2006-05-18 | Murata Manufacturing Co., Ltd. | セラミック多層基板 |
US7952206B2 (en) * | 2005-09-27 | 2011-05-31 | Agere Systems Inc. | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore |
US8592977B2 (en) * | 2006-06-28 | 2013-11-26 | Megit Acquisition Corp. | Integrated circuit (IC) chip and method for fabricating the same |
KR101407614B1 (ko) * | 2008-01-30 | 2014-06-13 | 삼성전자주식회사 | 인쇄회로기판, 반도체 패키지, 카드 및 시스템 |
GB0807485D0 (en) * | 2008-04-24 | 2008-06-04 | Welding Inst | Method of applying a bump to a substrate |
KR101485105B1 (ko) * | 2008-07-15 | 2015-01-23 | 삼성전자주식회사 | 반도체 패키지 |
KR101036388B1 (ko) | 2008-08-19 | 2011-05-23 | 삼성전기주식회사 | 인쇄회로기판 및 이의 제조 방법 |
KR101096030B1 (ko) * | 2008-09-10 | 2011-12-19 | 주식회사 하이닉스반도체 | 반도체 칩 및 이를 이용한 반도체 패키지 |
DE102008042107A1 (de) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Elektronisches Bauteil sowie Verfahren zu seiner Herstellung |
US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
TWI455263B (zh) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | 晶片封裝結構及晶片封裝方法 |
US8536458B1 (en) | 2009-03-30 | 2013-09-17 | Amkor Technology, Inc. | Fine pitch copper pillar package and method |
JP5320165B2 (ja) * | 2009-05-27 | 2013-10-23 | パナソニック株式会社 | 半導体装置 |
US8377816B2 (en) * | 2009-07-30 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming electrical connections |
US9543262B1 (en) | 2009-08-18 | 2017-01-10 | Cypress Semiconductor Corporation | Self aligned bump passivation |
US8324738B2 (en) | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
US8659155B2 (en) | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
JP5685807B2 (ja) * | 2009-12-03 | 2015-03-18 | 富士通株式会社 | 電子装置 |
US8610270B2 (en) | 2010-02-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
TWI419284B (zh) * | 2010-05-26 | 2013-12-11 | Chipmos Technologies Inc | 晶片之凸塊結構及凸塊結構之製造方法 |
US9018758B2 (en) * | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
US20130020698A1 (en) * | 2011-07-22 | 2013-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar Design for Conductive Bump |
US9105533B2 (en) | 2011-07-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure having a single side recess |
US10833033B2 (en) | 2011-07-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bump structure having a side recess and semiconductor structure including the same |
US8853853B2 (en) * | 2011-07-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures |
KR20130116643A (ko) | 2012-04-16 | 2013-10-24 | 에스케이하이닉스 주식회사 | 범프를 갖는 기판, 반도체칩, 및 반도체 패키지와, 그 제조방법 |
US9373609B2 (en) * | 2012-10-18 | 2016-06-21 | Infineon Technologies Ag | Bump package and methods of formation thereof |
CN102945836B (zh) * | 2012-11-08 | 2016-03-16 | 南通富士通微电子股份有限公司 | 半导体封装结构 |
US9620468B2 (en) | 2012-11-08 | 2017-04-11 | Tongfu Microelectronics Co., Ltd. | Semiconductor packaging structure and method for forming the same |
CN102931111B (zh) * | 2012-11-08 | 2015-06-10 | 南通富士通微电子股份有限公司 | 半导体封装结构的形成方法 |
JP6045971B2 (ja) * | 2013-04-19 | 2016-12-14 | 新電元工業株式会社 | 半導体装置 |
US9768142B2 (en) * | 2013-07-17 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming bonding structures |
KR20160040988A (ko) | 2014-10-06 | 2016-04-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 단일 측부 리세스를 갖는 범프 구조물 |
JP6439389B2 (ja) | 2014-11-05 | 2018-12-19 | 富士電機株式会社 | 半導体装置 |
KR102248876B1 (ko) * | 2014-12-24 | 2021-05-07 | 엘지디스플레이 주식회사 | 표시장치 어레이 기판 및 표시장치 |
US10192840B2 (en) * | 2015-09-25 | 2019-01-29 | Intel Corporation | Ball pad with a plurality of lobes |
US20170141041A1 (en) * | 2015-11-12 | 2017-05-18 | Mediatek Inc. | Semiconductor package assembly |
KR102373440B1 (ko) * | 2017-03-17 | 2022-03-14 | 삼성디스플레이 주식회사 | 디스플레이 패널 및 이를 구비하는 디스플레이 장치 |
US11177229B2 (en) * | 2019-04-05 | 2021-11-16 | Synaptics Incorporated | IC chip layout for minimizing thermal expansion misalignment |
CN113823616A (zh) * | 2020-06-18 | 2021-12-21 | 华邦电子股份有限公司 | 导电柱凸块及其制造方法 |
US11764153B1 (en) * | 2022-07-28 | 2023-09-19 | Chun-Ming Lin | Interconnect structure and manufacturing method for the same |
US12087662B1 (en) | 2023-06-12 | 2024-09-10 | Chun-Ming Lin | Semiconductor package structure having thermal management structure |
CN117790445A (zh) * | 2022-09-19 | 2024-03-29 | 长鑫存储技术有限公司 | 一种半导体结构及其制备方法 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4205099A (en) | 1978-04-14 | 1980-05-27 | Sprague Electric Company | Method for making terminal bumps on semiconductor wafers |
JPS5574163A (en) * | 1978-11-29 | 1980-06-04 | Nec Corp | Semiconductor device |
JPS5851512A (ja) | 1981-09-22 | 1983-03-26 | Mitsubishi Electric Corp | 半導体装置の電極形成方法 |
JPS6031245A (ja) | 1983-08-01 | 1985-02-18 | Nec Corp | 半導体装置 |
US5310699A (en) * | 1984-08-28 | 1994-05-10 | Sharp Kabushiki Kaisha | Method of manufacturing a bump electrode |
JPH01191451A (ja) | 1988-01-27 | 1989-08-01 | Hitachi Ltd | 半導体装置の製造方法 |
US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
US5349495A (en) * | 1989-06-23 | 1994-09-20 | Vlsi Technology, Inc. | System for securing and electrically connecting a semiconductor chip to a substrate |
US5130275A (en) | 1990-07-02 | 1992-07-14 | Digital Equipment Corp. | Post fabrication processing of semiconductor chips |
JPH0513418A (ja) | 1991-07-04 | 1993-01-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH05335315A (ja) | 1992-06-02 | 1993-12-17 | Seiko Epson Corp | 電極の製造方法 |
JP2784122B2 (ja) | 1992-10-29 | 1998-08-06 | ローム株式会社 | 半導体装置の製法 |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
JP3263875B2 (ja) | 1993-08-24 | 2002-03-11 | ソニー株式会社 | 表面実装型電子部品の製造方法及び表面実装型電子部品 |
JPH0837190A (ja) * | 1994-07-22 | 1996-02-06 | Nec Corp | 半導体装置 |
JPH0997791A (ja) | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | バンプ構造、バンプの形成方法、実装接続体 |
JPH0917795A (ja) | 1995-06-30 | 1997-01-17 | New Japan Radio Co Ltd | バンプ構造 |
JP3201957B2 (ja) | 1996-06-27 | 2001-08-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 金属バンプ、金属バンプの製造方法、接続構造体 |
JPH10209210A (ja) * | 1997-01-20 | 1998-08-07 | Sharp Corp | 半導体装置及びその製造方法並びにその検査方法 |
JPH11111753A (ja) * | 1997-10-01 | 1999-04-23 | Mitsubishi Electric Corp | 半導体装置 |
US6130148A (en) | 1997-12-12 | 2000-10-10 | Farnworth; Warren M. | Interconnect for semiconductor components and method of fabrication |
JP3654485B2 (ja) | 1997-12-26 | 2005-06-02 | 富士通株式会社 | 半導体装置の製造方法 |
JP2000323534A (ja) * | 1999-05-13 | 2000-11-24 | Sony Corp | 半導体素子の実装構造及び実装方法 |
US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
US6414849B1 (en) * | 1999-10-29 | 2002-07-02 | Stmicroelectronics, Inc. | Low stress and low profile cavity down flip chip and wire bond BGA package |
US6191023B1 (en) | 1999-11-18 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of improving copper pad adhesion |
JP3700563B2 (ja) * | 2000-09-04 | 2005-09-28 | セイコーエプソン株式会社 | バンプの形成方法及び半導体装置の製造方法 |
-
2000
- 2000-09-04 JP JP2000267076A patent/JP3700563B2/ja not_active Expired - Fee Related
-
2001
- 2001-08-31 TW TW090121665A patent/TW506087B/zh not_active IP Right Cessation
- 2001-08-31 US US09/945,241 patent/US20020033531A1/en not_active Abandoned
- 2001-09-04 CN CNB011412437A patent/CN1197145C/zh not_active Expired - Fee Related
-
2004
- 2004-12-10 US US11/009,995 patent/US7355280B2/en not_active Expired - Lifetime
-
2007
- 2007-10-30 US US11/980,126 patent/US7579692B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW506087B (en) | 2002-10-11 |
US20050087863A1 (en) | 2005-04-28 |
JP2002076047A (ja) | 2002-03-15 |
US20080073783A1 (en) | 2008-03-27 |
US20020033531A1 (en) | 2002-03-21 |
US7579692B2 (en) | 2009-08-25 |
CN1359147A (zh) | 2002-07-17 |
US7355280B2 (en) | 2008-04-08 |
JP3700563B2 (ja) | 2005-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1197145C (zh) | 凸块形成方法、半导体装置及其制造方法和半导体芯片 | |
CN1198332C (zh) | 布线基片、半导体器件和布线基片的制造方法 | |
CN1841689A (zh) | 半导体器件及半导体器件制造方法 | |
CN1208830C (zh) | 半导体芯片与布线基板及制法、半导体晶片、半导体装置 | |
CN1645604A (zh) | 半导体装置及其制造方法 | |
CN1311528A (zh) | 半导体器件及其制造方法、电路板和电子装置 | |
CN1283002C (zh) | 连接端子及其制造方法以及半导体装置及其制造方法 | |
CN1805657A (zh) | 配线电路基板 | |
CN1574257A (zh) | 半导体装置及其制造方法 | |
CN1211835C (zh) | 缓冲垫的形成方法及半导体器件的制造方法 | |
CN1187806C (zh) | 电路装置的制造方法 | |
CN1604293A (zh) | 半导体装置的制造方法及半导体装置 | |
CN1521847A (zh) | 电子部件封装构件及其制造方法 | |
CN1832152A (zh) | 半导体封装及制造方法 | |
CN1956183A (zh) | 电子部件内置式基板及其制造方法 | |
CN1516898A (zh) | 半导体装置及其制造方法 | |
CN1707779A (zh) | 半导体装置 | |
CN1503359A (zh) | 电子元件封装结构及制造该电子元件封装结构的方法 | |
CN1976015A (zh) | 半导体器件及其制造方法和半导体晶片 | |
CN1767177A (zh) | 半导体器件以及电子设备 | |
CN1420527A (zh) | 半导体器件的制造方法 | |
CN1233205C (zh) | 电路装置的制造方法 | |
CN1672473A (zh) | 制造有内置器件的基板的方法、有内置器件的基板、制造印刷电路板的方法和印刷电路板 | |
CN1497717A (zh) | 电路装置及其制造方法 | |
US20080185711A1 (en) | Semiconductor package substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050413 Termination date: 20160904 |