CN1805657A - 配线电路基板 - Google Patents
配线电路基板 Download PDFInfo
- Publication number
- CN1805657A CN1805657A CNA2005101370793A CN200510137079A CN1805657A CN 1805657 A CN1805657 A CN 1805657A CN A2005101370793 A CNA2005101370793 A CN A2005101370793A CN 200510137079 A CN200510137079 A CN 200510137079A CN 1805657 A CN1805657 A CN 1805657A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- wired circuit
- butut
- terminal
- base insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims description 38
- 238000009434 installation Methods 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000003351 stiffener Substances 0.000 abstract description 32
- 238000000034 method Methods 0.000 abstract description 25
- 230000005855 radiation Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 36
- 239000004744 fabric Substances 0.000 description 25
- 239000000758 substrate Substances 0.000 description 22
- 229920001721 polyimide Polymers 0.000 description 19
- 239000009719 polyimide resin Substances 0.000 description 19
- 239000011248 coating agent Substances 0.000 description 15
- 238000000576 coating method Methods 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000009826 distribution Methods 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 10
- 239000002243 precursor Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920005575 poly(amic acid) Polymers 0.000 description 4
- 229920003002 synthetic resin Polymers 0.000 description 4
- 239000000057 synthetic resin Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 208000007578 phototoxic dermatitis Diseases 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 210000002469 basement membrane Anatomy 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002825 nitriles Chemical class 0.000 description 1
- -1 polyamidoimide Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005144 thermotropism Effects 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
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- H05K2201/09554—Via connected to metal substrate
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
为了提供即使通过倒装片安装方式安装半导体元件,也可以获得优异的散热性的配线电路基板,在对应于安装部7的绝缘层3形成基底开口部8和包围该基底开口部8的薄层部9,在薄层部9上配置端子部13的内侧端子部分15,同时在基底开口部8内形成接触加强板2的散热部17。由此,由于将内侧端子部分15的表面配置得比散热部17的表面低,可以使通过凸点25安装的半导体元件S和散热部17相互接近。因此,采用倒装片安装方式,可以将半导体元件S准确可靠地安装在配线电路基板上,同时可以将来自半导体元件S的热量通过散热部17高效地传导到加强板2,能够获得优异的散热性。
Description
技术领域
本发明涉及配线电路基板,具体涉及通过倒装片安装方式安装半导体元件的配线电路基板。
背景技术
半导体元件在配线电路基板上的安装方法已知引线接合安装方式、倒装片安装方式、各向异性导电膜安装方式等。
在这样的配线电路基板中,由于安装于配线电路基板的半导体元件因通电而发热,因此高效地散热变得重要,为此进行了各种的研究。
具体地,提出过例如对应于IC芯片的有源元件配置区域,将由铜箔配线构成的散热布图和配线布图一起设置,从IC芯片向热传导性电路基板高效地散热(参看例如日本专利特开2000-323525号公报)。
此外,提出过例如通过将与金属制基底导通的导体和不与金属制基底导通的导体用具有热传导性的热传导性元件连接,使电子元件产生的热量迅速扩散到金属制基底,从而提高散热性(参看例如日本专利特开平11-97818号公报)。
然而,在倒装片安装方式中,在导体布图的端子部预先设置焊锡或金构成的凸点(bump),通过该凸点在配线电路基板上安装半导体元件。因此,安装的半导体元件和配线电路基板的间隔由于隔着凸点而变大,所以存在即使设置散热布图和热传导性元件,也无法期待足够的散热效果的问题。
发明内容
本发明的目的在于提供即使通过倒装片安装方式安装半导体元件,也可以获得优异的散热性的配线电路基板。
本发明的配线电路基板,是具有金属支持层、形成于所述金属支持层上的形成开口部的基底绝缘层、形成于所述基底绝缘层上的含有用于与半导体元件连接的端子部的导体布图、安装所述半导体元件的安装部的配线电路基板,其特征在于,在所述安装部配置有所述开口部和所述端子部,在所述开口部设有与所述金属支持层接触的散热部,所述端子部的表面相对所述散热部的表面,更接近所述金属支持层侧地配置。
此外,本发明的配线电路基板中,较好是所述端子部的表面相对所述散热部的表面,更接近所述金属支持层侧地配置,两者相距1~15μm。
采用本发明的配线电路基板,端子部的表面相对散热部的表面,更接近金属支持层侧地配置,所以即使在端子部设置凸点,通过该凸点安装半导体元件,也由于端子部的表面相对散热部的表面,更接近金属支持层侧地配置,可以使安装的半导体元件和散热部相互接近。因此,可以通过倒装片安装方式将半导体元件准确可靠地安装在配线电路基板上,同时可以将来自半导体元件的热量通过散热部高效地传导到金属支持层,可以获得优异的散热性。
附图说明
图1是本发明的配线电路基板的一种实施方式的安装半导体元件的安装部的主要部分平面图。
图2是对应于图1的主要部分截面图。
图3是对应于图2的半导体元件安装状态的主要部分截面图。
图4是图1所示的配线电路基板的制造方法的工艺图,其中,
(a)是在加强板上以指定的布图形成基底绝缘层的步骤,
(b)是在基底绝缘层上形成导体布图和散热部的步骤,
(c)是在基底绝缘层上以指定的布图形成覆盖绝缘层,使其覆盖端子部以外的导体布图的步骤,
(d)是在端子部形成电镀层的步骤,
(e)是蚀刻加强板,留下配线电路基板中设有安装部的部分的步骤。
图5是说明在图4(a)中,在加强板上以指定的布图形成基底绝缘层的步骤的工艺图,其中,
(a)是准备加强板的步骤,
(b)是在加强板的整面形成感光性聚酰亚胺树脂前体的被膜的步骤,
(c)是将被膜隔着光掩模曝光的步骤,
(d)是将曝光的被膜显影的步骤,
(e)是使被膜固化的步骤。
图6是说明在图4(b)中,在基底绝缘层上形成导体布图和散热部的步骤的工艺图,其中,
(a)是在基底绝缘层整面形成金属薄膜的步骤,
(b)是在金属薄膜的表面形成抗镀膜的步骤,
(c)是在从抗镀膜露出的金属薄膜的表面形成导体布图和散热部的步骤,
(d)是除去抗电镀层的步骤,
(e)是除去从导体布图和散热部露出的金属薄膜的步骤。
图7是说明在图4(c)中,在基底绝缘层上以指定的布图形成覆盖绝缘层,使其覆盖端子部以外的导体布图的步骤的工艺图,其中,
(a)是在含有导体布图和散热部的基底绝缘层的整面形成被膜的步骤,
(b)是将被膜隔着光掩模曝光的步骤,
(c)是将曝光的被膜显影的步骤,
(d)是使被膜固化的步骤。
具体实施方式
图1是本发明的配线电路基板的一种实施方式的安装半导体元件的安装部的主要部分平面图,图2是对应于图1的主要部分截面图,图3是对应于图2的半导体元件安装状态的主要部分截面图。
如图2所示,该配线电路基板1由柔性基板构成,具有作为金属支持层的加强板2、形成于加强板2上的基底绝缘层3、形成于基底绝缘层3上的导体布图4、在基底绝缘层3上形成的覆盖导体布图4的覆盖绝缘层5。
此外,在该配线电路基板1中,如图1所示,在覆盖绝缘层5中的特定部分形成俯视呈大致矩形的形状开口的覆盖层开口部6,将该覆盖层开口部6内作为用于安装半导体元件S(参见图3)的安装部7。
加强板2为了加强基底绝缘层3而设置于配线电路基板1中设置安装部7的部分。加强板2的厚度为,例如15~150μm,较好为18~30μm。
基底绝缘层3,呈沿配线电路基板1的长度方向伸展的带状,除了后述的薄层部9外,以例如3~20μm,较好为7~12μm的均一的厚度(该厚度相当于后述的外侧厚层部10和内侧厚层部11的厚度)形成。
在安装部7中,在基底绝缘层3,如图2所示,形成以俯视呈大致矩形的形状开口的基底开口部8,此外,围着该基底开口部8形成薄层部9。
基底开口部8在安装部7的中央部分,贯穿基底绝缘层3的厚度方向地,以与安装部7大致相似的形状形成。
薄层部9在覆盖层开口部6的周缘和基底开口部8之间,围着该基底开口部8以俯视呈大致矩形框的形状形成。更具体地,该薄层部9在距覆盖层开口部6的周缘指定间隔(后述外侧厚层部10)的内侧和距基底开口部8的周缘指定间隔(后述内侧厚层部10)的外侧之间形成。该薄层部9的厚度为例如1~15μm,较好为1~8μm。
由此,基底绝缘层3在安装部7中,如图1所示,从外侧方向(周缘)到内侧方向(中央部分)依次形成俯视呈大致矩形框的形状的外侧厚层部10、位于该外侧厚层部10的内侧的薄层部9、位于该薄层部9内侧的俯视呈大致矩形框的形状的内侧厚层部11、位于该内侧厚层部11的内侧的基底开口部8。
导体布图4由多条配线12构成,在基底绝缘层3上以对应于其目的和用途的布图形成。导体布图4的厚度为例如3~20μm。
在安装部7中,从覆盖层开口部6露出的导体布图4作为与半导体元件S连接的端子部13。
端子部13以从覆盖层开口部6的周缘的各边(四边)向内侧(基底开口部8)延伸的布图形成。更具体地,端子部13由在从覆盖层开口部6的周缘的各边(四边)向内侧延伸的4个部分中,互相隔开平行配置的多条配线12构成,各配线12的宽度W1设定为10~300μm,各配线12间的间隔W2设定为10~300μm。此外,各配线12的游离端配置于薄层部9,形成用于连接半导体元件S的圆连接盘。
此外,端子部13,如图2所示,在各配线12中,形成于外侧厚层部10上的外侧端子部分14和形成于薄层部9上的内侧端子部分15介于向下弯折的台阶部分16从外侧端子部分14向内侧端子部分15连续形成。
覆盖绝缘层5如上所述在基底绝缘层3上形成覆盖导体布图4,且在安装部7中形成覆盖层开口部6。覆盖绝缘层5的厚度为例如3~15μm。
此外,在该配线电路基板1的安装部7中,设有用于发散来自半导体元件S的热量的散热部17。
散热部17呈俯视呈大致矩形的形状,在安装部7的基底开口部8内形成于加强板2上。该散热部17,其下端与加强板2接触,其上端从基底开口部8向上膨大凸出,以截面为大致T形的形状形成,承载在内侧厚层部11的上端面。散热部17的厚度(从与加强板2接触的下表面到上表面的高度)为例如6~40μm,较好为10~30μm。
由此,散热部17,如图1所示,配置于从覆盖层开口部6的周缘的各边(四边)向内侧(基底开口部8)延伸的端子部13的各配线12的中心,换言之,端子部13的各配线12是围着散热部17的四周配置的。
此外,如图2所示,散热部17的表面和外侧端子部分14的表面比内侧端子部分15的表面配置得更高(在覆盖绝缘层5侧)。换言之,内侧端子部分15的表面比散热部17的表面和外侧端子部分14的表面配置得更低(在加强板2侧)。更具体地,散热部17的表面和外侧端子部分14的表面与内侧端子部分15的表面之间的上下方向的间隔G设定为例如1~15μm。
散热部17的表面和外侧端子部分14的表面以大致同样的高度形成。
此外,端子部13的各配线12的表面和散热部17的表面上形成由镍或金等构成的电镀层18。电镀层18由例如厚1~5μm的镍电镀层或厚0.05~5μm的金电镀层形成。
接着,参见图4~图7,对该配线电路基板1的制造方法进行说明。图4~图7中,以对应图2的截面表示。
该方法中,首先,如图4(a)所示,在加强板2上以指定的布图形成基底绝缘层3。
加强板2使用金属箔或金属薄板,所述金属可以使用例如不锈钢、42合金、铝、铜-铍、磷青铜等。从刚性、耐蚀性和加工性的观点来看,较好为使用不锈钢箔。
此外,用于形成基底绝缘层3的绝缘材料并没有特别限定,可以使用例如聚酰亚胺树脂、聚酰胺酰亚胺、丙烯酸树脂、聚醚腈树脂、聚醚砜树脂、聚对苯二甲酸乙二醇酯树脂、聚萘二甲酸乙二醇酯、聚氯乙烯树脂等合成树脂。其中,从耐热性和耐化学腐蚀性上看,较好是采用聚酰亚胺树脂。此外,从布图精细加工的简单易行性上看,较好是采用感光性的合成树脂,更好是采用感光性聚酰亚胺树脂。
例如,使用感光性聚酰亚胺树脂,在加强板2上以指定的布图形成基底绝缘层3的情况下,首先,如图5(a)所示,准备加强板2,接着,如图5(b)所示,在该加强板2的整面涂布感光性聚酰亚胺树脂的前体(感光性聚酰胺酸树脂)的清漆后,以例如60~150℃,较好为80~120℃的温度加热,形成感光性聚酰亚胺树脂的前体的被膜19。
然后,如图5(c)所示,将该被膜19隔着光掩模20曝光。光掩模20以指定的布图具有遮光部分20a、半透光部分20b和全透光部分20c。在半透光部分20b中,光以选自1~99%的适当的光透过率透过。
然后,将光掩模20与被膜19对向配置,使遮光部分20a相对加强板2中形成基底绝缘层3的基底开口部8的部分,半透光部分20b相对加强板2中形成基底绝缘层3的薄层部9的部分,全透光部分20c相对加强板2中形成薄层部9以外的基底绝缘层3的部分(包括外侧厚层部10和内侧厚层部11)。
此外,隔着光掩模20照射的光(照射光),其曝光波长为例如300~450nm,其曝光累计光量为例如100~2000mJ/cm2。
接着,如图5(d)所示,将曝光后的被膜19根据需要加热到指定温度后显影。被照射的被膜19的曝光部分,通过例如在130℃以上150℃以下的温度下进行加热,在接着的显影中可溶化(正型),或者通过例如在150℃以上200℃以下的温度下进行加热,在接着的显影中不溶化(负型)。
此外,在显影中,可以使用例如使用碱性显影液等公知的显影液的浸渍法和喷涂法等公知的方法。在本方法中,较好为以负型形成布图,在图5中,以负型形成布图。
通过所述显影,被膜19中残存光掩模20的全透光部分20c相对的部分(包括外侧厚层部10和内侧厚层部11),光掩模20的遮光部分20a相对的形成基底开口部8的部分溶解,同时光掩模20的半透光部分20b相对的形成薄层部9的部分以对应于光透过率的比例溶解,并残存一部分,由此使被膜9形成指定的布图。
接着,如图5(e)所示,将形成指定的布图的被膜19,通过加热到例如最终温度250℃以上,使其固化(酰亚胺化)。由此,由聚酰亚胺树脂构成的基底绝缘层3形成为指定的布图,布图中在对应安装部7的部分形成外侧厚层部10、薄层部9、内侧厚层部11和基底开口部8。
在不使用感光性的合成树脂的情况下,例如将干膜热粘接或根据需要通过粘接剂层粘接在加强板2上后,通过使用等离子体或激光的干法蚀刻或者使用碱性水溶液的湿法蚀刻等,形成指定的布图,布图中在对应安装部7的部分形成外侧厚层部10、薄层部9、内侧厚层部11和基底开口部8。
接着,在本方法中,如图4(b)所示,同时形成导体布图4和散热部17。用于形成导体布图4和散热部17的导体材料没有特别限定,可以使用例如铜、镍、金、焊锡或者它们的合金等,从导电性、经济性和加工性的观点来看,较好为使用铜。
此外,导体布图4和散热部17的形成使用减成法(subtractive method)或加成法(additive method)等公知的布图形成法。为了以精细间距精细地形成导体布图4,较好为使用加成法。
加成法中,首先,如图6(a)所示,在基底绝缘层3的整面,形成金属薄膜21作为基膜。用于形成金属薄膜21的金属材料可以使用例如铬、镍、铜或它们的合金等。此外,金属薄膜21的形成没有特别限定,可以使用例如溅射法等真空蒸镀法。金属薄膜21的厚度为例如100~3000。此外,金属薄膜21也可以例如通过溅射法依次形成铬薄膜和铜薄膜,形成多层。
接着,在加成法中,如图6(b)所示,在金属薄膜21的表面以导体布图4和散热部17的反转布图形成抗镀膜22。
抗镀膜22使用例如干膜抗蚀膜,通过公知的方法,形成上述的导体布图4和散热部17的反转布图。
接着,在加成法中,如图6(c)所示,在从抗镀膜22露出的金属薄膜21的表面,同时形成导体布图4和散热部17。导体布图4和散热部17的形成没有特别限定,可以使用例如电解电镀,较好为电解镀铜。
然后,如图6(d)所示,除去抗镀膜22。抗镀膜22的除去使用例如化学蚀刻(湿法蚀刻)等公知的蚀刻法,或者剥离。
然后,如图6(e)所示,除去从导体布图4和散热部17露出的金属薄膜21。金属薄膜21的除去使用例如化学蚀刻(湿法蚀刻)。
由此,形成包括上述端子部13的导体布图4和散热部17。在图2和图3中,图6所示的金属薄膜21略去。
接着,在本方法中,如图4(c)所示,在基底绝缘层3上以指定的布图形成覆盖绝缘层5,被覆端子部13以外的导体布图4。
用于形成覆盖绝缘层5的绝缘材料可以使用和基底绝缘层3同样的绝缘材料,较好为使用感光性聚酰亚胺树脂。
然后,例如为了使用感光性聚酰亚胺树脂,在基底绝缘层3上以指定的布图形成覆盖绝缘层5,首先,如图7(a)所示,在包括导体布图4的基底绝缘层3的整面涂布感光性聚酰亚胺树脂的前体(感光性聚酰胺酸树脂)的溶液后,以例如60~150℃,较好为80~120℃的温度加热,形成感光性聚酰亚胺树脂的前体的被膜23。
接着,如图7(b)所示,将该被膜23隔着光掩模24曝光。光掩模23以指定的布图具有遮光部分24a和全透光部分24b。
然后,将光掩模24与被膜23对向配置,使遮光部分24a相对被膜23中对应覆盖绝缘层5的覆盖层开口部6的部分,全透光部分24b相对其他部分。接着,与上述被膜19的曝光一样进行曝光。
接着,如图7(c)所示,将曝光后的被膜23与上述被膜19的显影一样进行显影。在图7中,以负型形成布图。
通过所述显影,被膜23中光掩模24的遮光部分24a相对的对应于覆盖层开口部6的部分溶解,形成露出安装部7的指定的布图。
接着,如图7(d)所示,将形成指定的布图的被膜23,通过加热到例如最终温度250℃以上,使其固化(酰亚胺化)。由此,由聚酰亚胺树脂构成的覆盖绝缘层5形成为指定的布图,布图中从覆盖层开口部6露出安装部7,配置于该安装部7的端子部13外的导体布图4被覆盖。
在不使用感光性的合成树脂的情况下,例如将干膜热粘接或根据需要通过粘接剂层粘接在基底绝缘层3上后,通过使用等离子体或激光的干法蚀刻或者使用碱性水溶液的湿法蚀刻等,形成指定的布图,布图中从覆盖层开口部6露出安装部7,配置于该安装部7的端子部13外的导体布图4被覆盖。
接着,在本方法中,如图4(d)所示,在端子部13和散热部17形成用于被覆保护其表面的电镀层18。用于形成电镀层18的电镀层材料没有特别限定,可以使用例如镍或金等。此外,电镀层18例如以抗镀膜被覆除端子部13和散热部17的表面外的部分,通过电解电镀或无电解镀形成。此外,电镀层18也可以通过依次镀镍和金,形成多层。
接着,在本方法中,如图4(e)所示,对加强板2进行蚀刻,留下配线电路基板1中设置安装部7的部分。该蚀刻中,例如以抗蚀膜被覆后,用氯化铁溶液对要留下的部分进行湿法蚀刻。
然后,在这样得到的配线电路基板1中,如上所述,在安装部7中,将包围散热部17的内侧端子部分15的表面设置得比该散热部17的表面低。因此,如图3所示,即使在内侧端子部分15的表面设置由金或焊锡等构成的凸点25,通过该凸点25安装半导体元件S,也由于将内侧端子部分15的表面配置得比散热部17的表面低,可以使安装的半导体元件S和散热部17相互接近。因此,采用这样的倒装片安装方式,可以将半导体元件S准确可靠地安装在配线电路基板上,同时可以将来自半导体元件S的热量通过散热部17高效地传导到加强板2,能够获得优异的散热性。
以下列举实施例和比较例,对本发明进一步进行详细说明,但本发明并不局限于某一个实施例。
实施例1
准备厚20μm的不锈钢(SUS304)箔构成的加强板2(参见图5(a))。
接着,在加强板2的整面涂布感光性聚酰亚胺树脂的前体(感光性聚酰胺酸树脂)的溶液后,以120℃加热2分钟,形成感光性聚酰亚胺树脂的前体构成的被膜19(参见图5(b))。
然后,将光掩模20与被膜19对向配置,使遮光部分20a相对加强板2中形成基底绝缘层3的基底开口部8的部分,半透光部分20b相对加强板2中形成基底绝缘层3的薄层部9的部分,全透光部分20c相对加强板2中形成薄层部9以外的基底绝缘层3的部分,将被膜19以紫外线(曝光累计光量720mJ/cm2)曝光(参见图5(c))。
接着,将曝光后的被膜19加热(160℃,3分钟)后,通过用碱性显影液显影,使被膜19形成指定的布图,布图中形成有基底开口部8和薄层部9(参见图5(d))。然后,通过将被膜19以420℃加热,形成由聚酰亚胺树脂构成的厚10μm的基底绝缘层3(薄层部厚5μm)(参见图5(e))。基底开口部8形成为边长2μm的俯视呈正方形的开口。
接着,在基底绝缘层3的整面,通过溅射法依次形成铬薄膜和铜薄膜,形成厚2000的金属薄膜21(参见图6(a))。然后,在金属薄膜21的表面层合干膜抗蚀膜,以紫外线(曝光累计光量235mJ/cm2)曝光后,通过用碱性显影液显影,形成导体布图4和散热部17的反转布图的抗镀膜22(参见图6(b))。
接着,在从抗镀膜22露出的金属薄膜21的表面,通过电解镀铜形成厚10μm的导体布图4和散热部17后(参见图6(c)),剥离抗镀膜22(参见图6(d)),接着,将从导体布图4和散热部17露出的金属薄膜21通过化学蚀刻除去(参见图6(e))。
接着,在导体布图4和基底绝缘层3的整面涂布感光性聚酰亚胺树脂的前体(感光性聚酰胺酸树脂)的溶液后,以120℃加热2分钟,形成感光性聚酰亚胺树脂的前体的被膜23(参见图7(a))。
然后,将光掩模24与被膜23对向配置,使遮光部分24a相对对应于覆盖绝缘层5的覆盖层开口部6的部分,全透光部分24b相对其他部分,将被膜23以(曝光累计光量720mJ/cm2)曝光(参见图7(b))。
接着,将曝光后的被膜23加热(160℃,3分钟)后,通过用碱性显影液显影,使被膜23形成指定的布图,布图中从覆盖层开口部6露出安装部7,配置于该安装部7的端子部13外的导体布图4被覆盖(参见图7(c))。然后,通过将被膜23以420℃加热,形成由聚酰亚胺树脂构成的厚3μm的覆盖绝缘层5(参见图7(d))。
然后,在端子部13通过无电解镀金,形成厚0.1μm的电镀层18(参见图4(d))后,通过对加强板2用氯化铁溶液进行湿法蚀刻,留下配线电路基板1中设置安装部7的部分(参见图4(e)),得到配线电路基板1。
得到的配线电路基板1中,内侧端子部分15的表面设置得比该散热部17的表面低5μm。
比较例1
在基底绝缘层3的形成中,除了不形成薄层部9,形成均一厚度的基底绝缘层3之外,采用与实施例1同样的方法形成配线电路基板。
得到的配线电路基板中,内侧端子部分15的表面和散热部17的表面配置为同样高度。
在实施例1和比较例1中得到的配线电路基板的安装部,通过金凸点以倒装片安装方式安装半导体元件。然后,向半导体元件通电。在实施例1的配线电路基板中,散热性良好,半导体元件工作良好,但在比较例1的配线电路基板中,散热性不佳,会对半导体元件的工作产生干扰。
提供上述说明作为本发明的示例的实施方式,但这只是单纯的示例,并不是限定性的解释。对于该技术领域的从业者显而易见的本发明的变形例也包含在后述的权利要求的范围内。
Claims (2)
1.配线电路基板,所述配线电路基板是具有金属支持层、形成于所述金属支持层上的形成开口部的基底绝缘层、形成于所述基底绝缘层上的含有用于与半导体元件连接的端子部的导体布图、安装所述半导体元件的安装部的配线电路基板,其特征在于,
在所述安装部配置有所述开口部和所述端子部,
在所述开口部设有与所述金属支持层接触的散热部,
所述端子部的表面相对所述散热部的表面,更接近所述金属支持层侧地配置。
2.如权利要求1所述的配线电路基板,其特征还在于,所述端子部的表面相对所述散热部的表面,更接近所述金属支持层侧地配置,两者相距1~15μm。
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CN101399248B (zh) * | 2007-09-27 | 2011-12-28 | 新光电气工业株式会社 | 配线基板及其制造的方法 |
CN104810322A (zh) * | 2015-05-18 | 2015-07-29 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示面板、显示装置、掩模板 |
CN109073680A (zh) * | 2016-05-06 | 2018-12-21 | 日本麦可罗尼克斯股份有限公司 | 多层布线基板和使用该多层布线基板的探针卡 |
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CN101399248B (zh) * | 2007-09-27 | 2011-12-28 | 新光电气工业株式会社 | 配线基板及其制造的方法 |
CN104810322A (zh) * | 2015-05-18 | 2015-07-29 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示面板、显示装置、掩模板 |
CN109073680A (zh) * | 2016-05-06 | 2018-12-21 | 日本麦可罗尼克斯股份有限公司 | 多层布线基板和使用该多层布线基板的探针卡 |
CN109073680B (zh) * | 2016-05-06 | 2021-01-05 | 日本麦可罗尼克斯股份有限公司 | 多层布线基板和使用该多层布线基板的探针卡 |
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