CN1521847A - 电子部件封装构件及其制造方法 - Google Patents
电子部件封装构件及其制造方法 Download PDFInfo
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- CN1521847A CN1521847A CNA2004100049508A CN200410004950A CN1521847A CN 1521847 A CN1521847 A CN 1521847A CN A2004100049508 A CNA2004100049508 A CN A2004100049508A CN 200410004950 A CN200410004950 A CN 200410004950A CN 1521847 A CN1521847 A CN 1521847A
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Abstract
本发明的电子部件封装构件包括:具有布线图案的布线基底;在布线基底上形成的第一绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;电子部件,它的连接端子倒装安装到暴露于第一绝缘膜开口部分中的布线图案上;用于覆盖电子部件的第二绝缘膜;在布线图案上的第一和第二绝缘膜的预定部分中形成的通孔;以及在第二绝缘膜上形成的上布线图案,上布线图案通过通孔连接到所述布线图案。
Description
技术领域
本发明涉及一种电子部件封装构件及其制造方法。更具体地,本发明涉及其中半导体芯片等以埋藏于绝缘膜中的状态安装在布线基底上的电子部件封装构件及其制造方法。
背景技术
LSI技术是实现多媒体器件的关键技术,LSI技术稳定地发展为更高速度和更大容量的数据传送。据此,对于LSI和电子器件之间的接口,也要求更高密度的封装技术。
基于对进一步增加密度的需求,已经开发以下半导体器件,在此器件中,多个半导体芯片是三维层叠的并且安装在布线基底上。例如,专利文献1(未经审查的日本专利公开号2001-177045)和专利文献2(未经审查的日本专利公开号2000-323645)公开了具有以下结构的半导体器件:多个半导体芯片以埋藏于绝缘膜中的状态而三维安装在布线基底上,并且,多个半导体芯片用多层布线图案等相互连接,其中,在多层布线图案等之间插入有绝缘膜。
然而,在上述专利文献1和2中,没有考虑以下事实:当在安装的半导体芯片上形成层间绝缘膜时,层间绝缘膜在因半导体芯片厚度而产生台阶的状态下形成。
具体地,如果在半导体芯片上的层间绝缘膜中产生台阶,当在层间绝缘膜上形成布线图案时,在光刻方法中容易发生散焦。相应地,难以高精度地形成所需布线图案。
进而,由于还在形成于层间绝缘膜上的布线图案中产生台阶,因此,当半导体芯片倒装接合到该布线图案时,接合的可靠性可能降低。
发明内容
本发明的目的是提供一种具有以下结构的电子部件封装构件及其制造方法,在此结构中,电子部件埋藏于布线基底上的绝缘膜中,其中,容易消除因电子部件厚度而产生的台阶,以平面化。
本发明涉及一种电子部件封装构件,包括:具有布线图案的布线基底;在布线基底上形成的第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;电子部件,其连接端子倒装安装在第一绝缘膜的开口部分的布线图案上;用于覆盖电子部件的第二绝缘膜;在布线图案上的第一和第二绝缘膜的预定部分中形成的通孔;以及在第二绝缘膜上形成的上布线图案,上布线图案通过通孔连接到所述布线图案。
在本发明中,在布线基底上形成第一绝缘膜,第一绝缘膜在封装区域中具有开口部分,并且,电子部件(较薄的半导体芯片等)的连接端子倒装安装到开口部分中的布线图案上。而且,形成用于覆盖电子部件的第二绝缘膜,并且在布线图案上的第一和第二绝缘膜中形成通孔。进而,在第二绝缘膜上形成通过通孔连接到所述布线图案的上布线图案。
如上所述,在本发明中,第一绝缘膜形成得围绕电子部件。从而,本发明具有用第一绝缘膜消除因电子部件厚度而产生的台阶的结构。相应地,用于覆盖电子部件的第二绝缘膜以第二绝缘膜上表面为平面的状态形成,不受电子部件厚度的影响。
从而,由于当形成上布线图案时在光刻方法中不发生散焦,因此,高精度地稳定形成上布线图案。
因而,电子部件以埋藏于平面绝缘膜中的状态倒装安装在布线图案上,并且在第二绝缘膜上形成用于三维层叠多个电子部件的上布线图案,而不会产生任何问题。进而,在上电子部件倒装安装在上布线图案上的情况下,上布线图案的连接部分设置在基本相同的高度。相应地,上电子部件高度可靠地接合到上布线图案。
对于上述发明的修改例,通过在电子部件的背部设置保护膜而省略第二绝缘膜。在此情况下,在第一绝缘膜和保护膜上形成上布线图案。可替换地,可采用以下结构:不在布线图案上的绝缘膜中形成通孔,而在连接端子上的电子部件的预定部分中形成贯穿电子部件的通孔,并且,上布线图案通过电子部件的通孔而连接到连接端子。
在上述发明的一个优选方面中,采用以下结构:电子部件的连接端子由金制成,在绝缘膜的开口部分中在布线图案表面上形成金膜,并且,电子部件的连接端子通过金-金接合而倒装安装到布线图案上。
在此情况下,用于消除因电子部件厚度而产生的台阶的第一绝缘膜还作为掩蔽层,用于有选择性地在第一树脂膜的开口部分(封装区域)中的布线图案(铜线等)上形成金膜。这使得有可能通过提供高可靠性接合的金-金接合,而容易在布线图案上倒装安装其连接端子由金制成的电子部件。
而且,本发明涉及以下电子部件封装构件,包括:具有布线图案的布线基底;在布线基底上形成的第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;电子部件,该部件以连接端子朝上的状态安装在第一绝缘膜的开口部分的封装区域中;用于覆盖电子部件的第二绝缘膜;分别在连接端子和布线图案上的绝缘膜预定部分中形成的通孔;以及在第二绝缘膜上形成的上布线图案,上布线图案通过通孔而分别连接到连接端子和所述布线图案。在本发明中,在布线基底上形成第一绝缘膜,第一绝缘膜在封装区域中具有开口部分,并且,电子部件以连接端子朝上的状态安装在开口部分中。
在电子部件以此方式安装的情况下,与上述发明相似,也容易用第一绝缘膜消除因电子部件厚度而产生的台阶。进而,在用于覆盖电子部件的第二绝缘膜以平面状态形成之后,分别在连接端子和布线图案上的第二绝缘膜预定部分中形成通孔。另外,在第二绝缘膜上高精度地稳定形成上布线图案,上布线图案通过通孔而分别连接到连接端子和所述布线图案。
对于上述发明的修改例,通过使用在元件形成表面上设置有钝化膜的电子部件而省略用于覆盖电子部件的第二绝缘膜,钝化膜具有用于暴露连接端子的开口部分。在此情况下,在绝缘膜和钝化膜上形成上布线图案。
附图说明
图1A-1N为顺序示出本发明第一实施例的电子部件封装构件的制造方法的剖面图。
图2A-2F为顺序示出本发明第二实施例的电子部件封装构件的制造方法的剖面图。
图3A-3E为示出本发明第三实施例的电子部件封装构件的制造方法的剖面图,并且图4为示出本发明第三实施例之修改例的电子部件封装构件的剖面图。
图5A-5G为顺序示出本发明第四实施例的电子部件封装构件的制造方法的剖面图,并且图6为示出本发明第四实施例之修改例的电子部件封装构件的剖面图。
具体实施方式
以下结合附图描述本发明的实施例。
(第一实施例)
图1A-1N为顺序示出本发明第一实施例的电子部件封装构件的制造方法的剖面图。在制造第一实施例的电子部件封装构件的方法中,如图1A所示,首先,制备用于制造装配印刷电路板的基底30。基底30由绝缘材料如树脂制成。在基底30中设置通孔30a,并且,在通孔30a的内表面上形成通孔镀层30b,通孔镀层30b连接到基底30上的第一布线图案32。通孔30a的开口用树脂体30c填充。
随后,形成第一层间绝缘膜34,此膜由树脂等制成并覆盖第一布线图案32。接着,用激光、RIE等蚀刻第一布线图案32上的第一层间绝缘膜34的预定部分,由此形成其深度达到第一布线图案32的第一通孔34x。
然后,在第一层间绝缘膜34上形成通过第一通孔34x连接到第一布线图案32的第二布线图案32a。第二布线图案32a由Cu线等制成,并且用与形成后述第三布线图案的方法相似的方法形成。因而,获得其上安装半导体芯片的布线基底2。
其次,如图1B所示,在第二布线图案32a和第一层间绝缘膜34上形成第一绝缘膜36a,其中,第一绝缘膜36a在倒装安装半导体芯片的封装区域A中具有开口部分39。
对于第一绝缘膜36a,使用环氧类树脂、聚酰亚胺类树脂、酚醛清漆类树脂、丙烯酸类树脂、等等。形成第一绝缘膜36a的方法包括用光刻术对感光树脂膜构图的方法。可替换地,可采用以下方法,其中:层压膜状树脂层而形成,或通过自旋涂敷或印刷形成树脂膜;接着,用激光或RIE蚀刻树脂膜,由此形成开口部分。而且,可采用以下方法,其中:膜状树脂层的所需部分用冲模切割,形成开口部分,并附上树脂膜。此外,树脂膜可通过丝网印刷而构图成具有开口部分的形状。
接着,此树脂膜在130-200℃温度下进行热处理而固化,由此得到第一绝缘膜36a。
本实施例的一个特征在于,当形成半导体芯片以埋藏于绝缘膜内的状态安装的结构时,容易消除因半导体芯片厚度而产生的台阶。相应地,在本实施例中,在封装区域A中具有开口部分39的第一绝缘膜36a的厚度形成得与半导体芯片厚度相对应,并且半导体芯片安装在开口部分39中。因而,容易用第一绝缘膜36a消除因半导体芯片厚度而产生的台阶。
从而,根据各种半导体芯片的厚度来适当调节第一绝缘膜36a的厚度。在使用薄至厚度约为150μm或更小(优选30-70μm,包括凸起的高度)的半导体芯片的情况下,第一绝缘膜36a的厚度设定为等于此半导体芯片的厚度。而且,第一绝缘膜36a的开口部分39优选形成得围绕以后安装的半导体芯片。
接着,如图1C所示,在暴露于第一绝缘膜36a的开口部分39中的第二布线图案(Cu线)32a上,通过无电镀而有选择性地形成0.1-1μm厚的金(Au)膜37。此时,由于第一绝缘膜36a用固化树脂膜制成,因此,第一绝缘膜36a对无电镀所用镀覆化学物是有抗性的。应指出,可在第二布线图案(Cu线)32a上用无电镀形成镍(Ni)膜之后,形成Au膜37,其中,Ni膜作为阻挡膜。
如上所述,除了消除当半导体芯片以后述方式安装时因半导体芯片厚度而产生的台阶以外,第一绝缘膜36a还用作掩蔽层,用于在封装区域A中在第二布线图案(Cu线)32a的连接部分B上有选择性地形成Au膜37。
接着,制备如图1D所示的具有Au凸起21的半导体芯片20。按如下方式获得半导体芯片20:通过研磨半导体晶片(未示出)的背部而使半导体晶片变薄为厚约150μm(优选50μm或更小),其中,半导体晶片具有诸如晶体管的元件以及在元件形成表面上的连接垫;接着,切割半导体晶片,分成独立的片。在半导体晶片切割之前或之后在连接垫上形成半导体芯片20的Au凸起21。
尽管已用半导体芯片20作为电子部件的实例,但也可使用各种电子部件,包括电容器部件。应指出,半导体芯片20的连接垫和凸起21是连接端子的实例。
随后,用超声波工具拾起的半导体芯片20以半导体芯片20的Au凸起21朝下的状态放置在第二布线图案32a的连接部分B的Au膜37上,并且水平施加超声波振动,同时向下施加压力。因而,半导体芯片20的Au凸起21与第二布线图案32a的Au膜37接合在一起。以此方式,半导体芯片20通过超声波倒装接合而安装在第二布线图案32a上。
此时,第一绝缘膜36a的开口部分39的尺寸优选根据半导体芯片20的尺寸进行调节,使得在半导体芯片20的侧面和开口部分39的侧面之间留下0.5-2mm(优选约1mm)的间隙。
通过以上方式,半导体芯片20的背部和第一绝缘膜36a的上表面为几乎相同的高度,并且消除因半导体芯片20厚度而产生的台阶,因为如前所述,第一绝缘膜36a在除封装区域A之外的区域中形成为其厚度与半导体芯片20的厚度几乎相同。当然,应该指出,在后续步骤中不产生麻烦的程度上,半导体芯片20背部的高度和第一绝缘膜36a上表面的高度可互不相同。
另外,由于使用第一绝缘膜36a作为掩模,在第二布线图案32a的连接部分B上有选择性地形成Au膜37,因此,第二布线图案32a的连接部分B和半导体芯片20的Au凸起21可通过低成本的Au-Au接合而接合。
通常,在半导体芯片20的Au凸起21倒装安装在由Cu膜制成的第二布线图案32a上的情况下,由于Au-Cu接合可靠性低,容易发生接合故障。然而,在本实施例中通过采用Au-Au接合,可降低与接合有关的电阻,并且提高接合的可靠性。
如上所述,对于半导体芯片20的Au凸起21和第二布线图案32a通过Au-Au接合而接合的情形,通过形成在封装区域A中具有开口部分39的第一绝缘膜36a而消除因半导体芯片20的厚度而产生的台阶是非常方便的,因为在第二布线图案32a的连接部分B上有选择性地形成Au膜37。
顺便提一下,其表面未形成Au膜的Cu布线用作第二布线图案32a,并且,具有焊料凸起的半导体芯片20可倒装接合到第二布线图案32a的Cu布线上。可替换地,如前所述,具有焊料凸起的半导体芯片20可倒装接合到其表面上形成有Au膜37的第二布线图案32a。当然,可采用其它各种倒装安装。
对于前述在第一绝缘膜36a的开口部分39中安装半导体芯片20的结构,举一个获得此结构的方法的修改实例,其中,在半导体芯片20倒装安装到封装区域A中的第二布线图案32a上之后,附加树脂膜,此树脂膜在与封装区域A相应的区域中具有开口部分。在此情况下,树脂膜的开口部分事先用冲模切割而形成。
其次,如图1E所示,从半导体芯片20和第一绝缘膜36a的开口部分39之间的间隙注入树脂材料,由此用树脂材料填充半导体芯片20和布线基底2之间的间隙以及半导体芯片20和第一绝缘膜36a的开口部分39的侧面之间的间隙。然后,树脂材料通过热处理而固化,变为底层填充树脂36c(填充绝缘膜)。因而,半导体芯片20的背部、底层填充树脂36c的上表面和第一绝缘膜36a的上表面为几乎相同的高度,以平面化。
应指出,底层填充树脂36c按如下形成:在半导体芯片20倒装安装之前,在包括封装区域A的预定区域中预先涂敷绝缘树脂(NCF或NCP);以此树脂介于中间的状态执行倒装接合;接着,此树脂通过热处理而固化,变为底层填充树脂36c。
而且,底层填充树脂36c至少填充半导体芯片20下表面和布线基底2之间的间隙就足够。这是因为:即使在半导体芯片20的侧面和第一绝缘膜36a的开口部分39的侧面之间的间隙中保留凹入部分,这些凹入部分也被在下一步骤中形成的第二绝缘膜填充,以平面化。
接着,如图1F所示,形成5-20μm厚的第二绝缘膜36b,此膜覆盖半导体芯片20。对于第二绝缘膜36b,使用环氧类树脂、聚酰亚胺类树脂、聚苯醚类树脂、等等。而且,对于形成第二绝缘膜36b的方法,采用层压树脂膜的方法、或通过自旋涂敷或印刷形成树脂膜并接着在130-200℃温度下热处理而固化该树脂膜的方法。
此时,在消除因半导体芯片20厚度而产生的台阶的底层结构上形成第二绝缘膜36b。相应地,以其上表面平面化的状态形成第二绝缘膜36b,而不受半导体芯片20厚度的影响。
因而,获得处于平面化状态的第二层间绝缘膜36,此膜由第一绝缘膜36a、底层填充树脂36c和第二绝缘膜36b组成。以此方式,形成半导体芯片20以埋藏于第二层间绝缘膜36中的状态而倒装安装到第二布线图案32a上的结构。
接着,如图1G所示,用YAG或CO2激光或RIE蚀刻在第二布线图案32a上的第二层间绝缘膜36的预定部分,由此形成其深度直抵第二布线图案32a的第二通孔36x。
其次,如图1H所示,通过无电镀或溅射在第二通孔36x的内表面上和在第二层间绝缘膜36上形成籽晶Cu膜32x。然后,如图1I所示,用光刻方法在籽晶Cu膜32x上形成具有开口部分33a的抗蚀膜33,开口部分33a与后面形成的第三布线图案相对应。此时,由于第二层间绝缘膜36全部以平面化的状态形成,因此,在光刻方法中不会发生散焦。从而,抗蚀膜33的所需图案被高精度地稳定形成。
然后,如图1J所示,使用抗蚀膜33作为掩模,通过以籽晶Cu膜32x作为电镀电源层的电镀而在第二通孔36x和抗蚀膜33的开口部分33a中形成Cu膜图案32y。
接着,在除去抗蚀膜33之后,用Cu膜图案32y作为掩模而蚀刻籽晶Cu膜32x。
因而,如图1K所示,在第二层间绝缘膜36上形成包括籽晶Cu膜32x和Cu膜图案32y的第三布线图案32b(上布线图案)。这些第三布线图案32b通过第二通孔36x连接到第二布线图案32a。
第三布线图案32b在用高精度形成的抗蚀膜33的图案划分界线的条件下形成。从而,可稳定地获得所要求的第三布线图案32b。
除了上述半添加工艺之外,第二和第三布线图案32a和32b还可通过消去工艺或全添加工艺形成。
顺便提一下,通过将从步骤(图1B)到步骤(图1K)的工艺重复预定次数,可形成多个半导体芯片20以埋藏于各个层间绝缘膜内的状态进行多层叠加而相互连接的模式,其中,在步骤(图1B)中,形成在布线基底2的封装区域A中具有开口部分39的第一绝缘膜36a,而在步骤(图1K)中形成第三布线图案32b。在此情况下,每个层间绝缘膜同样以平面化状态形成。相应地,其中具有半导体芯片的层间绝缘膜和布线图案能以层叠方式形成,而不产生任何问题。
进一步地,也可采用以下模式:半导体芯片20相似地埋藏在多个层间绝缘膜之中的任意层间绝缘膜中。进而,还可采用以下模式:半导体芯片20也以相似地埋藏于层间绝缘膜中的状态而层叠在基底30的背部上。
在图1K中,绘出第三布线图案32b中的连接部分B的片段,在后面,上半导体芯片的凸起连接到这些片段。
其次,如图1L所示,形成具有开口部分38a的阻焊膜38,开口部分38a用于一次全部地暴露第三布线图案32b的连接部分B。换句话说,阻焊膜38形成得围绕一个封装区域,后面在此区域中安装上半导体芯片。
在本实施例中,作为第三布线图案32b的连接部分B,示出间距为约150μm(如,线路:100μm,间隔:50μm)或更小的细微部分。相应地,如果形成具有开口部分的连续阻焊膜,所述开口部分用于暴露第三布线图案32b的连接部分B的各个主要部分,就有以下情形:由于形成工艺中的偏移,阻焊膜的开口部分以从连接部分B的主要部分偏移的状态而形成。如果阻焊膜的开口部分以从连接部分B的主要部分偏移的状态设置,就减小了上半导体芯片的凸起与连接部分B之间的接合面积。从而,由于凸起接合强度的降低而容易发生接合故障等。
然而,在本实施例中,在放置第三布线图案32b的连接部分B的封装区域中,没有形成阻焊膜38的图案,而在封装区域中一次全部地设置开口部分38a。因而,在第三布线图案32b的连接部分B中,不会发生倒装接合的接合面积变小的问题。
其次,如图1M所示,使用阻焊膜38作为掩模,通过无电镀,在暴露于开口部分38a中的第三布线图案32b上有选择性地相继形成镍(Ni)膜40和Au膜42。应指出,在不需要阻挡膜的情况下可省略Ni膜40。
然后,如图1N所示,制备具有凸起21的上半导体芯片20x(上电子部件),并且,上半导体芯片20x的凸起21倒装接合到第三布线图案32b的连接部分B的Au膜42上。对于上半导体芯片20x的凸起21,使用Au凸起或焊料凸起。在使用Au凸起的情况下,用超声波执行Au-Au接合。同时,在使用焊料凸起的情况下,通过回流加热而执行接合。
此时,在放置第三布线图案32b的连接部分B的封装区域中,阻焊膜38不存在。相应地,上半导体芯片20x的凸起21以能获得必需接合面积的状态而高可靠性地接合到第三布线图案32b的连接部分B上。
另外,由于第二层间绝缘膜36全部以平面化的状态形成,因此,第三布线图案32b的各个连接部分B在几乎相同的高度放置。从而,防止在上半导体芯片20x和第三布线图案32b的连接部分B之间发生接合故障。
应指出,可采用以下方式:通过在第三布线图案32b的连接部分B上安装焊接球而在连接部分B上形成凸起,并且,上半导体芯片20x的连接端子接合到这些凸起上。
以此方式,即使第三布线图案32b的连接部分B具有约150μm或更小的细微间距,上半导体芯片20x的凸起21也能高可靠性地倒装接合到第三布线图案32b的连接部分B上。
此时,优选根据上半导体芯片20x的尺寸而适当调节阻焊膜38的开口部分38a的尺寸,从而,从上半导体芯片20x外围部分到阻焊膜38的开口部分38a的侧面的尺寸可为0.5-2mm(优选约1mm)。
随后,又如图1N所示,用底层填充树脂35填充上半导体芯片20x的元件形成表面(下表面)和第三布线图案32b之间的间隙以及上半导体芯片20x的元件形成表面和第二层间绝缘膜36之间的间隙。底层填充树脂35填充在上半导体芯片20x下表面之下的间隙中,并且在被阻焊膜38的开口部分38a的侧面阻挡的状态下形成。
顺便提一下,当倒装接合具有微小间距的凸起21的上半导体芯片20x时,在放置第三布线图案32b的各个连接部分B的封装区域中不形成阻焊膜38的上述模式是一个优选实例。从而,可采用以下模式:在封装区域中连续地形成具有开口部分的阻焊膜38,所述开口部分用于第三布线图案32b的各个连接部分B的主要部分。
以此方式,完成第一实施例的半导体器件1(电子部件封装构件)。
在本实施例的半导体器件1中,形成在布线基底2的封装区域A中具有开口部分39的第一绝缘膜36a。而且,在第一绝缘膜36a的开口部分39中,在第二布线图案32a的连接部分B上倒装安装半导体芯片20。进而,用底层填充树脂36c以整体化状态填充半导体芯片20下表面之下的间隙和与其侧面相邻的间隙。
因而,半导体芯片20的背部(上表面)、第一绝缘膜36a的上表面和底层填充树脂36c的上表面被调节为几乎相同的高度,并且通过消除因半导体芯片20厚度所产生的台阶而平面化。进一步地,在第二绝缘膜的上表面被平面化的状态下形成用于覆盖半导体芯片20的第二绝缘膜。
而且,半导体芯片20以埋藏于平面第二层间绝缘膜36内的状态倒装安装在第二布线图案32a的连接部分B上,其中,第二层间绝缘膜36由第一绝缘膜36a、第二绝缘膜36b和底层填充树脂36c组成。
进一步地,在第二布线图案32a上的第二层间绝缘膜36的预定部分中形成第二通孔36x,并且,在第二层间绝缘膜36上形成通过第二通孔36x连接到第二布线图案32a的第三布线图案32b。
在第二层间绝缘膜36上,形成具有开口部分38a的阻焊膜38,开口部分38a一次全部地敞开其中放置第三布线图案32b的连接部分B的封装区域。上半导体芯片20x的凸起21倒装接合到第三布线图案32b的连接部分B上。进而,用底层填充树脂35填充上半导体芯片20x下表面之下的间隙。
如上所述,在本实施例的半导体器件1中,半导体芯片20倒装安装在第一绝缘膜36a的开口部分39中,第一绝缘膜36a部分地构成第二层间绝缘膜。本实施例的半导体器件1具有用第一绝缘膜36a消除因半导体芯片20厚度而产生的台阶的结构。
因而,由于用于覆盖半导体芯片20的第二绝缘膜36b以第二绝缘膜36b上表面是平面的状态形成,因此,在第二绝缘膜36b上高精度地稳定形成第三布线图案32b。而且,由于第三布线图案32b的连接部分B设置为几乎相同的高度,因此,上半导体芯片20x的凸起21与第三布线图案32b的连接部分B之间的接合可靠性得以提高。
从而,容易制造多个半导体芯片20以埋藏于各个层间绝缘膜中的状态进行三维层叠而相互连接的封装构件,而不会产生任何问题。
(第二实施例)
图2A-2F为顺序示出本发明第二实施例的电子部件封装构件的制造方法的剖面图。第二实施例与第一实施例的不同之处在于:使用在其背部上设置保护膜的半导体芯片;以及,不形成用于覆盖半导体芯片的绝缘膜。在第二实施例中,与第一实施例相似的步骤不再详细描述。
在制造第二实施例的电子部件封装构件的方法中,如图2A所示,首先,制备与第一实施例的图1C中相似的布线基底2。随后,制备在元件形成表面上具有凸起21并在其背部设置有绝缘保护膜44的半导体芯片20a(电子部件)。与第一实施例相似,半导体芯片20a是薄至厚度为约150μm(优选大约50μm)或更小的芯片。
对于保护膜44的材料,使用环氧类树脂、聚酰亚胺类树脂、聚苯醚类树脂、丙烯酸类树脂、等等。而且,对于形成保护膜44的方法,采用层压树脂膜的方法、通过自旋涂敷形成树脂膜的方法、或浸涂方法等等。在提高半导体芯片20a和保护膜44之间粘性的情况下,保护膜44可在半导体芯片20a背部上涂敷硅烷接合剂之后形成。
随后,又如图2A所示,通过与第一实施例中相似的方法,半导体芯片20a的凸起21倒装接合到暴露于第一绝缘膜36a的开口部分39(封装区域A)中的第二布线图案32a的Au膜37上。
接着,如图2B所示,与第一实施例相似,用底层填充树脂36c(填充树脂膜)填充半导体芯片20a下表面之下的间隙和与其侧面相邻的间隙。因而,绝缘膜36a的上表面、半导体芯片20a的保护膜44的上表面和底层填充树脂36c的上表面为几乎相同的高度,以平面化。
在第二实施例中,由于使用在其背部上具有保护膜44的半导体芯片20a,因此,与第一实施例不同,不需在半导体芯片20a上形成第二绝缘膜。相应地,在本实施例中,其中埋藏半导体芯片20a的第二层间绝缘膜36由绝缘膜36a、保护膜44和底层填充树脂36c组成。
其次,如图2C所示,用激光或RIE蚀刻在第二布线图案32a上的第二层间绝缘膜36的预定部分,由此形成其深度直抵第二布线图案32a的第二通孔36x。
随后,如图2D所示,通过与第一实施例相似的方法,在第二层间绝缘膜36上形成通过第二通孔36x连接到第二布线图案32a的第三布线图案32b(上布线图案)。
接着,如图2E所示,与第一实施例相似,在图2D的结构上形成具有开口部分38a的阻焊膜38,开口部分38a用于一次全部地暴露第三布线图案32b的各个连接部分B。进而,通过无电镀,在第三布线图案32b的连接部分B上相继形成Ni膜40和Au膜42。
然后,如图2F所示,通过与第一实施例相似的方法,上半导体芯片20x(上电子部件)的凸起21倒装接合到第三布线图案32b的连接部分B的Au膜42上。随后,与第一实施例相似,用底层填充树脂35填充半导体芯片20x下面的间隙。
以此方式,获得第二实施例的半导体器件1a(电子部件封装构件)。
在第二实施例中,发挥与第一实施例中相似的效果。除此之外,由于使用使用在其背部上具有保护膜44的半导体芯片20a,因此,与在第一实施例中形成用于覆盖半导体芯片的第二绝缘膜的方法相比,本实施例的制造方法得到简化,并且制造成本下降。而且,通过使用在其背部上具有保护膜44的半导体芯片20a,半导体器件可制造得比第一实施例更薄。
(第三实施例)
图3A-3E为顺序示出本发明第三实施例的电子部件封装构件的制造方法的剖面图。第三实施例与第一和第二实施例的不同之处在于:在半导体芯片倒装安装之后,在其中形成贯穿半导体芯片的通孔,因而实现互连。在第三实施例中,与第一实施例相似的步骤不再详细描述。
在制造第三实施例的电子部件封装构件的方法中,如图3A所示,首先,制备与第一实施例的图1C中相似的布线基底2。随后,制备半导体芯片20b,半导体芯片20b在其元件形成表面上具有连接垫23和与其相连的凸起21,并且在其背部上具有与第二实施例中相似的保护膜44。尽管未清楚示出,但通过重新布设Cu线把电极垫(未示出)重新布置为区域阵列型布置而获得半导体芯片20b的连接垫23,在外围型布置中,电极垫布置在半导体芯片20b的外围部分上。
接着,通过与第一实施例中相似的方法,半导体芯片20b的凸起21倒装接合到第二布线图案32a的连接部分B的Au膜37上。相连接的连接垫23和凸起21是连接端子的实例。
随后,如图3B所示,通过与第一实施例中相似的方法,用底层填充树脂36c(填充绝缘膜)填充半导体芯片20b下表面之下的间隙和与其侧面相邻的间隙。因而,与第二实施例相似,获得平面化的第二层间绝缘膜36,此膜由绝缘膜36a、保护膜44和底层填充树脂36c组成。
接着,如图3C所示,在连接垫23的除接合凸起21之外的区域上,用激光或RIE在半导体芯片20b和保护膜44的预定部分中形成其深度直抵连接垫23的第二通孔19。
在连接垫23的除接合凸起21之外的区域上形成第二通孔19的理由是:如果在接合凸起21的区域之上形成第二通孔19,激光或RIE就会在连接垫23和凸起21之间的接合处造成损坏,降低接合可靠性。
其次,如图3D所示,通过已在第一实施例中描述的半添加工艺等,在保护膜44和绝缘膜36a上形成第三布线图案32b(上布线图案),第三布线图案32b通过在半导体芯片20b中形成的第二通孔19而连接到连接垫23。
随后,与第一实施例相似,形成具有开口部分38a的阻焊膜38,开口部分38a用于一次全部地暴露第三布线图案32b的连接部分B。
接着,如图3E所示,通过与第一实施例中相似的方法,在暴露于阻焊膜38的开口部分38a中的第三布线图案32b的各个连接部分B上相继形成Ni膜40和Au膜42。进而,在具有凸起21的上半导体芯片20x(上电子部件)的凸起21倒装接合到第三布线图案32b的连接部分B的Au膜42上之后,用底层填充树脂35填充半导体芯片20x下表面之下的间隙。
以此方式,完成第三实施例的半导体器件1b(电子部件封装构件)。
下面,描述第三实施例的修改例的电子部件封装构件。图4为示出根据本发明第三实施例的修改例的电子部件封装构件的截面图。
如图4所示,在第三实施例修改例的半导体器件1c中,使用在其背部上没有保护膜44的半导体芯片20b。而且,在半导体芯片20b倒装接合到第二布线图案32a并用底层填充树脂36c填充之后,与第一实施例相似地,在半导体芯片20b上形成第二绝缘膜36b。
进一步地,在本修改例中,在形成第二通孔19的步骤中,用激光或RIE蚀刻用于覆盖半导体芯片20b的第二绝缘膜36b以及半导体芯片20b。进而,在第二绝缘膜36b上形成第三布线图案32b。其它组件与图3E中的相同,因此不再进一步描述。
第三实施例具有与第一实施例相似的效果。除此之外,由于通过在半导体芯片20b中形成的第二通孔19实现互连,因此,可缩短连接长度。从而,它可适应高频应用的半导体器件中信号速度的提高。
(第四实施例)
图5A-5G为顺序示出本发明第四实施例的电子部件封装构件的制造方法的剖面图。第四实施例与第一至第三实施例的不同之处在于:半导体芯片面朝上地安装。在第四实施例中,与第一实施例中相似的步骤不再详细描述。
在制造第四实施例的电子部件封装构件的方法中,如图5A所示,首先,制备与第一实施例的图1C中相似的布线基底2。随后,通过与第一实施例中相似的方法,在布线基底2上形成在封装区域A中具有开口部分39的第一绝缘膜36a。
在本实施例中,半导体芯片面朝上地安装在封装区域A(开口部分39)中。从而,与第一至第三实施例不同,不必在封装区域A内的第二布线图案32a的部分中形成Au膜。除此之外,暴露于第一绝缘膜36a的开口部分39中的布线基底2的封装区域A可以是如图5A所示的第二布线图案32a一部分、第一层间绝缘膜34一部分、其中第二布线图案32a和第一层间绝缘膜34共存的一部分中的任意一个。
接着,制备如图5B所示的半导体芯片20c(电子部件)。在半导体芯片20c中,在其元件形成表面上设置连接垫23(连接端子),并且用钝化膜25覆盖该表面上的其它部分。随后,半导体芯片20c以其连接垫23朝上(面向上)的状态固定在暴露于第一绝缘膜36a的开口部分39中的第二布线图案32a上,并且在它们之间插入粘附层46。
此时,半导体芯片20c的元件形成表面和第一绝缘膜36a的上表面为几乎相同的高度,因而,消除因半导体芯片20c厚度而产生的台阶。
然后,如图5C所示,在半导体芯片20c和第一绝缘膜36a上形成第二绝缘膜36b。第二绝缘膜36b用与第一实施例相似的材料和方法形成。
第二绝缘膜36b以其上表面被平面化的状态而形成,它不受因半导体芯片20c厚度而产生的台阶的影响。此时,用第二绝缘膜36b填充半导体芯片20c的侧面和第一绝缘膜36a的开口部分39的侧面之间的间隙,以平面化。
因而,获得由第一和第二绝缘膜36a和36b组成的第二层间绝缘膜36,并且形成半导体芯片20c埋藏于平面第二层间绝缘膜36中并且面朝上安装的结构。
接着,如图5D所示,用激光或RIE蚀刻在半导体芯片20c的连接垫23上的第二层间绝缘膜36的预定部分,由此形成其深度直抵连接垫23的第二通孔36x。此时,同时蚀刻在第二布线图案32a上的第二层间绝缘膜36的预定部分,由此同时形成其深度直抵第二布线图案32a的第二通孔36x。
随后,如图5E所示,通过在第一实施例中描述的半添加工艺,在第二层间绝缘膜36上形成第三布线图案32b(上布线图案),第三布线图案32b通过第二通孔36x而分别连接到半导体芯片20c的连接垫23和第二布线图案32a。
顺便提一下,从步骤(图5B)到步骤(图5E)的工艺可重复预定次数,在步骤(图5B)中,在第一绝缘膜36a的开口部分39中面朝上地安装半导体芯片20c,在步骤(图5E)中形成第三布线图案32b。在此情况下,容易获得以下封装构件而不产生任何问题,在此封装构件中,多个半导体芯片20c面朝上地埋藏在各个层间绝缘膜中并通过通孔而互连。
接着,如图5F所示,与第一实施例相似,形成具有开口部分38a的阻焊膜38,开口部分38a用于一次全部地暴露第三布线图案32b的各个连接部分B。接着,在暴露于阻焊膜38的开口部分38a中的第三布线图案32b上相继形成Ni膜40和Au膜42。
随后,如图5G所示,制备具有凸起21的上半导体芯片20x(上电子部件),并且,上半导体芯片20x的凸起21倒装接合到第三布线图案32b的连接部分B的Au膜42上。随后,与第一实施例相似,用底层填充树脂35填充半导体芯片20x下表面之下的间隙。
以此方式,完成第四实施例的半导体器件1d(电子部件封装构件)。
在第四实施例的半导体器件1d中,在布线基底2上形成在封装区域A中具有开口部分39的第一绝缘膜36a。而且,半导体芯片20c以其连接垫23向上(面朝上)的状态安装在第一绝缘膜36a的开口部分39中。因而,用第一绝缘膜36a消除因半导体芯片20c厚度而产生的台阶。
进而,以第二绝缘膜36b的上表面被平面化的状态形成用于覆盖半导体芯片20c的第二绝缘膜36b,并且,第二层间绝缘膜36由第一和第二绝缘膜36a和36b组成。因而,半导体芯片20c以埋藏于平面第二层间绝缘膜36中的状态面朝上地安装。
另外,分别在半导体芯片20c的连接垫23和第二布线图案32a上的第二层间绝缘膜36中形成第二通孔36x。进一步地,在第二层间绝缘膜36上形成通过第二通孔36x连接到连接垫23和第二布线图案32a的第三布线图案32b。进而,上半导体芯片20x的凸起21倒装接合到第三布线图案32b的连接部分B上。
下面,描述第四实施例的修改例的电子部件封装构件。图6为示出根据本发明第四实施例的修改例的电子部件封装构件的截面图。如图6所示,在第四实施例的修改例的半导体器件1e中,在半导体芯片20c上未形成第二绝缘膜36b。在此模式的情况下,其绝缘电阻具有高可靠性并且在连接垫23上具有开口部分25a的一种绝缘膜用作半导体芯片20c的钝化膜25。
对于此钝化膜25,不特别限制它的材料和厚度。然而,例如,钝化膜25由厚约0.5μm的氮化硅膜和厚约3μm或更厚的聚酰亚胺树脂膜组成。进一步地,具有开口部分的树脂膜可附加到半导体芯片20c上而变为钝化膜25,所述开口部分用于暴露连接垫23。
随后,用底层填充树脂36c填充半导体芯片20c的侧面和第一绝缘膜36a的开口部分39的侧面之间的间隙,以完全实现平面化。接着,蚀刻第二布线图案32a上的第一绝缘膜36a,由此形成第二通孔36x。
然后,在第一绝缘膜36a和钝化膜25上形成第三布线图案32b,第三布线图案32b通过第二通孔36x连接到第二布线图案32a,并通过钝化膜25的开口部分25a连接到连接垫23。通过采用上述修改例,可省略用于覆盖半导体芯片20c的第二绝缘膜36b。其它组件与图5G中的相同,因此不再进一步描述。
在第四实施例中,半导体芯片20c面朝上地安装在第一绝缘膜36a的开口部分39中。相应地,与第一至第三实施例中半导体芯片面朝下地倒装安装的情况相似,容易用第一绝缘膜36a消除因半导体芯片20c厚度而产生的台阶。从而,第四实施例具有与第一实施例相似的效果。
Claims (22)
1.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,其有一个连接端子倒装安装到暴露于第一绝缘膜开口部分中的布线图案上;
用于覆盖电子部件的第二绝缘膜;
在布线图案上的第一和第二绝缘膜的预定部分中形成的通孔;以及
在第二绝缘膜上形成的上布线图案,上布线图案通过通孔连接到上述布线图案。
2.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,它在其元件形成表面上具有连接端子并在其背部上具有保护膜,电子部件的连接端子倒装安装到暴露于所述绝缘膜开口部分中的布线图案上;
在布线图案上的绝缘膜预定部分中形成的通孔;以及
在绝缘膜和保护膜上形成的上布线图案,上布线图案通过通孔连接到上述布线图案。
3.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,它在其元件形成表面上具有连接端子并在其背部上具有保护膜,所述电子部件的连接端子倒装安装到暴露于所述绝缘膜开口部分中的布线图案上;
贯穿所述连接端子上的电子部件和保护膜的预定部分的通孔;以及
在绝缘膜和保护膜上形成的上布线图案,上布线图案通过电子部件的通孔而连接到所述连接端子。
4.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,其有一个连接端子倒装安装到暴露于第一绝缘膜开口部分中的布线图案上;
用于覆盖电子部件的第二绝缘膜;
贯穿所述连接端子上的电子部件和第二绝缘膜的预定部分的通孔;以及
在第二绝缘膜上形成的上布线图案,上布线图案通过电子部件的通孔连接到所述连接端子。
5.如权利要求1-4中任一项所述的电子部件封装构件,其中,电子部件的连接端子由金制成,在绝缘膜的开口部分中的布线图案表面上形成金膜,并且,电子部件的连接端子通过金-金接合而倒装安装到布线图案上。
6.如权利要求1-4中任一项所述的电子部件封装构件,其中,电子部件倒装安装在绝缘膜开口部分中的结构包括这样的结构:在电子部件和布线基底之间的间隙以及电子部件和开口部分侧面之间的间隙中,至少在电子部件和布线基底之间的间隙中形成填充绝缘膜。
7.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,该部件以连接端子朝上的状态安装在第一绝缘膜的开口部分的封装区域中;
用于覆盖电子部件的第二绝缘膜;
分别在连接端子和布线图案上的绝缘膜预定部分中形成的通孔;以及
在第二绝缘膜上形成的上布线图案,上布线图案通过通孔而分别连接到所述连接端子和上述布线图案。
8.一种电子部件封装构件,包括:
具有布线图案的布线基底;
在布线基底上形成的绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
电子部件,该部件在其元件形成表面上具有连接端子和钝化膜,并以连接端子朝上的状态安装在绝缘膜的开口部分中的封装区域中,所述钝化膜具有用于暴露所述连接端子的开口部分;
在布线图案上的绝缘膜预定部分中形成的通孔;以及
在绝缘膜和钝化膜上形成的上布线图案,上布线图案通过通孔连接到布线图案,并通过开口部分连接到所述连接端子。
9.如权利要求1-4、7和8中任一项所述的电子部件封装构件,其中,电子部件的上表面和具有开口部分的绝缘膜的上表面被调节为处于几乎相同的高度。
10.如权利要求1-4、7和8中任一项所述的电子部件封装构件,进一步包括:具有倒装安装到上布线图案上的连接端子的上电子部件。
11.如权利要求10所述的电子部件封装构件,其中,在绝缘膜和上布线图案上形成具有开口部分的阻焊膜,所述开口部分一次全部地敞开安装上电子部件的封装区域,并且,在上电子部件下表面之下的间隙中形成填充绝缘膜。
12.如权利要求1-4、7和8中任一项所述的电子部件封装构件,其中,电子部件是厚度为约150μm或更小的半导体芯片,并且绝缘膜由树脂制成。
13.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件的连接端子倒装安装到暴露于第一绝缘膜开口部分中的布线图案上;
形成用于覆盖电子部件的第二绝缘膜;
在布线图案上的第一和第二绝缘膜的预定部分中形成其深度直抵布线图案的通孔;以及
在第二绝缘膜上形成上布线图案,上布线图案通过通孔连接到上述布线图案。
14.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件的连接端子倒装安装到暴露于绝缘膜开口部分中的布线图案上,电子部件在其元件形成表面上具有所述连接端子并在其背部上具有保护膜;
在布线图案上的绝缘膜预定部分中形成其深度直抵布线图案的通孔;以及
在绝缘膜和保护膜上形成上布线图案,上布线图案通过通孔连接到上述布线图案。
15.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件的连接端子倒装安装到暴露于绝缘膜开口部分中的布线图案上,电子部件在其元件形成表面上具有所述连接端子并在其背部上具有保护膜;
通过蚀刻所述连接端子上的电子部件和保护膜的预定部分而形成其深度直抵连接端子的通孔;以及
在绝缘膜和保护膜上形成上布线图案,上布线图案通过通孔而连接到所述连接端子。
16.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件的连接端子倒装安装到暴露于第一绝缘膜开口部分中的布线图案上;
形成用于覆盖电子部件的第二绝缘膜;
通过蚀刻所述连接端子上的电子部件和第二绝缘膜的预定部分而形成其深度直抵连接端子的通孔;以及
在第二绝缘膜上形成上布线图案,上布线图案通过通孔连接到所述连接端子。
17.如权利要求13-16中任一项所述的方法,其中,在形成具有开口部分的绝缘膜的步骤之后,并在倒装安装电子部件的步骤之前,进一步包括以下步骤:
使用绝缘膜作为掩模,通过无电镀在暴露于绝缘膜开口部分中的布线图案上有选择地形成金膜,
其中,在倒装安装电子部件的步骤中,由金制成的电子部件的连接端子倒装安装到布线图案的金膜上。
18.如权利要求13-16中任一项所述的方法,其中,倒装安装电子部件的步骤包括在电子部件和布线图案之间形成填充绝缘膜。
19.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成第一绝缘膜,第一绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件以其连接端子朝上的状态安装在布线基底上的第一绝缘膜的开口部分中;
形成用于覆盖电子部件的第二绝缘膜;
分别在连接端子和布线图案上的绝缘膜预定部分中形成通孔;以及
在第二绝缘膜上形成上布线图案,上布线图案通过所述通孔而分别连接到所述连接端子和上述布线图案。
20.一种制造电子部件封装构件的方法,包括以下步骤:
制备具有布线图案的布线基底;
在布线基底上形成绝缘膜,该绝缘膜在安装电子部件的封装区域中具有开口部分;
将电子部件以连接端子朝上的状态安装在布线基底上的绝缘膜开口部分中,电子部件在其元件形成表面上具有连接端子和钝化膜,钝化膜具有用于暴露所述连接端子的开口部分;
在布线图案上的绝缘膜预定部分中形成其深度直抵布线图案的通孔;以及
在绝缘膜和钝化膜上形成上布线图案,上布线图案通过通孔连接到布线图案,并通过开口部分连接到所述连接端子。
21.如权利要求13-16、19和20中任一项所述的方法,其中,电子部件的上表面和具有开口部分的绝缘膜的上表面设定为处于几乎相同的高度。
22.如权利要求13-16、19和20中任一项所述的方法,其中,电子部件是厚度为约150μm或更小的半导体芯片,并且绝缘膜是树脂膜。
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CN103379737A (zh) * | 2012-04-19 | 2013-10-30 | 佳能株式会社 | 印刷电路板 |
CN103379737B (zh) * | 2012-04-19 | 2016-03-02 | 佳能株式会社 | 印刷电路板 |
US9185804B2 (en) | 2012-04-19 | 2015-11-10 | Canon Kabushiki Kaisha | Printed circuit board |
CN104321866A (zh) * | 2012-09-14 | 2015-01-28 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN104321866B (zh) * | 2012-09-14 | 2018-03-02 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN105280577A (zh) * | 2014-05-28 | 2016-01-27 | 南茂科技股份有限公司 | 芯片封装结构以及芯片封装结构的制作方法 |
CN107154418A (zh) * | 2016-03-04 | 2017-09-12 | 株式会社日本显示器 | 显示装置 |
CN107154418B (zh) * | 2016-03-04 | 2020-10-27 | 株式会社日本显示器 | 显示装置 |
CN110545635A (zh) * | 2018-05-29 | 2019-12-06 | 鹏鼎控股(深圳)股份有限公司 | 多层电路板的制作方法 |
CN110545635B (zh) * | 2018-05-29 | 2021-09-14 | 鹏鼎控股(深圳)股份有限公司 | 多层电路板的制作方法 |
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JP2004247475A (ja) | 2004-09-02 |
US7057290B2 (en) | 2006-06-06 |
US7964950B2 (en) | 2011-06-21 |
KR20040073301A (ko) | 2004-08-19 |
TWI331389B (en) | 2010-10-01 |
US20090206471A1 (en) | 2009-08-20 |
JP4137659B2 (ja) | 2008-08-20 |
US20060145359A1 (en) | 2006-07-06 |
US7691673B2 (en) | 2010-04-06 |
US20070013048A1 (en) | 2007-01-18 |
TW200416997A (en) | 2004-09-01 |
EP1447850A2 (en) | 2004-08-18 |
US20040178510A1 (en) | 2004-09-16 |
EP1447850A3 (en) | 2010-07-21 |
US7545049B2 (en) | 2009-06-09 |
KR101041011B1 (ko) | 2011-06-16 |
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