JP4668782B2 - 実装基板の製造方法 - Google Patents
実装基板の製造方法 Download PDFInfo
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- JP4668782B2 JP4668782B2 JP2005363411A JP2005363411A JP4668782B2 JP 4668782 B2 JP4668782 B2 JP 4668782B2 JP 2005363411 A JP2005363411 A JP 2005363411A JP 2005363411 A JP2005363411 A JP 2005363411A JP 4668782 B2 JP4668782 B2 JP 4668782B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
102 ビアプラグ
103、104A 導電パターン
104 導電層
104A,104B 導電層
105 接続層
106,111 絶縁層
107A,112A ビアプラグ
107B,112B パターン配線
107,112,116 配線部
108 半導体チップ
109 接続部
110 アンダーフィル
113,115,117 ソルダーレジスト層
114 接続層
Claims (5)
- 半導体チップが実装された実装基板の製造方法であって、
絶縁材料よりなる支持基板を貫通する第1のビアプラグを形成し、前記支持基板の第1の面に、前記第1のビアプラグに接続される第1の導電パターンを形成し、前記支持基板の第2の面に、導電層を形成する工程と、
前記第1の導電パターン上に接続層を形成した後、前記支持基板の第1の面に、前記第1の導電パターンの側面及び前記接続層を覆うように絶縁層を形成し、前記絶縁層に、前記接続層に達するビアホールを形成し、前記導電層を給電層として、前記ビアホールに第2のビアプラグと、前記絶縁層上に前記第2のビアプラグに接続されるパターン配線と、を形成することで、電解メッキにより配線部を形成する配線部形成工程と、
前記導電層をパターニングすることで、前記第1のビアプラグと個別に接続される第2の導電パターンを形成するパターニング工程と、
前記第2の導電パターンと前記パターン配線との間の接続試験を行う試験工程と、
前記配線部に半導体チップを実装する実装工程と、
前記実装工程の後に、前記絶縁層の下面及び前記第1の導電パターンの下面を露出させるように前記支持基板を除去する除去工程と、を有することを特徴とする実装基板の製造方法。 - 前記支持基板の前記第1の面には、前記第1のビアプラグとともに電解メッキの給電経路となる第1の導電パターンが形成され、当該第1の導電パターンは前記除去工程の後、除去されることを特徴とする請求項1記載の実装基板の製造方法。
- 前記実装工程の後に、
前記支持基板の前記第2の面に、別の給電層を形成する給電層形成工程と、
前記別の給電層から給電することで、電解メッキにより、前記配線部上に上層配線部を形成する上層配線部形成工程と、をさらに有し、
当該上層配線部形成工程の後で前記除去工程が実施されることを特徴とする請求項1または2記載の実装基板の製造方法。 - 前記配線部は、前記第1の面に形成された第1の絶縁層に形成され、前記上層配線部は、当該第1の絶縁層上に形成された第2の絶縁層に形成されることを特徴とする請求項3記載の実装基板の製造方法。
- 前記除去工程では、前記支持基板を研磨により除去することを特徴とする請求項1乃至4のうち、いずれか1項記載の実装基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005363411A JP4668782B2 (ja) | 2005-12-16 | 2005-12-16 | 実装基板の製造方法 |
US11/610,244 US7410837B2 (en) | 2005-12-16 | 2006-12-13 | Method of manufacturing mounting substrate |
TW095147046A TW200730065A (en) | 2005-12-16 | 2006-12-15 | Method of manufacturing mounting substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005363411A JP4668782B2 (ja) | 2005-12-16 | 2005-12-16 | 実装基板の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007165776A JP2007165776A (ja) | 2007-06-28 |
JP2007165776A5 JP2007165776A5 (ja) | 2008-11-13 |
JP4668782B2 true JP4668782B2 (ja) | 2011-04-13 |
Family
ID=38174163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005363411A Active JP4668782B2 (ja) | 2005-12-16 | 2005-12-16 | 実装基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7410837B2 (ja) |
JP (1) | JP4668782B2 (ja) |
TW (1) | TW200730065A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201325338A (zh) * | 2011-12-14 | 2013-06-16 | Wistron Corp | 避免金手指結構沾錫之電路板 |
US8889484B2 (en) | 2012-10-02 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for a component package |
US9642261B2 (en) * | 2014-01-24 | 2017-05-02 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Composite electronic structure with partially exposed and protruding copper termination posts |
US9508703B2 (en) * | 2014-04-30 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked dies with wire bonds and method |
KR102192569B1 (ko) * | 2015-11-06 | 2020-12-17 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119131A (ja) * | 1999-10-20 | 2001-04-27 | Matsushita Electric Ind Co Ltd | 電子部品実装体とそれを用いた電子機器と電子部品実装体の製造方法 |
JP2002261440A (ja) * | 2001-03-01 | 2002-09-13 | Sony Chem Corp | フレキシブル配線基板の製造方法及びフレキシブル配線基板 |
JP2004047666A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板とその製造方法および樹脂封止型半導体装置の製造方法 |
JP2004247475A (ja) * | 2003-02-13 | 2004-09-02 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
JP2005101035A (ja) * | 2003-09-22 | 2005-04-14 | Toppan Printing Co Ltd | 多層フレキシブル配線基板の製造方法及び多層フレキシブル配線基板 |
JP2005315775A (ja) * | 2004-04-30 | 2005-11-10 | Fujitsu Autom Ltd | 片面移動式プローブを用いた4端子検査方法及び4端子検査用治具 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11112152A (ja) | 1997-10-03 | 1999-04-23 | Matsushita Electric Ind Co Ltd | フリップチップ実装の多層プリント基板 |
US7474538B2 (en) * | 2002-05-27 | 2009-01-06 | Nec Corporation | Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP4108643B2 (ja) * | 2004-05-12 | 2008-06-25 | 日本電気株式会社 | 配線基板及びそれを用いた半導体パッケージ |
-
2005
- 2005-12-16 JP JP2005363411A patent/JP4668782B2/ja active Active
-
2006
- 2006-12-13 US US11/610,244 patent/US7410837B2/en active Active
- 2006-12-15 TW TW095147046A patent/TW200730065A/zh unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119131A (ja) * | 1999-10-20 | 2001-04-27 | Matsushita Electric Ind Co Ltd | 電子部品実装体とそれを用いた電子機器と電子部品実装体の製造方法 |
JP2002261440A (ja) * | 2001-03-01 | 2002-09-13 | Sony Chem Corp | フレキシブル配線基板の製造方法及びフレキシブル配線基板 |
JP2004047666A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板とその製造方法および樹脂封止型半導体装置の製造方法 |
JP2004247475A (ja) * | 2003-02-13 | 2004-09-02 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
JP2005101035A (ja) * | 2003-09-22 | 2005-04-14 | Toppan Printing Co Ltd | 多層フレキシブル配線基板の製造方法及び多層フレキシブル配線基板 |
JP2005315775A (ja) * | 2004-04-30 | 2005-11-10 | Fujitsu Autom Ltd | 片面移動式プローブを用いた4端子検査方法及び4端子検査用治具 |
Also Published As
Publication number | Publication date |
---|---|
TW200730065A (en) | 2007-08-01 |
US7410837B2 (en) | 2008-08-12 |
US20070141758A1 (en) | 2007-06-21 |
JP2007165776A (ja) | 2007-06-28 |
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