CN1956183A - 电子部件内置式基板及其制造方法 - Google Patents

电子部件内置式基板及其制造方法 Download PDF

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Publication number
CN1956183A
CN1956183A CNA2006101501224A CN200610150122A CN1956183A CN 1956183 A CN1956183 A CN 1956183A CN A2006101501224 A CNA2006101501224 A CN A2006101501224A CN 200610150122 A CN200610150122 A CN 200610150122A CN 1956183 A CN1956183 A CN 1956183A
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China
Prior art keywords
substrate
electronic part
part built
semiconductor chip
hole plug
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CNA2006101501224A
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English (en)
Inventor
町田洋弘
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Publication of CN1956183A publication Critical patent/CN1956183A/zh
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本发明公开一种电子部件内置式基板，包括：无芯基板(11)，在其中配线图案(31)形成于层叠绝缘层(26)和(27)中；半导体芯片(14)，其与配线图案(31)电连接；树脂层(13)，其构造成覆盖无芯基板(11)的第一主面并且具有容纳半导体芯片(14)的容纳部分(57)；以及密封树脂(19)，其密封容纳于容纳部分(57)中的半导体芯片(14)。

Description

电子部件内置式基板及其制造方法
技术领域
本发明涉及一种电子部件内置式基板。具体地，本发明涉及这样一种电子部件内置式基板，其具有多层配线结构以及与设置在多层配线结构中的配线图案电连接的电子部件。
背景技术
近年来，在诸如半导体芯片等电子部件的高密度化方面已经取得显著进步，从而便于实现电子部件的小型化。伴随着该进步已经提出了电子部件内置于多层配线结构中的电子部件内置式基板，多层配线结构构造成在多个层叠(层压)的绝缘层中形成配线图案。
图34为现有技术的电子部件内置式基板的剖视图。
如图34所示，电子部件内置式基板200具有第一多层配线结构201、第二多层配线结构202、裸芯片203、散热板204、密封树脂205、通孔塞(through-via)208、209和210，以及散热端子211。
第一多层配线结构201具有层叠的树脂层213和设置于层叠树脂层213中的第一配线图案214。容纳部分216形成为容纳裸芯片203。
第二多层配线结构202设置于第一多层配线结构201上。第二多层配线结构202具有层叠的树脂层217和设置于层叠树脂层217中的第二配线图案218。第二配线图案218通过通孔塞208与第一配线图案214电连接。
裸芯片203布置在容纳部分216中，并由密封树脂205密封。裸芯片203具有与通孔塞209相连的电极(图中未示出)。该电极通过通孔塞209与第二配线图案218电连接。
这样，便可以通过在第一多层配线结构201中所形成的容纳部分216中设置裸芯片203来实现电子部件内置式基板200的小型化。
散热板204设置于裸芯片203的表面203B上，该表面与表面203A相反，而与通孔塞209相连的电极形成于表面203A上。散热板204与通孔塞210相连。散热端子211从密封树脂205中露出，并通过通孔塞210与散热板204热连接。
在电子部件内置式基板200与安装板诸如母板等(图中未示出)相连的状态中，散热端子211通过与设置于安装板上的散热部件诸如散热器等相连而散去裸芯片203中产生的热量(例如，参见专利文献1：日本未审定专利申请公开No.2004-79736)。
然而，在现有技术的电子部件内置式基板200中，在将裸芯片203容纳于第一多层配线结构201的容纳部分216中后，在第一多层配线结构201上形成第二多层配线结构202。因此，现有技术存在一个问题，即：甚至在将KGD(已知良品)的裸芯片203安装于第一多层配线结构201上时，如果第二配线图案218中发生故障(如短路)，现有技术的电子部件内置式基板200仍为有缺陷的产品，这降低了电子部件内置式基板200的产量。
此外，为了散去裸芯片203的热量，必须通过通孔塞210和散热端子211将设置于裸芯片203中的散热板204连接至散热部件诸如设置在安装板上的散热器等。因此，现有技术还存在另一个问题，即：不能充分散去裸芯片203产生的热量。
发明内容
本发明的实施例提供一种电子部件内置式基板，所述电子部件内置式基板能够提高其产量并有效散去内置电子部件所产生的热量。
根据本发明的一个或多个实施例的一个方面，提供了一种电子部件内置式基板，包括：多层配线结构，在其中配线图案形成于层叠绝缘层中；电子部件，其与所述配线图案电连接；树脂层，其覆盖所述多层配线结构的第一主面，并且具有容纳所述电子部件的容纳部分；以及密封树脂，其密封容纳于所述容纳部分中的所述电子部件。
根据本发明，可以在形成所述多层配线结构之后将所述电子部件与所述多层配线结构的配线图案电连接。因此，通过将所述电子部件安装于初步确定为合格产品的所述多层配线结构上，从而可以提高所述电子部件内置式基板的产量。
而且，从所述密封树脂中露出的散热元件可以设置于所述电子部件的一个表面上，该表面与电连接所述配线图案的表面相反。这样便可以采用比现有技术的基板更为简单的构造，以通过所述散热元件有效散去所述电子部件所产生的热量。
此外，根据本发明的电子部件内置式基板可以设置有与所述配线图案电连接并且穿透所述树脂层的通孔塞。这样，所述通孔塞适于用作外部连接端子。这样便可以将另一个基板或者半导体器件连接至所述通孔塞，从而可以提高封装密度。
在一些实施例中体现了下列优点中的一个或多个。例如，可以提高电子部件内置式基板的产量，并且有效散去内置电子部件所产生的热量。其他特征和优点则不限于这些具体实施例。
附图说明
图1是根据本发明实施例的电子部件内置式基板的剖视图。
图2是具有根据本发明所述实施例的电子部件内置式基板的电子装置的一个实例图。
图3是具有根据本发明所述实施例的电子部件内置式基板的电子装置的另一个实例图。
图4是制造根据本发明所述实施例的电子部件内置式基板的第一工序的视图。
图5是制造根据本发明所述实施例的电子部件内置式基板的第二工序的视图。
图6是制造根据本发明所述实施例的电子部件内置式基板的第三工序的视图。
图7是制造根据本发明所述实施例的电子部件内置式基板的第四工序的视图。
图8是制造根据本发明所述实施例的电子部件内置式基板的第五工序的视图。
图9是制造根据本发明所述实施例的电子部件内置式基板的第六工序的视图。
图10是制造根据本发明所述实施例的电子部件内置式基板的第七工序的视图。
图11是制造根据本发明所述实施例的电子部件内置式基板的第八工序的视图。
图12是制造根据本发明所述实施例的电子部件内置式基板的第九工序的视图。
图13是制造根据本发明所述实施例的电子部件内置式基板的第十工序的视图。
图14是制造根据本发明所述实施例的电子部件内置式基板的第十一工序的视图。
图15是制造根据本发明所述实施例的电子部件内置式基板的第十二工序的视图。
图16是制造根据本发明所述实施例的电子部件内置式基板的第十三工序的视图。
图17是制造根据本发明所述实施例的电子部件内置式基板的第十四工序的视图。
图18是制造根据本发明所述实施例的电子部件内置式基板的第十五工序的视图。
图19是制造根据本发明所述实施例的电子部件内置式基板的第十六工序的视图。
图20是制造根据本发明所述实施例的电子部件内置式基板的第十七工序的视图。
图21是制造根据本发明所述实施例的电子部件内置式基板的第十八工序的视图。
图22是制造根据本发明所述实施例的电子部件内置式基板的第十九工序的视图。
图23是制造根据本发明所述实施例的电子部件内置式基板的第二十工序的视图。
图24是制造根据本发明所述实施例的电子部件内置式基板的第二十一工序的视图。
图25是制造根据本发明所述实施例的电子部件内置式基板的第二十二工序的视图。
图26是制造根据本发明所述实施例的电子部件内置式基板的第二十三工序的视图。
图27是制造根据本发明所述实施例的电子部件内置式基板的第二十四工序的视图。
图28是制造根据本发明所述实施例的电子部件内置式基板的第二十五工序的视图。
图29是制造根据本发明所述实施例的电子部件内置式基板的第二十六工序的视图。
图30是制造根据本发明所述实施例的电子部件内置式基板的第二十七工序的视图。
图31是制造根据本发明所述实施例的电子部件内置式基板的第二十八工序的视图。
图32是制造根据本发明所述实施例的电子部件内置式基板的第二十九工序的视图。
图33是制造根据本发明所述实施例的电子部件内置式基板的第三十工序的视图。
图34为现有技术的电子部件内置式基板的剖视图。
优选实施例详述
以下将参考附图详细说明本发明的优选实施例。
图1是根据本发明实施例的电子部件内置式基板的剖视图。在图1中，参考标号A表示无芯基板(coreless substrate)11表面上的一个区域，该区域内连接有半导体芯片14(下文称之为“半导体芯片连接区A”)。参考标号B表示形成有通孔塞21的位置(下文称之为“通孔塞形成位置B”)。参考标号M1表示树脂层13自预浸渍树脂层28的顶面28A处起的厚度(下文称之为“厚度M1”)。顺便提到，可将半导体芯片14作为电子部件内置于电子部件内置式基板中，在下文中将该情况作为本发明所述实施例的一个实例进行说明。
以下参考图1说明根据本发明所述实施例的电子部件内置式基板10。电子部件内置式基板10包括用作多层配线结构的无芯基板11、树脂层13、半导体芯片14(为一电子部件)、散热元件16、金凸点17、密封树脂19、通孔塞21、阻焊层22和防扩散膜23。
无芯基板11包括层叠的绝缘层26与27、预浸渍树脂层28、配线图案31、防扩散膜32与33、阻焊层34和外部连接端子35。
绝缘层27设置于绝缘层26上。例如，环氧树脂可以用作绝缘层26和27的材料。预浸渍树脂层28设置于树脂层13与绝缘层27之间，并与树脂层13和绝缘层27相接触。预浸渍树脂层28是通过将树脂注入碳纤维织物或玻璃纤维织物，或者注入方向平行的碳纤维或玻璃纤维中而获得的。预浸渍树脂层28为用作支承板的轻质、高硬度和高强度的树脂层。
这样，预浸渍树脂层28设置于树脂层13与绝缘层27之间。因此，电子部件内置式基板10的强度和硬度便可得到充分保证，从而防止电子部件内置式基板10发生诸如翘曲等变形。
配线图案31设置于层叠绝缘层26和27以及预浸渍树脂层28中。配线图案31包括通孔塞36、38、43和44，配线37和41，第一连接片46以及第二连接片48。
通孔塞36设置为穿透绝缘层26。通孔塞36的顶部(位于无芯基板11的第一主面侧的端部)与配线37相连。防扩散膜33设置于通孔塞36的底部(位于无芯基板11的第二主面侧的端部)。配线37设置在绝缘层26的顶面26A上，而且被绝缘层27覆盖。配线37与其底面上的通孔塞36电连接。
通孔塞38设置在位于配线37上的绝缘层27中。通孔塞38与配线37和41电连接。配线41设置在绝缘层27的顶面27A上，并且被预浸渍树脂层28覆盖。配线41与其底面上的通孔塞38电连接。
通孔塞43设置在位于配线41上的预浸渍树脂层28中。通孔塞43将配线41与第一连接片46电连接。通孔塞44设置在位于配线41上的预浸渍树脂层28中。通孔塞44将配线41与第二连接片48电连接。
第一连接片46设置在预浸渍树脂层28的顶面28A上，并且被密封树脂19覆盖。第一连接片46与其底面上的通孔塞43电连接。第一连接片46通过防扩散膜32和金凸点17与半导体芯片14电连接。
第二连接片48设置在预浸渍树脂层28的顶面28A上，并且被树脂层13覆盖。第二连接片48设置在第一连接片46所处位置之外。第二连接片48与通孔塞44和通孔塞21电连接。
顺便提到，导电金属可以用作配线图案31的材料。例如，在该实例中铜可以用作导电金属。
防扩散膜32设置于第一连接片46上，与设置金凸点17的位置相对应。防扩散膜32为第一连接片46上的多层膜，其中依次层叠镍层51和金层52。此外，金层52与金凸点17相连。
防扩散膜33设置于通孔塞36的底部。防扩散膜33为通孔塞36底部处的多层膜，其中依次层叠镍层54和金层55。金层55与外部连接端子35相连。阻焊层34设置为覆盖绝缘层26的底面26B，防扩散膜33从阻焊层34中露出。
外部连接端子35设置在位于无芯基板11第二主面侧的防扩散膜33的金层55中。外部连接端子35用于将电子部件内置式基板10连接至安装板诸如母板等。例如，焊球可以用作外部连接端子35。
树脂层13设置为覆盖预浸渍树脂层28的顶面28A，预浸渍树脂层28设置于无芯基板11的第一主面侧。在树脂层13中形成适于容纳半导体芯片14的容纳部分57和内有通孔塞21的通孔59。容纳部分57形成为穿透树脂层13，与半导体芯片连接区A相对应。而且，容纳部分57构造成其尺寸大于半导体芯片14的外形尺寸，从而在容纳部分57的侧壁和半导体芯片14之间形成间隙，该间隙中填充有密封树脂19。
通孔59形成为穿透树脂层13并且露出第二连接片48的顶面，与通孔塞形成位置B相对应。
半导体芯片14具有电极片61，并且在容纳入容纳部分57中时由密封树脂19密封。电极片61通过金凸点17和防扩散膜32与第一连接片46电连接。因此，半导体芯片14与设置于无芯基板11中的配线图案31电连接。例如，存储半导体芯片和逻辑半导体芯片(比存储半导体芯片更易产生热量)可以用作半导体芯片14。
这样，具有容纳部分57的树脂层13设置于无芯基板11上。半导体芯片14容纳于容纳部分57中，以便与配线图案31电连接。这使得能够将半导体芯片14安装于初步确定为合格产品的无芯基板11上。因此，可以提高电子部件内置式基板10的产量。
散热元件16设置于半导体芯片14的表面14B上，该表面14B与电连接配线图案31的表面14A相反。此外，散热元件16的顶面16A从密封树脂19中露出。散热元件16用于将半导体芯片14所产生的热量散出至电子部件内置式基板10的外部。例如，主要成份为硅胶的散热片可以用作散热元件16。
这样，散热元件16设置于半导体芯片14的表面14B上，该表面14B与电连接配线图案31的表面14A相反。而且，散热元件16从密封树脂19中露出。因此，与现有技术的电子部件内置式基板200相比，散热路径得以缩短。因此，可以有效散去半导体芯片14所产生的热量。顺便提到，调整散热元件16使得至少散热元件16的顶面16A从密封树脂19中露出就足够了。或者，可以使散热元件16的顶面16A和侧面的一部分从密封树脂19中露出。与仅仅使散热元件16的顶面16A从密封树脂19中露出相比，在这种情况下可以增强散热元件16的散热效率。
金凸点17用于通过芯片倒装技术将半导体芯片14连接至其上设置有防扩散膜32的第一连接片46。金凸点17将电极片61与第一连接片46电连接。
密封树脂19填充容纳部分57，从而密封半导体芯片14。密封树脂19设置为至少露出散热元件16的顶面16A。例如，底部填充树脂可以用作密封树脂19。例如，含有分散玻璃填料的环氧基树脂可以用作底部填充树脂。
这样，采用密封树脂19密封容纳于树脂层13的容纳部分57中的半导体芯片14。因此，可以调整无芯基板11上方的半导体芯片14的位置。而且，还可以减小无芯基板11和半导体芯片14之间的热膨胀系数之差。
通孔塞21设置于树脂层13中所形成的通孔59中。通孔塞21的一个端部(底部)与第二连接片48电连接。通孔塞21的另一端部(顶部)与树脂层13的顶面13A大致齐平。例如，导电金属可以用作通孔塞21的材料。例如，在该实例中铜可以用作导电金属。
这样，与第二连接片48电连接的通孔塞21设置于通孔59中。因此，另一基板(例如，安装板)和半导体器件等可以与通孔塞21的顶部相连，该顶部与树脂层13的顶面13A大致齐平。从而可以提高电子部件内置式基板10的封装密度。
阻焊层22设置为覆盖树脂层13的顶面13A，并露出通孔塞21的顶部。
防扩散膜23设置于通孔塞32从阻焊层22中露出的顶部。防扩散膜23为通孔塞21顶部上的多层膜，其中依次层叠镍层63和金层64。
根据本实施例的电子部件内置式基板，树脂层13设置在具有多层配线结构的无芯基板11上，树脂层13具有适于容纳半导体芯片14的容纳部分57。这样，在无芯基板11形成后，半导体芯片14可以与无芯基板11中的配线图案31电连接。因此，通过将半导体芯片14连接至初步确定为合格产品的无芯基板11，可以提高电子部件内置式基板10的产量。
此外，散热元件16设置于半导体芯片14的表面14B之上。而且，散热元件16从密封树脂19中露出。因此，与现有技术的电子部件内置式基板200相比，散热路径得以缩短。从而可以有效散去半导体芯片14所产生的热量。
而且，与第二连接片48电连接的通孔塞21设置于树脂层13中所形成的通孔59中。于是，另一基板和半导体器件等可以与通孔塞21的顶部相连，该顶部与树脂层13的顶面13A大致齐平。从而可以提高电子部件内置式基板10的封装密度。
顺便提到，在本实施例的前述说明中是将半导体芯片14作为电子部件的一个实例进行描述。然而，也可以使用焊接部件诸如电容器等代替半导体芯片14。
图2为电子装置的一个实例图，其具有根据本实施例的电子部件内置式基板。在图2中，相同的参考标号表示与根据本实施例的电子部件内置式基板10相同的部件。
参照图2，电子装置70构造成包括电子部件内置式基板10和半导体器件71。半导体器件71包括基板72、通孔塞73、连接片74、第一半导体芯片76、第二半导体芯片77、密封树脂79、阻焊层81、防扩散膜82和外部连接端子84。
通孔塞73设置为穿透基板72。通孔塞73的一个端部(位于基板72的顶面72A侧)与连接片74电连接。而且，防扩散膜82设置于通孔塞73的另一端部(位于基板72的底面72B侧)。通孔塞73将连接片74与防扩散膜82电连接。
连接片74设置于基板72的顶面72A上，与通孔塞73所形成的位置相对应。连接片74通过导线89和91与第一半导体芯片76和第二半导体芯片77电连接。例如，导电金属可以用作通孔塞73和连接片74的材料。例如，在该实例中铜可以用作导电金属。
第一半导体芯片76具有电极片86。第一半导体芯片76的表面(位于未形成电极片86的一侧)与基板72的顶面72A接合。第一半导体芯片76的电极片86通过导线89(采用引线接合法)与连接片74电连接。
第二半导体芯片77在外形尺寸方面小于第一半导体芯片76，并且具有电极片87。第二半导体芯片77的表面(位于未形成电极片87的一侧)与第一半导体芯片76接合。第二半导体芯片77的电极片87通过导线91(采用引线接合法)与连接片74电连接。
密封树脂79设置于基板72的顶面72A上，密封彼此引线接合的第一半导体芯片76和第二半导体芯片77以及导线89和91。
阻焊层81设置为覆盖基板72的底面72B，同时露出通孔塞73的底部。
防扩散膜82设置于通孔塞73从阻焊层81中露出的底部。防扩散膜82为通孔塞73底部上的多层膜，其中依次层叠镍层93和金层94。
外部连接端子84设置于防扩散膜82的金层94上。外部连接端子84通过防扩散膜82、通孔塞73、连接片74以及导线89和91与第一半导体芯片76和第二半导体芯片77电连接。外部连接端子84与设置于电子部件内置式基板10上的防扩散膜23相连。因此，半导体器件71与电子部件内置式基板10电连接。
例如，如果存储半导体芯片和逻辑半导体芯片(比存储半导体芯片更易产生热量)与具有上述构造的电子装置70中的无芯基板11的配线图案31电连接，则将逻辑半导体芯片置于半导体芯片14所处的位置。而将存储半导体芯片置于第一半导体芯片76和第二半导体芯片77各自所处的位置。这样，存储半导体芯片和各逻辑半导体芯片相互隔开。因此，可以防止逻辑半导体芯片所产生的热量对存储半导体芯片造成不良影响。而且，逻辑半导体芯片位于半导体芯片14所处的位置。这样便可以通过散热元件16有效散去逻辑半导体芯片产生的热量。
图3是具有根据本实施例的电子部件内置式基板的电子装置的另一个实例图。在图3中，相同的参考标号表示与图2中所示电子部件内置式基板70相同的部件。
参照图3，电子装置100构造成包括电子部件内置式基板101和半导体器件105。除了将外部连接端子102设置于电子部件内置式基板101的防扩散膜23上以外，电子部件内置式基板101的构造与电子部件内置式基板10相似。外部连接端子102用于将电子部件内置式基板101连接至安装板诸如母板等。例如，焊球可以用作外部连接端子102。
除了将配线106设置于基板72的底面72B上并且将防扩散膜82设置于配线106上之外，半导体器件105的构造与半导体器件71(参见图2)相似。防扩散膜82与设置在电子部件内置式基板101中的外部连接端子35相连。因此，半导体器件105与电子部件内置式基板101电连接。
即便是采用这种构造的电子装置100也能够获得与电子装置70相似的优点。
图4至图33是说明制造根据本实施例的电子部件内置式基板的方法的视图。在图4至图33中，相同的参考标号表示与根据本实施例的电子部件内置式基板10相同的部件。
首先，如图4所示，制备一个由导电金属制成的支承板111。此后，在支承板111上形成绝缘层26。例如，可用厚度为400μm或以上的铜板作为支承板111。此外，在支承板111上形成绝缘层26之前，对支承板111进行表面清洗。绝缘层26通过将例如片状环氧基树脂层(厚度范围为30μm至40μm)附着在支承板111上而形成。
随后，如图5所示，与通孔塞36所形成的位置相对应，在绝缘层26中形成各通孔112，支承板111从各通孔中露出。通孔112通过例如激光束加工的方法形成。
此后，如图6所示，将金属层113形成为覆盖绝缘层26的顶面26A和通孔112。在绝缘层26上进行去除污处理后，通过进行电解电镀形成金属层113。可以将导电金属用作金属层113的材料。例如，在该实例中可以采用铜层(厚度为1μm)作为导电金属。
此后，如图7所示，将具有开口部分115A的干膜抗蚀剂115形成于图6中所示的结构上。开口部分115A与配线37的形状和形成位置相对应。例如，可以采用PFR-800AUS410(由Taiyo Ink MFG.CO.，LTD.制造)作为干膜抗蚀剂115。
此后，如图8所示，通过将金属层113作为供电层进行电解电镀，进行导电金属116的沉淀和生长，从而填充通孔112和开口部分115A。这样，分别在通孔112中形成通孔塞36(每一通孔塞均包括金属层113和导电金属116)。例如，可以采用铜作为导电金属116。
此后，如图9所示，去除干膜抗蚀剂115。此后，如图10所示，去除未被导电金属116覆盖的多余金属层113。随后，在绝缘层26的顶面26A上形成配线37(每一配线均包括金属层113和导电金属116)。
此后，如图11所示，通过与图4至图10中所示相似的技术，将绝缘层27、通孔塞38(每一通孔塞均包括金属层118和导电金属119)和配线41(每一配线均包括金属层118和导电金属119)形成于图10所示的结构上。例如，可以采用片状环氧基树脂层(厚度范围为30μm至40μm)作为绝缘层27。可以采用导电金属作为金属层118的材料。例如，在实际应用中，可以采用铜层(厚度为1μm)作为金属层118。而且，例如，可以采用铜层作为导电金属119。
此后，如图12所示，将预浸渍树脂层28形成为覆盖绝缘层27的顶面27A和配线41。例如，在实际应用中，将片状预浸渍树脂层28附着在图11所示的结构上。例如，预浸渍树脂层28的厚度可以为100μm。
此后，如图13所示，将通孔塞43和44(都包括金属层121和导电金属122)形成于位于配线41上的预浸渍树脂层28中。而且，将第一连接片46和第二连接片48(都包括金属层121和导电金属122)形成于预浸渍树脂层28的顶面28A上。这样便形成配线图案31；该配线图案包括通孔塞36、38、43和44，配线37和41，第一连接片46以及第二连接片48。
此后，如图14所示，将具有开口部分123A的干膜抗蚀剂123形成于图13所示的结构上。采用能够耐电镀液(更具体地，形成镍层51和金层52时所用的电镀液)的干膜抗蚀剂(电镀液无法浸入的干膜抗蚀剂)作为干膜抗蚀剂123。例如，可以采用411Y50(由Nichigo-MortonCo.，Ltd.制造)作为干膜抗蚀剂123。与防扩散膜32的形状和形成位置相对应，开口部分123A形成为露出第一连接片46的顶面。
随后，如图15所示，通过将金属层113作为供电层进行电解电镀，将镍层51和金层52依次层叠在从开口部分123A中露出的第一连接片46上而形成防扩散膜32。
此后，如图16所示，去除干膜抗蚀剂123。此后，如图17所示，在图16所示的结构上将干膜抗蚀剂125形成于与半导体芯片连接区A和通孔塞形成位置B相对应的区域上。采用能够耐电镀液(更具体地，形成镍层51和金层52时所用的电镀液)的干膜抗蚀剂(电镀液无法浸入的干膜抗蚀剂)作为干膜抗蚀剂125。例如，可以采用411Y50(由Nichigo-Morton Co.，Ltd.制造)作为干膜抗蚀剂125。干膜抗蚀剂125的厚度M2(自预浸渍树脂层28的顶面28A起)可设定为例如100μm。
此后，如图18所示，在图17所示的结构上将树脂层13形成于未被干膜抗蚀剂125覆盖的区域上。然后进行短时烘焙，以便使树脂层13硬化。树脂层13形成为使树脂层13的顶面13A与干膜抗蚀剂125的顶面125A大致齐平。例如，可以采用环氧基树脂作为树脂层13的材料。例如，可以通过旋涂法形成树脂层13。可以在预定处理条件下进行短时硬化，例如在100℃的温度硬化30分钟。
此后，如图19所示，抗蚀膜127形成为覆盖设置于半导体芯片连接区A上的干膜抗蚀剂125的顶面125A。抗蚀膜127是采用液态抗蚀剂而形成。例如，可以采用PSR-4000 AUS703(由Taiyo Ink MFG.CO.，LTD.制造)作为液态抗蚀剂。
此后，如图20所示，去除形成于第二连接片48上的干膜抗蚀剂125，从而形成露出第二连接片48的通孔59。例如，采用氢氧化钠通过湿蚀刻法去除干膜抗蚀剂125。
此后，如图21所示，通过将第二连接片48作为供电层进行电解电镀，在通孔59中进行导电金属的沉积和生长。这样，形成通孔塞21。例如，在该实例中可以将铜作为导电金属。
此后，如图22所示，去除抗蚀膜127。去除抗蚀膜127可以采用例如灰化的方法。然后，如图23所示，将保护片129附着在图22所示的结构上，以便覆盖该结构的顶面。当采用湿蚀刻法去除支承板111时，保护片129用于防止通孔塞21被蚀刻。
此后，如图24所示，采用湿蚀刻法去除支承板111。然后，去除保护片129，这如图25所示。
此后，如图26所示，形成阻焊层22和阻焊层34。阻焊层22适于覆盖图25所示结构的顶面，阻焊层34适于覆盖图25所示结构的底面。可以采用膜状阻焊层作为阻焊层22和34。例如，可以采用PFR-800AUS 410(由Taiyo Ink MFG.CO.，LTD.制造)作为膜状阻焊层。
此后，如图27所示，进行阻焊层22和34的暴露和生长，从而形成穿透阻焊层22的开口部分22A和22B以及穿透阻焊层34的开口部分34A。开口部分22A露出形成于半导体芯片连接区A上的干膜抗蚀剂125的顶面125A。开口部分22B露出通孔塞21的顶面。此外，开口部分34A露出通孔塞36的底面。
此后，如图28所示，通过将通孔塞21和通孔塞36作为供电层进行电解电镀，形成防扩散膜23和防扩散膜33。通过将镍层63和金层64依次层叠在通孔塞21(在开口部分22B中露出)的顶面上，从而获得防扩散膜23；通过将镍层54和金层55依次层叠在通孔塞36(从开口部分34A中露出)的底面上，从而获得防扩散膜33。
这样便制造出具有多层配线结构的无芯基板11。随后对无芯基板11进行电气检查以确定合格产品。确定为合格产品的无芯基板11用于图29至33所示的下列步骤。
此后，如图29所示，去除设置于半导体芯片连接区A上的干膜抗蚀剂125，从而在半导体芯片连接区A上形成容纳半导体芯片14的容纳部分57。与半导体芯片连接区A相对应，容纳部分57穿透树脂层13并露出预浸渍树脂层28、第一连接片46和防扩散膜32。
此后，如图30所示，将散热元件16设置为覆盖半导体芯片14的表面14B，该表面与连接第一连接片46的表面14A相反。然后，将金凸点132形成于半导体芯片14的电极片61的底面上。随后，将金凸点133形成于防扩散膜32上。稍后，熔融金凸点132和133，使二者相互连接，从而形成电连接半导体芯片14与防扩散膜32的金凸点17(参见图31)。
此后，如图31所示，熔融金凸点132和133，使二者相互连接。通过将熔融的金凸点132和133相结合，获得作为一体的图31所示的金凸点17。这样，通过金凸点17将半导体芯片14电连接至设置于无芯基板11中的配线图案31。
这样便将半导体芯片14连接至确定为合格产品的无芯基板11，从而提高电子部件内置式基板10的产量。
此后，如图32所示，采用密封树脂19将容纳于容纳部分57中的半导体芯片14密封。密封树脂19形成为至少露出散热元件16的顶面16A。例如，可以采用底部填充树脂作为密封树脂19。例如，可以采用含有分散玻璃填料的环氧基树脂作为底部填充树脂。
这样，密封树脂19形成为至少露出设置于半导体芯片14表面14B上的散热元件16的顶面16A。这样便可以采用比现有技术的基板更为简单的构造有效散去电子部件产生的热量。
此后，如图33所示，将外部连接端子35成形于位于无芯基板11的第二主面侧的防扩散膜33的金层55上。这样便可制成电子部件内置式基板10。例如，可以采用焊球作为外部连接端子35。
按照制造根据本实施例的电子部件内置式基板的方法，树脂层13设置于确定为合格产品的无芯基板11上，树脂层13具有适于容纳半导体芯片14的容纳部分57。设置于无芯基板11中的配线图案31与半导体芯片14电连接，从而可以提高电子部件内置式基板10的产量。
尽管已经详细说明了本发明的优选实施例，但是本发明不限于这些具体实施例。在不违背本发明实质和范围的条件下，可以进行各种修改或变化。
顺便提到，虽然是将半导体芯片14作为电子部件的一个实例来详细描述本实施例，但是可以将半导体芯片14以外的电子部件例如焊接部件诸如电容器等(在该情况下，其通过焊接与配线图案31电连接)容纳于容纳部分57中。
而且，虽然是将无芯基板11(因其没有有芯部件(core member)，因而能够比芯基板更薄)作为多层配线结构的一个实例详细描述本实施例，但是也可采用具有有芯部件诸如金属板等的有芯基板代替无芯基板11。
本发明可以应用于这样的电子部件内置式基板：其能够提高自身产量并且有效散去内置电子部件所产生的热量。
本申请以2005年10月27日提交的日本专利申请No.2005-313243为基础并要求该申请的外国优先权，其全部内容以引用的方式并入本文。

Claims (7)

1.一种电子部件内置式基板，包括：
多层配线结构，在其中配线图案形成于层叠绝缘层中；
电子部件，其与所述配线图案电连接；
树脂层，其覆盖所述多层配线结构的第一主面并且具有容纳所述电子部件的容纳部分；以及
密封树脂，其密封容纳于所述容纳部分中的所述电子部件。
2.根据权利要求1所述的电子部件内置式基板，其中，
所述层叠绝缘层中与所述树脂层相接触的层为预浸渍树脂层。
3.根据权利要求1或2所述的电子部件内置式基板，还包括：
散热元件，其设置于所述电子部件的一个表面上并且从所述密封树脂中露出，所述表面与电连接所述配线图案的表面相反。
4.根据权利要求1或2所述的电子部件内置式基板，还包括：
通孔塞，其与所述配线图案电连接并且穿透所述树脂层。
5.根据权利要求1或2所述的电子部件内置式基板，还包括：
外部连接端子，其设置于与所述多层配线结构的第一主面相反的第二主面上，并且与所述配线图案电连接。
6.一种制造电子部件内置式基板的方法，包括以下步骤：
形成多层配线结构，在所述多层配线结构中配线图案形成于层叠绝缘层中；
形成树脂层，所述树脂层覆盖所述多层配线结构的第一表面并且具有容纳部分；
在所述树脂层的容纳部分中设置电子部件，并将所述电子部件电连接至所述配线图案；以及
形成密封树脂，所述密封树脂密封容纳于所述容纳部分中的所述电子部件。
7.根据权利要求6所述的制造电子部件内置式基板的方法，还包括以下步骤：
形成通孔塞，所述通孔塞穿透所述树脂层并且与所述配线图案电连接。
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