CN1723556A - 可叠置的半导体器件及其制造方法 - Google Patents
可叠置的半导体器件及其制造方法 Download PDFInfo
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- CN1723556A CN1723556A CNA2004800017045A CN200480001704A CN1723556A CN 1723556 A CN1723556 A CN 1723556A CN A2004800017045 A CNA2004800017045 A CN A2004800017045A CN 200480001704 A CN200480001704 A CN 200480001704A CN 1723556 A CN1723556 A CN 1723556A
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- dielectric film
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
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- H—ELECTRICITY
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
Claims (83)
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JP2003158489 | 2003-06-03 | ||
JP158489/2003 | 2003-06-03 |
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CN1723556A true CN1723556A (zh) | 2006-01-18 |
CN100468719C CN100468719C (zh) | 2009-03-11 |
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CNB2004800017045A Expired - Fee Related CN100468719C (zh) | 2003-06-03 | 2004-05-31 | 可叠置的半导体器件及其制造方法 |
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US (2) | US7709942B2 (zh) |
EP (1) | EP1636842B1 (zh) |
KR (1) | KR100778597B1 (zh) |
CN (1) | CN100468719C (zh) |
HK (1) | HK1086386A1 (zh) |
TW (1) | TWI247373B (zh) |
WO (1) | WO2004109771A2 (zh) |
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US7489032B2 (en) | 2003-12-25 | 2009-02-10 | Casio Computer Co., Ltd. | Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same |
JP3945483B2 (ja) * | 2004-01-27 | 2007-07-18 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP3925809B2 (ja) * | 2004-03-31 | 2007-06-06 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
-
2004
- 2004-05-31 WO PCT/JP2004/007862 patent/WO2004109771A2/en active Application Filing
- 2004-05-31 EP EP04735511A patent/EP1636842B1/en not_active Expired - Fee Related
- 2004-05-31 KR KR1020057012181A patent/KR100778597B1/ko not_active IP Right Cessation
- 2004-05-31 CN CNB2004800017045A patent/CN100468719C/zh not_active Expired - Fee Related
- 2004-06-02 TW TW093115726A patent/TWI247373B/zh not_active IP Right Cessation
- 2004-06-02 US US10/860,478 patent/US7709942B2/en not_active Expired - Fee Related
-
2006
- 2006-05-30 HK HK06106292.6A patent/HK1086386A1/xx not_active IP Right Cessation
-
2008
- 2008-03-12 US US12/047,228 patent/US7615411B2/en not_active Expired - Fee Related
Cited By (18)
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US9378967B2 (en) | 2006-10-10 | 2016-06-28 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US8999810B2 (en) | 2006-10-10 | 2015-04-07 | Tessera, Inc. | Method of making a stacked microelectronic package |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
CN101861646B (zh) * | 2007-08-03 | 2015-03-18 | 泰塞拉公司 | 利用再生晶圆的堆叠封装 |
US8268674B2 (en) | 2007-08-08 | 2012-09-18 | Teramikros, Inc. | Semiconductor device and method for manufacturing the same |
US8846446B2 (en) | 2007-08-10 | 2014-09-30 | Samsung Electronics Co., Ltd. | Semiconductor package having buried post in encapsulant and method of manufacturing the same |
US8004089B2 (en) | 2008-01-31 | 2011-08-23 | Casio Computer Co., Ltd. | Semiconductor device having wiring line and manufacturing method thereof |
US7972903B2 (en) | 2008-01-31 | 2011-07-05 | Casio Computer Co., Ltd. | Semiconductor device having wiring line and manufacturing method thereof |
CN101499445B (zh) * | 2008-01-31 | 2012-05-30 | 兆装微股份有限公司 | 半导体器件及其制造方法 |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
CN105655316A (zh) * | 2014-11-27 | 2016-06-08 | 珠海越亚封装基板技术股份有限公司 | 具有与电容器串联的至少一个通孔的芯片用聚合物框架 |
CN109037188A (zh) * | 2017-06-08 | 2018-12-18 | 日月光半导体制造股份有限公司 | 半导体装置封装 |
US10475734B2 (en) | 2017-06-08 | 2019-11-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
CN109037188B (zh) * | 2017-06-08 | 2020-05-29 | 日月光半导体制造股份有限公司 | 半导体装置封装 |
CN111344858A (zh) * | 2017-11-17 | 2020-06-26 | 三菱电机株式会社 | 半导体模块 |
CN111344858B (zh) * | 2017-11-17 | 2024-04-16 | 三菱电机株式会社 | 半导体模块 |
Also Published As
Publication number | Publication date |
---|---|
TW200509270A (en) | 2005-03-01 |
US20040245614A1 (en) | 2004-12-09 |
TWI247373B (en) | 2006-01-11 |
CN100468719C (zh) | 2009-03-11 |
EP1636842B1 (en) | 2011-08-17 |
KR100778597B1 (ko) | 2007-11-22 |
EP1636842A2 (en) | 2006-03-22 |
US20080166836A1 (en) | 2008-07-10 |
US7615411B2 (en) | 2009-11-10 |
WO2004109771A3 (en) | 2005-03-24 |
US7709942B2 (en) | 2010-05-04 |
HK1086386A1 (en) | 2006-09-15 |
KR20050087872A (ko) | 2005-08-31 |
WO2004109771A2 (en) | 2004-12-16 |
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