JP5563814B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5563814B2 JP5563814B2 JP2009287903A JP2009287903A JP5563814B2 JP 5563814 B2 JP5563814 B2 JP 5563814B2 JP 2009287903 A JP2009287903 A JP 2009287903A JP 2009287903 A JP2009287903 A JP 2009287903A JP 5563814 B2 JP5563814 B2 JP 5563814B2
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- Prior art keywords
- connection terminal
- internal connection
- insulating layer
- semiconductor device
- layer
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Description
本半導体装置の製造方法は、複数の半導体チップ搭載領域と、前記複数の半導体チップ搭載領域を分離するスクライブ領域とが設けられ、主面側に保護膜を備えた支持基板を準備し、前記支持基板の主面の外縁部に第2電極パッドを形成する工程と、前記支持基板の前記スクライブ領域に前記保護膜を厚さ方向に貫通する溝部を形成する工程と、前記溝部を充填し、前記保護膜から突起する樹脂層を形成する工程と、主面に第1電極パッドが形成された半導体チップの裏面を、前記支持基板の前記主面の前記第2電極パッドの形成された領域の内側に固着する工程と、前記第1電極パッド上及び前記第2電極パッド上に、それぞれ第1内部接続端子及び第2内部接続端子を形成する工程と、前記支持基板の主面に、前記半導体チップ、前記第1内部接続端子、前記第2内部接続端子、及び前記樹脂層の突起部分を覆い、前記第1内部接続端子及び前記第2内部接続端子の一部を露出する第1絶縁層を形成する工程と、前記第1絶縁層上に、前記第1内部接続端子と前記第2内部接続端子とを電気的に接続する配線パターンを形成する工程と、前記第1絶縁層上に前記配線パターンを覆うように、前記配線パターンの一部を露出する開口部を有する第2絶縁層を形成する工程と、前記スクライブ領域の前記樹脂層を含む部分を切断し、前記支持基板、前記保護膜、及び前記第1絶縁層の外周側面に、前記保護膜を厚さ方向に貫通して前記支持基板と前記第1絶縁層の一部を構成する切り欠き部が樹脂で充填されている個片化された複数の半導体装置を作製する工程と、を有し、前記第2絶縁層を形成する工程において、前記開口部は、平面視において、前記第1内部接続端子よりも外側の領域に配置されることを要件とする。
図12は、第1の実施の形態に係る半導体装置を例示する断面図である。図12を参照するに、半導体装置10は、半導体チップ11と、第1内部接続端子12と、固着層13と、支持基板14と、第2内部接続端子15と、絶縁層16と、第1金属層28及び第2金属層29からなる配線パターン17と、ソルダーレジスト18と、外部接続端子19とを有する。
図29は、第2の実施の形態に係る半導体装置を例示する断面図である。図29に示す半導体装置30において、図12に示す半導体装置10と同一構成部分には同一符号を付し、その説明を省略する場合がある。図29を参照するに、第2の実施の形態に係る半導体装置30は、切り欠き部36Xを有し、切り欠き部36Xに樹脂層37Xが形成されている点を除いて、半導体装置10と同様に構成される。以下、半導体装置10と同一構成部分についての説明は省略し、半導体装置10と異なる部分を中心に説明する。
第3の実施の形態では、第1の実施の形態の図22及び図23に示す工程を、異なる工程(図36〜図38参照)に変更する例を示す。
11 半導体チップ
12 第1内部接続端子
12A、15A、16A、49A、49B 面
13 固着層
14 支持基板
15 第2内部接続端子
16 絶縁層
17 配線パターン
17A 外部接続端子配設領域
18 ソルダーレジスト
19 外部接続端子
21、25 半導体基板
22 半導体集積回路
23、26 電極パッド
24、27 保護膜
28 第1金属層
29 第2金属層
35 レジスト膜
36 溝部
36X 切り欠き部
37、37X 樹脂層
44 ダイシングブレード
49 板状体
A 半導体装置形成領域
B、E スクライブ領域
C、F 基板切断位置
D 半導体チップ搭載領域
D1 深さ
H1、H2 高さ
T1〜T4 厚さ
Claims (8)
- 支持基板と、
前記支持基板の主面に形成された第2電極パッドと、
前記第2電極パッドを露出して、前記支持基板の主面上に設けられた保護膜と、
前記第2電極パッド上に設けられた第2内部接続端子と、
前記第2電極パッドの形成された領域の内側において、前記保護膜上に固着された半導体チップと、
前記半導体チップの主面に形成された第1電極パッド上に設けられた第1内部接続端子と、
前記保護膜を介して前記支持基板の前記主面に形成され、前記半導体チップ、前記第1内部接続端子、及び前記第2内部接続端子を覆い、前記第1内部接続端子及び前記第2内部接続端子の一部を露出する第1絶縁層と、
前記第1絶縁層上に形成され、前記第1内部接続端子と前記第2内部接続端子とを電気的に接続する配線パターンと、
前記第1絶縁層上に前記配線パターンを覆うように形成され、前記配線パターンの一部を露出する開口部を有する第2絶縁層と、を有し、
前記開口部は、平面視において、前記第1内部接続端子よりも外側の領域に配置され、
前記支持基板、前記保護膜、及び前記第1絶縁層の外周側面に、前記保護膜を厚さ方向に貫通して前記支持基板と前記第1絶縁層の一部を構成する切り欠き部が形成され、前記切り欠き部は樹脂で充填されている半導体装置。 - 前記第1絶縁層は樹脂を主成分とし、
前記切り欠き部は前記第1絶縁層を構成する樹脂とは異なる樹脂で充填されている請求項1記載の半導体装置。 - 前記切り欠き部の表面は粗化面である請求項1又は2記載の半導体装置。
- 前記第1内部接続端子及び前記第2内部接続端子の一部は、前記第1内部接続端子及び前記第2内部接続端子の上面であり、
前記第1内部接続端子の上面、前記第2内部接続端子の上面、及び前記第1絶縁層の上面は面一である請求項1乃至3の何れか一項記載の半導体装置。 - 前記第1絶縁層の上面は粗化面である請求項1乃至4の何れか一項記載の半導体装置。
- 複数の半導体チップ搭載領域と、前記複数の半導体チップ搭載領域を分離するスクライブ領域とが設けられ、主面側に保護膜を備えた支持基板を準備し、前記支持基板の主面の外縁部に第2電極パッドを形成する工程と、
前記支持基板の前記スクライブ領域に前記保護膜を厚さ方向に貫通する溝部を形成する工程と、
前記溝部を充填し、前記保護膜から突起する樹脂層を形成する工程と、
主面に第1電極パッドが形成された半導体チップの裏面を、前記支持基板の前記主面の前記第2電極パッドの形成された領域の内側に固着する工程と、
前記第1電極パッド上及び前記第2電極パッド上に、それぞれ第1内部接続端子及び第2内部接続端子を形成する工程と、
前記支持基板の主面に、前記半導体チップ、前記第1内部接続端子、前記第2内部接続端子、及び前記樹脂層の突起部分を覆い、前記第1内部接続端子及び前記第2内部接続端子の一部を露出する第1絶縁層を形成する工程と、
前記第1絶縁層上に、前記第1内部接続端子と前記第2内部接続端子とを電気的に接続する配線パターンを形成する工程と、
前記第1絶縁層上に前記配線パターンを覆うように、前記配線パターンの一部を露出する開口部を有する第2絶縁層を形成する工程と、
前記スクライブ領域の前記樹脂層を含む部分を切断し、前記支持基板、前記保護膜、及び前記第1絶縁層の外周側面に、前記保護膜を厚さ方向に貫通して前記支持基板と前記第1絶縁層の一部を構成する切り欠き部が樹脂で充填されている個片化された複数の半導体装置を作製する工程と、を有し、
前記第2絶縁層を形成する工程において、前記開口部は、平面視において、前記第1内部接続端子よりも外側の領域に配置される半導体装置の製造方法。 - 前記第1絶縁層を形成する工程において、前記第1内部接続端子及び前記第2内部接続端子の一部は、前記第1内部接続端子及び前記第2内部接続端子の上面であり、
前記第1内部接続端子の上面、前記第2内部接続端子の上面、及び前記第1絶縁層の上面は面一となる請求項6記載の半導体装置の製造方法。 - 前記第1絶縁層の上面を粗面化する工程を含む請求項6又は7記載の半導体装置の製造方法。
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JP4599834B2 (ja) * | 2003-12-12 | 2010-12-15 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2005071745A1 (ja) * | 2004-01-27 | 2005-08-04 | Murata Manufacturing Co., Ltd. | 積層型電子部品およびその製造方法 |
JP2005327984A (ja) * | 2004-05-17 | 2005-11-24 | Shinko Electric Ind Co Ltd | 電子部品及び電子部品実装構造の製造方法 |
JP4398305B2 (ja) * | 2004-06-02 | 2010-01-13 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP2006041438A (ja) * | 2004-07-30 | 2006-02-09 | Shinko Electric Ind Co Ltd | 半導体チップ内蔵基板及びその製造方法 |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
JP4305502B2 (ja) * | 2006-11-28 | 2009-07-29 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP5067056B2 (ja) * | 2007-07-19 | 2012-11-07 | ソニー株式会社 | 半導体装置 |
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Cited By (2)
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US11355467B2 (en) | 2020-01-15 | 2022-06-07 | Samsung Electronics Co., Ltd. | Semiconductor devices including thick pad |
US11652076B2 (en) | 2020-01-15 | 2023-05-16 | Samsung Electronics Co., Ltd. | Semiconductor devices including thick pad |
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US20110260339A1 (en) | 2011-10-27 |
US20110151645A1 (en) | 2011-06-23 |
US8008123B2 (en) | 2011-08-30 |
US8330279B2 (en) | 2012-12-11 |
JP2011129767A (ja) | 2011-06-30 |
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