CN1519920A - 半导体器件和半导体器件的制造方法 - Google Patents
半导体器件和半导体器件的制造方法 Download PDFInfo
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- CN1519920A CN1519920A CNA2004100004456A CN200410000445A CN1519920A CN 1519920 A CN1519920 A CN 1519920A CN A2004100004456 A CNA2004100004456 A CN A2004100004456A CN 200410000445 A CN200410000445 A CN 200410000445A CN 1519920 A CN1519920 A CN 1519920A
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- H01L2924/3511—Warping
Abstract
本发明提供具有低价格且可对每一个半导体芯片进行测试而且没有芯片尺寸的制约的叠层CSP的半导体器件。把半导体芯片1的底面的整个面粘接到第1绝缘薄膜4上,把第2绝缘薄膜5粘接到半导体芯片1的上表面的整个面和第1绝缘薄膜4上。形成贯通第2绝缘薄膜5使半导体芯片1的上表面露出来的第1孔8,和贯通第1绝缘薄膜4和第2绝缘薄膜5的第2孔9和10。向第1孔8内埋入第1导体11,向第2孔9和10内埋入第2导体12和13。在第1绝缘薄膜4的表面之上形成电连到第2导体12和13上的第1布线15,在第绝缘薄膜5的表面之上形成电连到第1导体11和第2导体12和13上的第2布线14。
Description
技术领域
本发明涉及具有高密度装配封装的半导体器件,特别是涉及其装配封装的小型化和薄型化。
背景技术
近些年来,作为可在民用设备中使用的半导体器件装配封装,人们正在热中于高密度的芯片尺寸封装(CSF)的开发。其中,在装配封装内部叠层多个半导体芯片的被称之为封装内的系统(SiP)的叠层CSP的开发也很热门。在叠层CSP中,在基板之上重叠地装载多个半导体芯片,用引线键合技术进行结线、树脂密封。因此,就存在着2个问题。(1)必须把半导体芯片重叠为使得所有的半导体芯片的引线键合的焊盘都露出来。为此,归因于1个半导体芯片的芯片尺寸,就存在着别的半导体芯片会受到芯片尺寸的制约的问题。(2)由于在树脂密封后进行作为CSP的测试而不进行每一个半导体芯片的测试,故在每一个半导体芯片的成品率低的时候,就会存在着作为CSP的成品率将显著地降低的问题。这就是所谓的未知是否良好芯片(KGD)问题。
于是,人们就提出了把电子部件埋入到多层布线基板内的方法(例如参看专利文献1和专利文献2)。若用这些方法,则也可以对每一块多层布线基板都进行测试。但是,在这些方法中,存在着需要每一个半导体芯片的组装工序,或不能提高装配密度等的制约。
[专利文献1]
特许3212127号公报(图1)
[专利文献2]
特开2001-68624号公报
发明内容
本发明就是鉴于上述事情而发明的,目的在于提供本身为低价格且可以对每一个半导体芯片进行测试而且没有芯片尺寸的制约的高密度的叠层CSP的半导体器件。
此外,本发明的目的还在于提供具有低价格且可以对每一个半导体芯片进行测试而且没有芯片尺寸的制约的叠层CSP的半导体器件的制造方法。
目的为解决上述那些问题的本发明的第1特征的半导体器件具有:下表面具有第1平面的第1绝缘薄膜;配置在第1平面之下的第1布线层;配置在第1绝缘薄膜之上的第1半导体芯片;配置在第1半导体芯片和第1绝缘薄膜之上,上表面具有第2平面的第2绝缘薄膜;配置在第2平面之上,电连到第1半导体芯片上的第2布线层;贯通第1绝缘薄膜和第2绝缘薄膜电连到第1布线层和第2布线层上的第1导体柱;贯通第2绝缘薄膜电连到第1半导体芯片和第2布线层上的导体。
本发明的第2特征的半导体器件具有:上表面具有第1平面的导体板;配置在第1平面之上的粘接层;配置在粘接层之上的第1半导体芯片;配置在第1半导体芯片和导体板之上,上表面具有第2平面的第1绝缘薄膜;配置在第2平面之上,电连到第1半导体芯片上的第1布线层。
本发明的第3特征的半导体器件的制造方法包括:把半导体芯片的底面的整个面粘接到第1绝缘薄膜上把第2绝缘薄膜粘接到半导体芯片的上表面的整个面和第1绝缘薄膜上;形成贯通第2绝缘薄膜,使半导体芯片的上表面露出来的第1孔,贯通第1绝缘薄膜和第2绝缘薄膜的第2孔;向第1孔内埋入第1导体和向第2孔内埋入第2导体;在第1绝缘薄膜的表面之上形成电连到第2导体上的第1布线,在第2绝缘薄膜的表面之上形成电连到第1导体和第2导体上的第2布线。
本发明的第4特征的半导体器件的制造方法包括:使半导体芯片的底面的整个面粘接到金属板上,把第1绝缘薄膜粘接到半导体芯片的上表面整个面和金属板上;形成贯通第1绝缘薄膜使半导体芯片的上表面露出来的孔;向孔内埋入第1导体;在第1绝缘薄膜的表面之上形成电连到第1导体上的第1布线。
附图说明
图1(a)是实施形态1的半导体器件的俯视图。(b)是(a)的I-I方向的剖面图。
图2是实施形态1的半导体器件的制造途中的剖面图(其1)。
图3是实施形态1的半导体器件的制造途中的剖面图(其2)。
图4是实施形态1的半导体器件的制造途中的剖面图(其3)。
图5是实施形态2的半导体器件的剖面图。
图6是实施形态3的半导体器件的剖面图。
图7是实施形态4的半导体器件的剖面图。
图8是实施形态5的半导体器件的剖面图。
图9(a)是实施形态6的半导体器件的俯视图。(b)是(a)的I-I方向的剖面图。
图10是实施形态6的半导体器件的制造途中的剖面图(其1)。
图11是实施形态6的半导体器件的制造途中的剖面图(其2)。
图12是实施形态6的半导体器件的制造途中的剖面图(其3)。
图13是图7的实施形态的半导体器件的剖面图。
图14(a)是实施形态8的半导体器件的俯视图。(b)是(a)的I-I方向的剖面图。
图15是实施形态8的半导体器件的制造途中的剖面图(其1)。
图16是实施形态8的半导体器件的制造途中的剖面图(其2)。
具体实施方式
其次,参看附图,对本发明的实施形态进行说明。在以下的图面的记载中,对于同一或类似的部分都赋予了同一或类似的标号。此外,图面是模式性的图面,应当留意厚度和平面尺寸之间的关系、各层的厚度的比率等与现实的上述关系和比率是不同的。
(实施形态1)
本发明的实施形态1的半导体器件33,如图1所示,具有绝缘薄膜4、5,布线层14、15,半导体芯片1,导体柱11到13,导电球17。半导体器件33构成有所谓的封装。
绝缘薄膜4下表面具有平面。该平面配置在从半导体芯片1的下方到侧下方的下方。绝缘薄膜4是树脂。作为树脂,使用可密封半导体芯片1的树脂。说得更具体点,使用堆积基板的叠层用树脂。例如可以使用(日本)味之素株式会社的商品名为ABF的树脂。
布线层15,配置在从半导体芯片1的下方到侧方下方的绝缘薄膜4的下表面的平面之下。布线层15具有再布线图形。
半导体芯片1的两个表面和侧面,已用绝缘薄膜4和5密封起来。半导体芯片1配置在绝缘薄膜4之上。半导体芯片1具有半导体衬底2和半导体元件形成区3。半导体元件形成区3配置在半导体衬底2之上。半导体元件形成区3具有电极。
绝缘薄膜5配置在半导体芯片1和绝缘薄膜4之上。绝缘薄膜5使用与绝缘薄膜4同样的树脂。绝缘薄膜5的上表面具有平面。该平面配置在从半导体芯片1的上方到侧方的上方。如图2(b)所示,绝缘薄膜4的半导体芯片1的下方的膜厚d2,与绝缘薄膜5的第1半导体芯片1的上方的膜厚d3相等。绝缘薄膜4的半导体芯片1的侧方的膜厚d4与绝缘薄膜5的第1半导体芯片1的侧方的膜厚d5相等。
布线层14,具有再布线图形。布线层14的再布线图形,电连到半导体芯片1的电极上。布线层14,配置在从半导体芯片1的上方到侧方的上方的绝缘薄膜5的上表面的平面之上。
导体柱12和13,构成贯通电极用的通路。导体柱12贯通绝缘薄膜5。导体柱13贯通绝缘薄膜4。导体柱12和13,已电连到布线层14和15上。导体柱12和13,配置在半导体芯片1的侧方。导体柱12和13,配置在半导体芯片1的外周上。导体柱12和13配置在半导体器件33的外围部分上。
本身为通路的导体柱11,贯通绝缘薄膜5。导体柱11已电连到半导体芯片1的电极和布线层14上。
成为装配用球的导电球17,电连接到布线层15上。导体柱11配置在半导体芯片1的外围部分上。
实施形态1的半导体器件,可作为单体的薄型CSP使用。就是说,是半导体器件单体,可以进行半导体芯片1的测试。
半导体器件,由于在上表面和下表面这两方上具有布线层14和15,故可以采用将多个半导体器件叠层,把多个半导体器件的彼此的布线层14和15连接起来的办法构成叠层CSP。
考虑半导体器件的厚度。半导体芯片1的厚度是50微米,在半导体芯片1之上和下边的绝缘薄膜4和5的厚度分别可以作成为30到40微米。借助于此,半导体器件的厚度就变成为每一者的合计的110到130微米。可以实现薄的薄型CSP。
其次,对本发明的实施形态1的半导体器件的制造方法进行说明。
首先,如图2(a)所示,既可以使用粘结装置6、7,或者也可以使用压力辊子。粘结装置的样品台6和压力台7的表面是平面。把本身为堆叠基板的叠层用树脂薄膜的绝缘薄膜4载置到粘结装置的样品台6之上。使得每一个半导体芯片1的底面的整个面都接触到绝缘薄膜4之上那样地,把多个半导体芯片1装载到绝缘薄膜4之上。使得每一个半导体芯片1的上表面的整个面都接触到绝缘薄膜5上那样地,把绝缘薄膜5装载到多个半导体芯片1之上。作为绝缘薄膜5,使用与绝缘薄膜4同一材质且同一膜厚的绝缘薄膜。在绝缘薄膜5之上配置粘结装置的压力台7。
在粘结装置的样品台6和压力台7之间,压缩绝缘薄膜4、5和半导体芯片1。借助于此,从两面用绝缘薄膜4和5层压半导体芯片1。半导体芯片1和绝缘薄膜4和5形成一体化。可以把半导体芯片1的底面整个面都粘接到绝缘薄膜4上。可以把绝缘薄膜5粘接到半导体芯片1的上表面的整个面和绝缘薄膜4上。使得绝缘薄膜4的下表面和绝缘薄膜5的上表面之间的间隔,在有半导体芯片1的地方(d1+d2+d3)和无半导体芯片1的地方(d4+d5)变成为相等。这是因为在进行压缩时,在半导体芯片1的正下边的绝缘薄膜4和半导体芯片1的正之上的绝缘薄膜5上会产生大的压缩应力,为缓和该压缩应力绝缘薄膜4和5要产生变形的缘故。绝缘薄膜4的膜厚,在有半导体芯片1的地方(d2),比没有半导体芯片1的地方(d4)更薄。绝缘薄膜5的膜厚,有半导体芯片1的地方(d3),比没有半导体芯片1的地方(d5)更薄。为了促进变形,要加大压缩应力。要想加大压缩应力,压力辊子比起压力台7更有利。此外,为了促进变形,可以提高绝缘薄膜4和5的流动性。为此,只要提高绝缘薄膜4和5的温度即可。
另外,作为绝缘薄膜5,由于使用的是与绝缘薄膜4同一材质且同一膜厚的绝缘薄膜,故在有半导体芯片1的地方,绝缘薄膜5的膜厚(d3)与绝缘薄膜4的膜厚(d2)将变得相等。同样,在没有半导体芯片1的地方,绝缘薄膜5的膜厚(d5)与绝缘薄膜4的膜厚(d4)将变得相等。由于可以像这样地使绝缘薄膜4和5的变形量变成为相等,故可以使残留应力的向量也对于半导体芯片1面对称地发生。借助于此,在半导体芯片1上就不会产生挠曲。
其次,向两面中的每一者上,涂敷光刻胶并使之图形化。以图形化后的光刻胶为掩模进行绝缘薄膜4和5的刻蚀。如图3(c)所示,就可以形成成为通路孔的孔8到10。孔8到10的形成,可与通常的堆叠工序同样地实施。孔8贯通绝缘薄膜5。孔8使半导体芯片1的上表面露出来。孔9贯通绝缘薄膜5。孔10贯通绝缘薄膜4。孔9在孔10的正上方形成。借助于此,就可以设置贯通电极。
其次,用电镀法在露出面之上形成导体膜。借助于此,如图3(d)所示,就可以把导体柱11埋入到孔8内。同样,可以把导体柱12埋入到孔9内。可以把导体柱13埋入到孔10内。此外,还可以在绝缘薄膜4的表面之上形成布线层15。可以在绝缘薄膜5的表面之上形成布线层14。所形成的导体膜,由于是连续的膜,故会把导体柱12和13电连起来。同样,把布线层15和导体柱13电连起来。把布线层14和导体柱12电连起来。把布线层14和导体柱11电连起来。
其次,向两面中的每一者上,涂敷光刻胶并使之图形化。以图形化后的光刻胶为掩模进行布线层14和15的刻蚀。如图4(e)所示,就可以形成具有已图形化的布线的布线层14和15。
另外,上述的布线层14、15的布线图形的生成,作为原则要使用部分添加法(semi-additive)。说明该工艺。首先,用无电解电镀法在露出面上形成薄铜箔。借助于此,就确保了要在后边进行的电解电镀时的导通。其次,借助于光刻胶膜形成布线层14和15的负掩模。进行电解电镀,形成成为通路孔插针的导体柱11到13和已被图形化为负掩模的反转图形的布线层14和15。剥离光刻胶膜。用刻蚀法除去薄铜箔。
其次,在切断面16处切断绝缘薄膜4、5,如图4(f)所示,把多个半导体芯片1分离成个片。
最后,如图1(a)和图1(b)所示,在布线层15之下形成外部电极用的导电球17。另外,使多个半导体芯片1向个片的分离和导电球的形成的顺序,没有什么限制。
倘采用实施形态1的半导体器件的制造方法,则可以以具有多个半导体芯片1的叠层绝缘薄膜4、5的薄片单位一次地实施过去分别地实施现有的实施堆叠基板制造工序、突点工序、组装工序(倒装芯片、树脂密封)中的每一者的多个工序。借助于此,就会大幅度地提高半导体器件的生产性。
实施形态1的半导体器件的制造方法,可以认为是在本身为所谓的堆叠基板制造工序的绝缘薄膜4和5的叠层的工序中把半导体芯片1埋入到绝缘薄膜4和5内。因此,可以对于已埋入了半导体芯片1的绝缘薄膜4和5的叠层薄膜灵活运用通常的堆叠基板制造工序。反之,若对于通常的堆叠基板制造工序,用实施形态1的半导体器件的制造方法,则可以认为不需要堆叠基板的核心基板。或者,若使用实施形态1的半导体器件的制造方法,则可以认为已埋入了半导体芯片1的绝缘薄膜4和5的叠层薄膜,相当于已组装好的堆叠基板,同时,是堆叠基板的核心基板。就是说,采用省略核心基板的制造,或者,同时进行核心基板的制造和堆叠基板的组装的办法,就可以缩短半导体器件的制造方法的工序。而且,由于以薄片单位进行制造,故可以实现组装成本的降低。
此外,由于不存在现有的核心基板,故半导体器件的厚度将由半导体芯片1和绝缘薄膜4和5的厚度决定。借助于此,就可以把半导体器件的厚度设定在110到130微米的范围内。此外,由于绝缘薄膜4和5对于半导体芯片1变成为上下对称构造,故可以防止因半导体芯片1和绝缘薄膜4、5的膨胀系数的不同而产生的挠曲。
(实施形态2)
本发明的实施形态2的半导体器件,如图5所示,具有实施形态1的半导体器件33和34。半导体器件33和34中的每一者都构成所谓的封装,借助于半导体器件33和34,构成叠层型多芯片组件。
半导体器件34,配置在在半导体器件33的上层之上。半导体器件34的导电球47,配置、电连到半导体器件33的布线层14之上。导电球47,配置、电连到半导体器件34的布线层15之下。另外,半导体器件33的半导体芯片1和半导体器件34的半导体芯片1,既可以具有同一构造、同一功能,也可以具有不同的构造和功能,特别是可以具有不同的大小。此外,半导体器件33和34,并不限于2个,也可以重叠为3个以上。
半导体器件33和34,在进行叠层之前,要分别进行测试。然后叠层要使用测试合格的半导体器件33和34。因此,可以提高叠层后的半导体器件的成品率。
(实施形态3)
本发明的实施形态3的半导体器件,如图6所示,除去实施形态1的半导体器件33之外,还具有绝缘薄膜18和22,布线层20,导体柱19和23。
绝缘薄膜22,配置在绝缘薄膜4和布线层15之下。绝缘薄膜22的下表面,具有平面。
绝缘薄膜18配置在绝缘薄膜5和第2布线层14之上。绝缘薄膜18的上表面,具有平面。绝缘薄膜22的膜厚,是一定的,与在上方有无半导体芯片1无关。绝缘薄膜18的膜厚,是一定的,与在下方有无半导体芯片1无关。绝缘薄膜18和22的膜厚相等。因此,半导体芯片1不会进行挠曲。为此,要使得用同一材料且同一膜厚的薄膜、使粘接条件变成为相同那样地,同时粘接到绝缘薄膜18和22上。借助于此,就可以使粘接时的温度和压力变成为相同。
布线层20配置在绝缘薄膜18的平面之上。布线层20电连接到布线层14上。
导体柱19贯通绝缘薄膜18。导体柱19电连到布线层14和20上。导体柱23贯通绝缘薄膜22。导体柱23电连到布线层15和导电球17上。
实施形态3的半导体器件,可以采用除去实施形态1的半导体器件的制造方法之外,还要实施表面和背面这两面同时的堆叠工序的办法完成。实施形态3的半导体器件,变成为具有3层的布线层14、15、20的多层布线构造。布线层的层数可根据需要增加。
(实施形态4)
本发明的实施形态4的半导体器件,如图7所示,除去实施形态1的半导体器件33之外,还具有贯通半导体芯片1电连到布线层14和15上的导体柱25、26、28。
半导体芯片1,除去半导体衬底2和半导体元件形成层3之外,还具有成为穿通插针的导体柱25和绝缘膜24。导体柱25从半导体衬底2的表面达到背面。在导体柱25的正上方,设置导体柱26。在导体柱25的正下边设置导体柱28。导体柱25,要电连到导体柱26和28上。绝缘膜24设置在半导体衬底2和导体柱25之间。在导体柱26之上设置有与布线层14同一层的布线27。在导体柱28之下,设置有与布线层15同一层的布线29。在布线层29之下设置有导电球30。导电球30的形状与导电球17等同。
借助于此,就可以在半导体器件的表面的整个面和背面的整个面上配置电极。为此,只要从半导体器件的两面进行通路孔的开口,使得可以从半导体芯片1的两面连接到导体柱25上即可。由于在半导体器件的表面和背面的整个面上都配置电极,故可以确保封装尺寸的比较多的引脚数,可以期待装配密度的提高。
此外,导体柱25要在半导体芯片1的前工序(Cu布线电镀)中形成。导体柱25由于非常接近半导体元件形成区3,故可以采用从那里直接用导体柱26、28进行电极引出的办法,来大幅度地减少布线长度。
例如,考虑2段叠层10mm见方的半导体芯片1,对配置在半导体芯片1的中央的半导体元件彼此间进行结线的情况。在在半导体芯片1的周围设置导体柱12和13的情况下,最短也需要5mm+5mm(半导体芯片1的长度的一半的来回量)+0.1mm(半导体器件3 3的厚度)+0.2mm(从半导体芯片1边缘到导体柱12和13为止的距离),布线长度的合计变成为10.3mm。另一方面,倘采用实施形态4的半导体器件,由于可以缩短半导体芯片1的长度的一半的来回量,故布线长度将变成为0.3mm。这样一来,就可以进行大幅度的布线长度的缩短,可以减小布线间的电感。就可以把实施形态4的半导体器件应用于高速动作装置。
(实施形态5)
本发明的实施形态5的半导体器件,如图8所示,与实施形态1的半导体器件33不同,具有突点32,来取代导体柱11。
半导体芯片1,除去半导体衬底2和半导体元件形成层3之外,还具有本身为导体柱的突点32。半导体元件形成层3,在表面之上具有电极焊盘31,突点32将配置在电极焊盘31之上。突点32已电连到电极焊盘上。突点32贯通绝缘薄膜5,配置在布线层14之下。突点32连接到布线层14上。
在实施形态5的半导体器件中,在使半导体芯片1和绝缘薄膜4和5进行叠层以进行一体化之前,要在半导体芯片1的电极焊盘31之上形成突点32。在进行叠层时,在位于突点32的正上方的绝缘薄膜5内将产生高的压缩应力,从突点32的正上方除去绝缘薄膜5,使突点32的上部露出来。突点32既可以是柱状突点,也可以是电镀突点。在实施形态5的半导体器件中,在用电解电镀形成导体柱12和13的导体柱11时,不需要使得同时结束埋入那样地对彼此的电镀速度进行调整。可以缩短用来形成布线层14和15和导体柱12和13的电解电镀的电镀时间。如上所述,电解电镀的工艺窗口可以扩展,可容易地进行工艺管理。
(实施形态6)
本发明的实施形态6的半导体器件,如图9所示,具有导体板35、粘接层36、半导体芯片1、绝缘薄膜5和18、布线层14、导体柱23和导电球17。
导体板35,上表面具有平面。导体板35需要一定的强度,以便把布线层14配置在一个平面之上。但是,在半导体器件的制造工序中,只要具有可把布线层14配置在一个平面之上的强度就是充分的。为确保半导体器件的使用上的强度,可把散热用的散热片或热沉固定到导体板35之下。借助于此,就可以把导体板35形成得薄到即便是把绝缘薄膜5和18合在一起也可以容易地切断的那种程度。作为导体板35也可以使用所谓的导体箔。
粘接层36,配置在导体板35的上表面的平面之上。半导体芯片1配置在粘接层36之上。绝缘薄膜5配置在半导体芯片1和导体板35之上。绝缘薄膜5的上表面,具有平面。该平面配置在半导体芯片1的侧方之上。
布线层14,配置在绝缘薄膜5的上表面的平面之上。布线层14电连到半导体芯片1上。绝缘薄膜18配置在布线层18和绝缘薄膜5之上。导体柱23,贯通绝缘薄膜18。导体柱23电连到布线层14和导电球17上。导电球17则电连到布线层14上。
实施形态1的半导体器件,适合于引脚少的领域的半导体芯片1,相对于此,实施形态6的半导体器件适合于引脚多的领域的半导体芯片1。实施形态6的半导体器件,与半导体芯片1的半导体元件形成区3相反的面的密封不是用绝缘薄膜而是用金属板等的导体板35形成。采用把该导体板35作成为硬板的办法,就可以制作可确保半导体器件的封装的刚性,不依赖于半导体芯片1的芯片尺寸的、比芯片尺寸大的半导体器件。借助于此,就可以提供可应用于多引脚领域的半导体芯片1的大型多引脚封装。
此外,可以通过导体板35使在多引脚领域的半导体芯片1内发生的大量的热散热,可以减小半导体器件的热电阻。导体板35起着散热板或热沉的作用。
因此,导体板35的材质,在重视散热的情况下,理想的是铜(Cu)或铜合金。在不需要散热,仅仅想要增多本身为外部引脚的导电球17的情况下,和在想要作成为对于芯片尺寸加大封装尺寸的扇出构造的情况下,作为导体板35,也可以使用便宜的铝合金板,或为了与半导体芯片1的线膨胀系数相吻合而使用陶瓷板。
其次,对本发明的实施形态6的半导体器件的制造方法进行说明。
首先,如图10(a)所示,使用粘结装置7。粘结装置的压力台7的表面是平面。使得每一个半导体芯片1的底面的整个面都接触到金属板35上那样地使多个半导体芯片1载置到金属板35之上。使得每一个半导体芯片1的上表面的整个面都接触到绝缘薄膜5上那样地把绝缘薄膜5载置到多个半导体芯片1之上。作为绝缘薄膜5,使用的是与绝缘薄膜4同一材质且同一膜厚的绝缘薄膜。把粘结装置的压力台7配置到绝缘薄膜5之上。
在金属板35和粘结装置的压力台7之间,压缩绝缘薄膜5和半导体芯片1。另外,在该压缩时金属板35变形的情况下,也可以在金属板35之下配置可保持平坦状态不变地固定金属板35的样品台。如图10(b)所示,用金属板35和绝缘薄膜5使半导体芯片1进行叠层。金属板35、半导体芯片1和绝缘薄膜5进行一体化。可以使半导体芯片1的底面的整个面都粘接到金属板35上。可以使绝缘薄膜5粘接到半导体芯片1的上表面的整个面和金属板35上。使金属板35的上表面与绝缘薄膜5的上表面之间的间隔,在有半导体芯片1的地方(d1+d3+d6)和没有半导体芯片1的地方(d5)处相等。这是因为在进行压缩时,在半导体芯片1的正上方的绝缘薄膜5上会产生大的压缩应力,为缓和该压缩应力绝缘薄膜5要产生变形的缘故。绝缘薄膜5的膜厚,在有半导体芯片1的地方(d3)处比没有半导体芯片1的地方(d5)更薄。
其次,涂敷绝缘薄膜5、光刻胶并使之图形化。以图形化后的光刻胶为掩模,进行绝缘薄膜5的刻蚀。如图11(c)所示,可以形成成为通路孔的孔8和41。孔8、41贯通绝缘薄膜5。孔8、41,使半导体芯片1的上表面露出来。
其次,用电镀法在露出面之上形成导体膜。借助于此,如图11(d)所示,就可以向孔8、41中埋入导体柱11、42。就可以在绝缘薄膜5的表面之上形成布线层14。所形成的导体膜,由于是连续的膜,故会把布线层14和导体柱11、42电连起来。
其次,向布线层14之上涂敷光刻胶并使之图形化。以图形化后的光刻胶为掩模进行布线层14的刻蚀。如图11(e)所示,就可以形成具有已图形化的布线的布线层14。另外,布线层14的形成,也可以使用部分添加法。
其次,如图12(f)所示,把绝缘薄膜18粘接到布线层14之上。如图12(g)所示,在绝缘薄膜18的布线层14的上方,形成孔43、44。在切断面16处切断绝缘薄膜5、18和导体板35,把多个半导体芯片1分离成个片。
最后,如图9(a)和图9(b)所示,在孔43、44中形成导体柱23、38,在导体柱23、38之上形成导电球17。另外,使多个半导体芯片1向个片的分离和导电柱23、38与导电球17的形成的顺序,没有什么限制。
倘采用实施形态6的半导体器件的制造方法,则可以以具有多个半导体芯片1的把金属板35和绝缘薄膜5叠层起来的薄片单位一次地实施过去分别地实施现有的堆叠基板制造工序、突点工序、组装工序(倒装芯片、树脂密封)中的多个工序。借助于此,就会大幅度地提高半导体器件的生产性。
(实施形态7)
本发明的实施形态7的半导体器件,如图13所示,具有实施形态6的半导体器件40和实施形态1至3的半导体器件45。半导体器件40和45中的每一者,都构成所谓的封装,并借助于半导体器件40和45,构成叠层型多芯片组件。
半导体器件45,配置在半导体器件40的上层之上。半导体器件40的导电球17,配置、电连到半导体器件45的导体柱19之下。半导体器件45的导体柱19配置、电连到半导体器件45的布线层14之下。半导体器件40和45,并不限于2个,也可以重叠为3个以上。
半导体器件40和45,在进行叠层之前,要分别进行测试。然后叠层使用测试合格的半导体器件40和45。因此,可以提高叠层后的半导体器件的成品率。
此外,半导体器件45,由于在外围部分的宽广的区域中,未配置半导体芯片1,故若使用半导体器件45单体,则有时候使用时的强度不足。即便是在该情况下,采用用半导体器件40的导电球17固定半导体器件40和45的办法,作为半导体器件40和45全体,就可以确保使用时的强度。由此可知:半导体器件40的半导体芯片1和半导体器件45的半导体芯片1,完全不会相互地受芯片尺寸的影响。
(实施形态8)
本发明的实施形态8的半导体器件,如图14所示,与实施形态1的半导体器件33不同,穿通插针12、13、25贯通半导体芯片1。
半导体芯片1,具有半导体衬底2、半导体元件形成区3、导体柱25和绝缘膜24。导体柱25,从半导体衬底2的表面到达背面,并电连到导体柱12和13上。绝缘膜24,设置在半导体衬底2与导体柱25之间。
其次,对本发明的实施形态8的半导体器件的制造方法进行说明。
首先,如图15(a)所示,使用具有压力窖的粘结装置6、7。把本身为堆叠基板的叠层用树脂薄膜的绝缘薄膜4载置到粘结装置的样品台6之上。使得每一个半导体芯片1的底面的整个面都接触到绝缘薄膜4上那样地,把多个半导体芯片1载置到绝缘薄膜4之上。使得每一个半导体芯片1的上表面的整个面都接触到绝缘薄膜5上那样地把绝缘薄膜5载置到多个半导体芯片1之上。作为绝缘薄膜5,使用与绝缘薄膜4同一材质且同一膜厚的绝缘薄膜。在绝缘薄膜5之上配置粘结装置的压力台7。
在粘结装置的压力窖内的样品台6和压力台7之间,压缩绝缘薄膜4、5和半导体芯片1。借助于此,如图15(b)所示,从两面用绝缘薄膜4和5把半导体芯片1叠层起来。可以使半导体芯片1的底面的整个面都粘接到绝缘薄膜4上。可以使绝缘薄膜5粘接到半导体芯片1的上表面的整个面和绝缘薄膜4上。在进行压缩时,由于可以给绝缘薄膜4的整个面和绝缘薄膜5的整个面加上均一的压力,故绝缘薄膜4的膜厚,在有半导体芯片1的地方(d7)和无半导体芯片1的地方(d4)处相等。绝缘薄膜5的膜厚,在有半导体芯片1的地方(d8)和无半导体芯片1的地方(d5)处相等。在半导体芯片1间,粘接绝缘薄膜4和5。
另外,由于作为绝缘薄膜5使用与绝缘薄膜4同一材质且同一膜厚的绝缘薄膜,故绝缘薄膜5的膜厚(d5、d8)和绝缘薄膜4的膜厚(d4、d7)就变成为相等。借助于此,在半导体芯片1上就不会产生挠曲。
其次,向两面中的每一者上都涂敷光刻胶并使之图形化。以图形化后的光刻胶为掩模进行绝缘薄膜4、5的刻蚀。如图16(c)所示,可以形成成为通路孔的孔8到孔10。孔8贯通绝缘薄膜5。孔8使半导体芯片1的上表面露出来。孔9贯通绝缘薄膜5,在导体柱25的正上方形成。孔10贯通绝缘薄膜4在导体柱25的正下边形成。借助于此,就可以设置贯通电极。
其次,借助于电镀法在露出面之上形成导体膜。借助于此,如图16(d)所示,就可以向孔8到10中埋入导体柱11到13。此外,还可以在绝缘薄膜4、5的表面之上形成布线层14、15。
其次,向两面中的每一者上都涂敷光刻胶并使之图形化。以图形化后的光刻胶为掩模进行布线层14、15的刻蚀。如图16(e)所示,可以形成具有已图形化的布线的布线层14和15。另外,在布线层14和15的形成中,也可以使用部分添加法。在切断面16处切断绝缘薄膜4、5,把多个半导体器件分离成个片。最后,如图14所示,在布线层15之下形成导电球17。
倘采用实施形态8的半导体器件的制造方法,则可以得到与实施形态1同样的效果,可以以具有多个半导体芯片1的叠层绝缘膜4、5的薄片单位一次地实施过去分别地实施现有的堆叠基板制造工序、突点工序、组装工序(倒装芯片、树脂密封)中的多个工序。借助于此,就会大幅度地提高半导体器件的生产性。特别是实施形态8的半导体器件的制造方法,在绝缘薄膜4、5不进行流动性的变形的情况下可以应用。
如上所述,倘采用本发明,则可以提供低价格且可以对每一个半导体芯片进行测试而且没有芯片尺寸的制约的叠层CSP的半导体器件。
此外,倘采用本发明,则可以提供具有低价格且可以对每一个半导体芯片进行测试而且没有芯片尺寸的制约的叠层CSP的半导体器件的制造方法。
Claims (20)
1.一种半导体器件,其特征在于具有:
下表面具有第1平面的第1绝缘薄膜;
配置在上述第1平面之下的第1布线层;
配置在上述第1绝缘薄膜之上的第1半导体芯片;
配置在上述第1半导体芯片和上述第1绝缘薄膜之上,上表面具有第2平面的第2绝缘薄膜;
配置在上述第2平面之上,电连到上述第1半导体芯片上的第2布线层;
贯通上述第1绝缘薄膜和上述第2绝缘薄膜电连到上述第1布线层和上述第2布线层上的第1导体柱;
贯通上述第2绝缘薄膜,电连到上述第1半导体芯片和上述第2布线层上的导体。
2.根据权利要求1所述的半导体器件,其特征在于:上述第2平面比上述第1半导体芯片的上表面更宽。
3.根据权利要求1或2所述的半导体器件,其特征在于:上述第1半导体芯片,具有:半导体衬底;从上述半导体衬底的表面达到背面,电连到上述第1导体柱上的第2导体柱;设置在上述半导体衬底与上述第2导体柱之间的绝缘膜。
4.根据权利要求1或2所述的半导体器件,其特征在于:上述第1导体柱配置在上述第1半导体芯片的侧方。
5.根据权利要求1或2所述的半导体器件,其特征在于:还具有电连到上述第1布线层上的导电球。
6.根据权利要求1或2所述的半导体器件,其特征在于:上述第1绝缘薄膜在上述第1半导体芯片的下方的膜厚,与上述第2绝缘薄膜在上述第1半导体芯片的上方的膜厚相等。
7.根据权利要求1或2所述的半导体器件,其特征在于至少还具有:
配置在上述第1绝缘薄膜和上述第1布线层之下,下表面具有第3平面的第3绝缘薄膜;
配置在上述第3平面之下,电连到上述第1布线层上的第3布线层;
配置在上述第2绝缘薄膜和上述第2布线层之上,上表面具有第4平面的第4绝缘薄膜;
配置在上述第4平面之上,电连到上述第2布线层上的第4布线层。
8.根据权利要求7所述的半导体器件,其特征在于:上述第3绝缘薄膜的膜厚,与上述第4绝缘薄膜的膜厚相等。
9.根据权利要求1或2所述的半导体器件,其特征在于还具有:
电连到上述第2布线层上的导电球;
下表面具有第5平面的第5绝缘薄膜;
配置在上述第5平面之下,电连到上述导电球上的第5布线层;
配置在上述第5绝缘薄膜之上的第2半导体芯片;
配置在上述第2半导体芯片和上述第5绝缘薄膜之上,上表面具有第6平面的第6绝缘薄膜;
配置在上述第6平面之上,电连到上述第2半导体芯片上的第6布线层;
贯通上述第5绝缘薄膜和上述第6绝缘薄膜,电连到上述第5布线层和上述第6布线层上的第3导体柱。
10.根据权利要求1或2所述的半导体器件,其特征在于:上述第1半导体芯片,具有:半导体衬底;从上述半导体衬底的表面达到背面,电连到上述第1布线层和上述第2布线层上的第4导体柱;设置在上述半导体衬底和上述第4导体柱之间的绝缘膜。
11.一种半导体器件,其特征在于具有:
上表面具有第1平面的导体板;
配置在上述第1平面之上的粘接层;
配置在上述粘接层之上的第1半导体芯片;
配置在上述第1半导体芯片和上述导体板之上,上表面具有第2平面的第1绝缘薄膜;
配置在上述第2平面之上,电连到上述第1半导体芯片上的第1布线层。
12.根据权利要求11所述的半导体器件,其特征在于:上述第2平面,配置在上述第1半导体芯片的侧方的上方。
13.根据权利要求11或12所述的半导体器件,其特征在于:还具有电连到上述布线层上的第1导电球。
14.根据权利要求11或12所述的半导体器件,其特征在于:还具有:
下表面具有第3平面的第2绝缘薄膜;
配置在上述第3平面之下,电连到上述第1导电球上的第2布线层;
配置在上述第2绝缘薄膜之上,电连到上述第2布线层上的第2半导体芯片;
配置在上述第2半导体芯片和上述第2绝缘薄膜之上,上表面具有第4平面的第3绝缘薄膜;
配置在上述第4平面之上的第3布线层;
贯通上述第2绝缘薄膜和上述第3绝缘薄膜,电连到上述第2布线层和上述第3布线层上的第1导体柱。
15.一种半导体器件的制造方法,其特征在于包括:
把半导体芯片的底面的整个面粘接到第1绝缘薄膜上把第2绝缘薄膜粘接到上述半导体芯片的上表面的整个面和第1绝缘薄膜上;
形成贯通上述第2绝缘薄膜,使上述半导体芯片的上述上表面露出来的第1孔,贯通上述第1绝缘薄膜和上述第2绝缘薄膜的上述第2孔;
向上述第1孔内埋入第1导体和向上述第2孔内埋入第2导体;
在上述第1绝缘薄膜的表面之上形成电连到上述第2导体上的第1布线,在上述第2绝缘薄膜的表面之上形成电连到上述第1导体和上述第2导体上的第2布线。
16.根据权利要求15所述的半导体器件的制造方法,其特征在于:
上述半导体芯片是多个,
在形成了上述第2布线之后,切断上述第1绝缘薄膜和上述第2绝缘薄膜,分离成每一个上述半导体芯片。
17.根据权利要求15或16所述的半导体器件的制造方法,其特征在于:
上述半导体芯片是多个,
还包括:在一个上述半导体芯片的上述第2布线的上方配置另一个上述半导体芯片的上述第1布线,把一个上述半导体芯片的上述第2布线和另一个上述半导体芯片的上述第1布线电连起来。
18.根据权利要求15或16所述的半导体器件的制造方法,其特征在于:通过粘接上述第2绝缘薄膜,使上述第1绝缘薄膜的下表面和上述第2绝缘薄膜的上表面之间的间隔,在有半导体芯片的地方和无半导体芯片的地方相等。
19.根据权利要求15或16所述的半导体器件的制造方法,其特征在于:通过粘接上述第2绝缘薄膜,使上述第1绝缘薄膜的膜厚,在有半导体芯片的地方比无半导体芯片的地方更薄。
20.一种半导体器件的制造方法,其特征在于包括:
使半导体芯片的底面的整个面粘接到金属板上,把第1绝缘薄膜粘接到上述半导体芯片的上表面整个面和上述金属板上;
形成贯通上述第1绝缘薄膜使半导体芯片的上述上表面露出来的孔;
向上述孔内埋入第1导体;
在上述第1绝缘薄膜的表面之上形成电连到上述第1导体上的第1布线。
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TW200421960A (en) | 2004-10-16 |
JP3740469B2 (ja) | 2006-02-01 |
US20040183192A1 (en) | 2004-09-23 |
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