CN105023920A - 包括多个半导体芯片和多个载体的器件 - Google Patents

包括多个半导体芯片和多个载体的器件 Download PDF

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Publication number
CN105023920A
CN105023920A CN201510179747.2A CN201510179747A CN105023920A CN 105023920 A CN105023920 A CN 105023920A CN 201510179747 A CN201510179747 A CN 201510179747A CN 105023920 A CN105023920 A CN 105023920A
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semiconductor chip
support
carrier
disposed
electrical contact
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CN201510179747.2A
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CN105023920B (zh
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O.赫伯伦
M-A.库察克
R.奥特伦巴
K.席斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及包括多个半导体芯片和多个载体的器件。一种器件包括被布置在第一载体之上且包括第一电接触的第一半导体芯片。该器件还包括被布置在第二载体之上且包括被布置在所述第二半导体芯片面对所述第二载体的表面之上的第二电接触的第二半导体芯片。所述第二载体电耦合到所述第一电接触和所述第二电接触。

Description

包括多个半导体芯片和多个载体的器件
技术领域
本公开涉及包括多个半导体芯片和多个载体的器件。此外，本公开涉及用于制造此类器件的方法。
背景技术
器件可以包括可在该器件操作期间进行交互的多个半导体芯片。器件的设计和所选择的半导体芯片布置可以影响器件的性能。必须不断改进半导体器件和用于制造半导体器件的方法。特别地，可能期望的是改进半导体器件的热性能和电性能。
发明内容
根据实施例，器件包括布置在第一载体之上的第一半导体芯片和第一电接触。该器件还包括布置在第二载体之上的第二半导体芯片。第二半导体芯片包括布置在第二半导体芯片的表面之上的第二电接触。第二电接触面向第二载体。第二载体被电耦合到第一电接触和第二电接触。
根据实施例，器件包括布置在第一载体之上的第一半导体芯片和至少部分地密封第一半导体芯片的密封材料。层压材料被布置在该密封材料之上。第二载体至少部分地嵌入该层压材料中。第二半导体芯片被布置在第二载体和该层压材料之上。
根据实施例，器件包括驱动器电路和第一半导体芯片。该驱动器电路和第一半导体芯片被单片集成在第一半导体材料中。该器件还包括集成在第二半导体材料中的第二半导体芯片，其中第二半导体材料包括复合半导体。
附图说明
附图被包括用来提供对于各方面的进一步理解，并且被合并在本说明书中并构成本说明书的一部分。这些图图示出各方面并且连同描述一起用来解释各方面的原理。其他方面和各方面的许多所意图的优点将被容易地认识到，因为通过参考以下详细描述它们变得更好理解。这些附图的元件不必相对于彼此合乎比例。相似的附图标记可以指示对应的类似部件。
图1示意性地图示出根据本公开的器件的横截面视图。
图2示意性地图示出根据本公开的器件的横截面视图。
图3A到3G示意性地图示出用于制造根据本公开的器件的方法的横截面视图。
图4示意性地图示出根据本公开的器件的横截面视图。
图5示意性地图示出根据本公开的器件的横截面视图。
图6图示出直接驱动电路的示意图。
图7图示出半桥电路的示意图。
图8示意性地图示出根据本公开的器件的横截面视图。
图9示意性地图示出根据本公开的器件的横截面视图。
具体实施方式
在以下详细描述中，进行对于形成其一部分的附图的参考，并且在所述附图中通过图示的方式示出了可以在其中实践本公开的特定方面。在此方面，可以参考正描述的图的取向来使用诸如“顶”、“底”、“前面”、“后面”等等之类的方向性术语。因为所描述的器件的组件可以位于数个不同取向上，所以可以出于图示的目的使用方向性术语而绝非进行限制。在不偏离本公开的范围的情况下可以利用其他方面并且可以做出结构或逻辑改变。因此，不应在限制意义上考虑以下详细描述，并且本公开的范围由所附权利要求限定。
如本说明书中采用的，术语“被连接”、“被耦合”、“被电连接”和/或“被电耦合”并不打算必然意指元件必须被直接连接或耦合在一起。可以在“被连接”、“被耦合”、“被电连接”和/或“被电耦合”的元件之间提供中间元件。
进一步地，本文中可以使用关于例如形成或设置在对象表面“之上”的材料层而使用的措词“之上”来意指可以将该材料层“直接”设置（例如形成、沉积，等等）在暗指的表面上，例如与其直接接触。本文中还可以使用关于例如形成或设置在表面“之上”的材料层而使用的措词“之上”来意指可以将该材料层“间接”设置（例如形成、沉积，等等）在暗指的表面上，例如将一个或多个附加层布置在暗指的表面和该材料层之间。
本文中描述了器件和用于制造器件的方法。结合所描述的器件做出的评述也适用于对应的方法，并且反之亦然。例如，如果描述了器件的特定组件，则用于制造该器件的对应方法可以包括以合适的方式提供该组件的动作，即使并未在图中明确地描述或图示此类动作。此外，本文中描述的各种示例性方面的特征可以彼此组合，除非另有具体说明。
本文中描述的器件可以包括一个或多个半导体芯片并且因此也可以被称为半导体器件。半导体芯片可以具有不同类型并且可以由不同技术来制造。例如，半导体芯片可以包括集成的电、光电或机电电路、无源装置（passives），等等。可以将集成电路设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储器电路、集成无源装置、微机电系统，等等。半导体芯片不需要由特定的半导体材料制造并且可以包含并非半导体的无机和/或有机材料，诸如例如绝缘体、塑料或金属。在一个示例中，半导体芯片可以由基本半导体材料制成或者可以包括基本半导体材料，所述基本半导体材料例如Si等。在另一示例中，半导体芯片可以由复合半导体材料制成或者可以包括复合半导体材料，所述复合半导体材料例如SiC、SiGe、GaAs等。
半导体芯片可以包括一个或多个功率半导体。例如，可以将功率半导体芯片配置为二极管、功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结型栅场效应晶体管）、超级结器件、功率双极晶体管，等等。本文中描述的器件还可以包括被配置成控制和/或驱动该功率半导体芯片的集成电路的半导体芯片或集成电路。
半导体芯片可以具有垂直结构，即可以制作半导体芯片使得电流可以基本上在垂直于半导体芯片主面的方向上流动。具有垂直结构的半导体芯片在其两个主面之上（即在其顶侧和底侧之上）可以具有电极。特别地，功率半导体芯片可以具有垂直结构并且可以具有被布置在两个主面之上的负载电极。可以将功率MOSFET的源电极和栅电极布置在一个面之上，同时可以将该功率MOSFET的漏电极布置在另一面之上。垂直功率半导体芯片的示例是PMOS（P沟道金属氧化物半导体）、NMOS（N沟道金属氧化物半导体）或上面指定的示例性功率半导体中的一个。
半导体芯片可以具有横向结构，即可以制作半导体芯片使得电流可以基本上在平行于该半导体芯片的主面的方向上流动。具有横向结构的半导体芯片可以具有被布置在其主面之一之上的电极。在一个示例中，具有横向结构的半导体芯片可以包括集成电路，诸如例如逻辑芯片。在另外的示例中，功率半导体芯片可以具有横向结构，其中可以将负载电极布置在该芯片的一个主面之上。例如，可以将功率MOSFET的源电极、栅电极和漏电极布置在该功率MOSFET的一个主面之上。横向功率半导体芯片的另外的示例可以是HEMT（高电子迁移率晶体管），该HEMT可以由上面提到的复合半导体材料中的一个制作。
半导体芯片可以是封装的或未封装的。在此方面，如本说明书中使用的术语“半导体器件”和“半导体封装”可以互换地使用。特别地，半导体封装可以是包括密封材料的半导体器件，该密封材料可以至少部分地密封该半导体器件的一个或多个组件。
半导体芯片可以包括变化数目的电接触。取决于所考虑的器件类型，可以将电接触布置在该半导体芯片的一个或多个表面之上的变化的几何结构中。在一个示例中，可以将电接触布置在该半导体芯片的前侧和背侧之上。此类半导体芯片可以例如对应于可以包括布置在该半导体芯片的一侧上的漏极接触以及布置在该半导体芯片的相对侧之上的源极接触和栅极接触的功率半导体芯片。在另外的示例中，可以将电接触排他地布置在半导体芯片的前侧之上。例如，此类半导体芯片可以被称为横向芯片并且可以例如对应于分立半导体芯片。例如，可以将电接触直接设置在半导体芯片的电子结构之上，使得当在电接触和该电子结构之间提供电连接时可以不需要另外的再分布层。替换地，可以经由一个或多个附加再分布层将电接触连接到该电子结构。
电接触可以具有接触焊盘（接触元件或接触端子或接触电极）的形式。接触焊盘可以包括一个或多个层，这些层中的每一个可以包括金属和金属合金中的至少一个。例如，可以将金属焊盘施加于半导体芯片的半导体材料。这些层可以被制造为具有任何期望的几何形状和任何期望的材料成分。可以使用任何期望的金属或金属合金（例如铝、钛、金、银、铜、钯、铂、镍、铬、钒、钨、钼，等等）作为材料。这些层不需要是同质的或者由仅仅一种材料制造，即包括在这些层中的材料的各种成分和浓度可以是可能的。可以将任何适当的技术用于制造接触焊盘或形成接触焊盘的层。例如，可以使用无电镀工艺。
本文中描述的器件可以包括可以在其之上布置一个或多个半导体芯片的载体。这些器件不限于仅包括一个单个载体，而是也可以包括多个载体。一般地，载体可以由金属、合金、电介质、塑料、陶瓷或其组合制造。载体可以具有同质结构，但是也可以提供像具有电再分布功能的传导路径的内部结构。此外，载体的所占面积（footprint）可以取决于要被布置在该载体之上的半导体芯片的数目和所占面积。即，载体可以特别地包括被配置成承载半导体芯片的安装面积。载体的示例可以是管芯焊盘、包括管芯焊盘的引线框架或者包括一个或多个再分布层的陶瓷衬底。
在一个示例中，载体可以包括可以具有任何形状、任何大小和任何材料的引线框架。可以构造引线框架使得可以形成管芯焊盘（或芯片岛）和引线。在制作器件期间，管芯焊盘和引线可以彼此进行连接。管芯焊盘和引线也可以由一个片制成。在具有在制作过程中将管芯焊盘和引线中的一些进行分离的目的的情况下，管芯焊盘和引线可以通过连接装置在彼此当中进行连接。此处，可以通过机械锯切、激光束、切削、冲压、碾磨、蚀刻和任何其他适当技术中的至少一个来执行将管芯焊盘和引线进行分离。特别地，引线框架可以是导电的。例如，引线框架可以完全由金属和/或金属合金，特别是铜、铜合金、镍、铁镍、铝、铝合金、钢、不锈钢和其他适当材料中的至少一个制作。引线框架材料可以包括痕量的铁、硫、氮化铁，等等。引线框架可以镀有导电材料，例如铜、银、钯、金、镍、铁镍和镍磷中的至少一个。在这种情况下，引线框架可以被称为“被预镀的引线框架”。即使引线框架可以是导电的，引线框架的管芯焊盘的选择也可以是彼此电绝缘的。
引线框架的形状、大小和/或材料可以取决于可以被布置在引线框架之上的一个或多个半导体芯片。在一个示例中，可以将诸如横向GaN芯片之类的复合半导体芯片布置在引线框架之上。在这种情况下，引线框架可以由铝和/或铝合金制成或者可以包括铝和/或铝合金。此类引线框架可以具有从约1毫米到约5毫米，更特别地从约1毫米到约2毫米的厚度。例如，可以将引线框架连接到可以由类似材料制成的热沉。在另外的示例中，可以将低电压MOS布置在引线框架之上。在这种情况下，引线框架可以由铜和/或铜合金制成或者可以包括铜和/或铜合金，并且可以进一步包括痕量的铁和/或硫。此类引线框架可以具有从约0.1毫米到约0.5毫米，更特别地从约0.2毫米到约0.3毫米的厚度。
载体（或引线框架）可以至少部分地嵌入层压材料中。层压材料的厚度可以等于或大于嵌入该层压材料中的引线框架的厚度。层压材料的材料可以类似于如下面指定的密封材料，使得在这一点上做出的评述也可以适用于层压材料。可以将包括一个或多个引线框架的层压材料附着到器件的另外的组件，例如附着到密封材料。可以通过应用层压、胶粘、烧结等等中的至少一个来将层压材料附着到该另外的组件。在附着层压材料之后，其可以在被包括在层压材料中的载体与已在其之上布置该层压材料的组件之间提供机械连接。
本文中描述的器件可以包括一个或多个导电元件，该一个或多个导电元件被配置成在这些器件的组件之间提供电耦合。例如，可以将导电元件配置成电连接第一半导体芯片和第二半导体芯片或者在半导体芯片与可以被布置在器件内部或外部的另外的组件之间提供电连接。
导电元件可以包括一个或多个接触夹。接触夹可以由类似于引线框架的材料的材料制成或者可以包括类似于引线框架的材料的材料，使得上面结合引线框架做出的评述也可以适用于接触夹。接触夹的形状不一定限于特定大小或特定几何形状。可以通过冲压、冲孔、挤压、切削、锯切、碾磨和任何其他适当技术来制作接触夹。可以通过任何适当技术来建立导电元件与半导体芯片的接触焊盘之间的接触。在一个示例中，可以例如通过采用扩散焊接工艺来将导电元件焊接到其他组件。
导电元件可以包括一个或多个导线，特别是接合导线或键合导线。导线可以包括金属和/或金属合金，特别是金、铝、铜或其合金中的一个或多个。此外，导线可以或可以不包括涂层。导线可以具有基本上圆形的横截面，使得术语导线的“厚度”可以指的是接合导线的直径。然而，所理解的是，导线也可以具有不同形式的横截面。一般地，导线可以具有从约15μm（微米）到约1000μm（微米）的厚度，并且更特别地约50μm（微米）到约500μm（微米）的厚度。
在第一更特别的示例中，导线可以具有小于75μm（微米）的厚度，例如从约50μm（微米）到约75μm（微米）的厚度。此类导线可以特别地包括铝或者由铝制成。导线可以包括另外的材料。例如高达1%的硅。例如，此类导线可以在接触元件与功率半导体芯片的栅电极之间和/或在两个不同的功率半导体芯片的栅电极之间提供电连接。在第二更特别的示例中，导线可以具有从约125μm（微米）到约500μm（微米）的厚度。可以特别地采用此类导线来在接触元件与功率半导体芯片的源电极之间提供电连接。
本文中描述的器件可以包括一个或多个再分布层。例如，可以将再分布层布置在包括接触焊盘的半导体芯片的主表面之上。再分布层可以包括一个或多个金属层，该一个或多个金属层可以具有导体线或导体平面的形状并且可以电耦合到器件的半导体芯片的接触焊盘。可以将这些金属层用作提供与来自器件外部的半导体芯片的电接触和/或提供与被包括在器件中的其他半导体芯片和/或组件的电接触的接线层。金属层可以将这些半导体芯片的接触焊盘电耦合到外面的接触焊盘。可以将金属层制造为具有任何期望的几何形状和任何期望的材料成分。例如，金属层可以包括铝、镍、钯、银、锡、金、铜、对应的金属合金等等及其组合中的至少一个。金属层可以包括由这些材料制成的一个或多个单个金属层。替换地或附加地，金属层可以包括由例如铜/镍/金的材料制成的一个或多个多层。可以将金属层布置在电绝缘层之上或之下或之间。例如，可以通过可以由类似材料制成的一个或多个通孔连接（或直通连接）来建立在布置于不同层次上的金属层之间的连接。
本文中描述的器件可以包括密封材料，该密封材料可以至少部分地覆盖器件的一个或多个组件。该密封材料可以是电绝缘的，并且可以形成密封体。密封材料可以包括环氧基树脂、玻璃纤维填充的环氧基树脂、玻璃纤维填充的聚合物、酰亚氨、填充或非填充的热塑聚合物材料、填充或非填充的硬塑（duroplastic）聚合物材料、填充或非填充的共混聚合物、热固材料、模塑料、圆顶（glob-top）材料、层压材料，等等。可以使用各种技术（例如压缩模塑、喷射模塑、粉末模塑、液体模塑、层压，等等中的至少一个）来利用密封材料密封器件的组件。
本文中描述的器件可以包括可以以半导体材料实现的一个或多个驱动器电路（或驱动器）。驱动器电路可以包括一个或多个电气电路或电气组件，该一个或多个电气电路或电气组件可以被配置成驱动（或控制）一个或多个组件或电路，例如也可以被包括在器件中的高功率晶体管。被驱动的组件可以是电压驱动的或电流驱动的。例如，功率MOSFET、IGBT等等可以是电压驱动的开关，因为其绝缘栅可以特别地起到像电容的作用。相反，诸如三端双向可控硅开关（用于交变电流的三极管）、半导体闸流管、双极晶体管、PN二极管等等之类的开关可以是电流驱动的。在一个示例中，驱动包括栅电极的组件可以包括例如以接通和关断开关波形的形式向栅电极施加不同的电压。在另外的示例中，可以使用驱动器电路来驱动直接驱动电路。
本文中描述的器件可以包括可以以半导体材料实现的一个或多个控制电路（或控制器）。控制电路可以包括一个或多个电气电路或电气组件，该一个或多个电气电路或电气组件可以被配置成控制也可以被包括在器件中的一个或多个组件或电路。可以将控制电路配置成对驱动器件的各组件的一个或多个驱动器进行控制。在一个示例中，控制电路可以同时控制多个直接驱动电路的驱动器。例如，因此可以通过控制器来控制包括两个直接驱动电路的半桥电路。控制器可以例如包括微控制器。
图1示意性地图示出根据本公开的器件100的横截面视图。在图1的示例中，以一般的方式图示出器件100，并且其可以包括为简单起见而未图示的另外的组件。例如，器件100可以还包括根据本公开的其他器件的一个或多个组件。下文描述类似于器件100的更多详细器件。
器件100可以包括可以被布置在第一载体12之上的第一半导体芯片11。第一半导体芯片11可以包括第一电接触13。在图1的示例中，可以将第一电接触13布置在第一半导体芯片11可以背对第一载体12的表面之上。在另外的示例中，也可以将第一电接触13布置在不同的位置，例如在第一半导体芯片11面对第一载体12的表面之上。器件100可以还包括可以被布置在第二载体15之上的第二半导体芯片14。第二半导体芯片14可以包括可以被布置在第二半导体芯片14面对第二载体15的表面之上的第二电接触16。可以将第二载体15电耦合到第一电接触13和第二电接触16。在第二载体15与电接触13和16之间的电耦合可以以各种方式来建立，并且不限于一个特定示例。在图1中，因此由虚线定性地指示第二载体15与第一电接触13之间的电耦合，但是为了简单起见，未图示出特定的实现方式。下面提供组件之间合适的电耦合的示例。
图2示意性地图示出根据本公开的器件200的横截面视图。器件200可以包括可以被布置在第一载体12之上的第一半导体芯片11。器件200可以还包括密封材料18，该密封材料18可以至少部分地密封第一半导体芯片11。此外，器件200可以包括可以被布置在密封材料18之上的的层压材料19。可以将第二载体15至少部分地嵌入层压材料19中。器件200也可以包括第二半导体芯片14，该第二半导体芯片14可以被布置在第二载体15之上和层压材料19之上。下面描述类似于器件200的更多详细器件。
图3A到3G示意性地图示出用于制造器件300的方法，在图4G中示出该器件300的横截面。可以将器件300视为器件100和200的实现方式，使得可以将下面描述的器件300的细节同样地应用于器件100和200。图3A到3G图示出一个器件300的制造。然而，可以同时制造更大数目的类似器件。可以对于图中所示多个数目的类似布置执行如图3A到3G中所示的每个动作。该要处理的多个布置可以例如以并排方式进行放置，例如在图3A到3G中所示布置的向左边和向右边。
在图3A中，可以提供第一载体12。例如，第一载体12可以对应于引线框架，该引线框架可以包括一个或多个管芯焊盘和/或可以连接到或可以不连接到一个或多个管芯焊盘的一个或多个引线。第一载体12可以由铝和铝合金中的至少一个制成或者可以包括铝和铝合金中的至少一个。进一步地，第一载体12可以具有从约1毫米到约5毫米、更特别地从约1毫米到约2毫米的厚度t1。第一载体12的上表面20可以具有可以是足够大的表面面积，使得可以将例如GaN半导体芯片的复合半导体芯片布置在上表面20之上。GaN半导体芯片可以具有从约1mm2到约4mm2、更特别地从约2mm2到约3mm2的表面面积。当要制造多个器件时，可以以并排方式布置对应数目的多个类似载体（未图示出）。于是另外的载体可以变成要制造的附加器件的一部分。
在图3B中，可以将第一半导体芯片11布置在第一载体12的上表面20之上。可以通过使用任何适当技术和材料来将第一半导体芯片11附着到第一载体12，例如借助于扩散焊料、胶水、粘合剂等等。取决于要制造的器件300的期望功能，第一半导体芯片11和第一载体12可以彼此电耦合或者可以彼此电绝缘。在图3B的示例中，第一半导体芯片11可以对应于横向复合半导体芯片，例如GaN HEMT。第一半导体芯片11可以包括电接触，这些电接触可以被布置在第一半导体芯片11可以背对第一载体12的表面之上。在图3B的示例中，这些电接触可以包括源电极21、栅电极22和漏电极23。
在图3C中，第一载体12和第一半导体芯片11可以由密封材料18至少部分地密封。例如，可以将第一载体12和第一半导体芯片11放置到模具（molding tool）中，其中第一载体12的下表面和包括电接触的第一半导体芯片11的上表面可以由该模具至少部分地覆盖。然后可以将密封材料18注射到模具中，从而形成如图3C中图示的密封体18。此处，第一载体12的下表面和第一半导体芯片11的上表面可以保持从密封材料18暴露。可以将第一载体12的下表面和密封材料18的下表面布置在公共平面中。类似地，也可以将第一半导体芯片11的上表面和密封材料18的上表面布置在公共平面中。
在图3D中，可以提供层压材料19。层压材料19可以包括第二载体15，该第二载体15可以至少部分地嵌入层压材料19中。第二载体15可以对应于引线框，该引线框可以包括一个或多个管芯焊盘和/或可以连接到或可以不连接到该一个或多个管芯焊盘的一个或多个引线。第二载体15的至少一部分可以是导电的。在一个示例中，第二载体15可以由铜和/或铜合金制成或者可以包括铜和/或铜合金，并且可以还包括痕量的铁和/或硫。第二载体15可以具有从约0.1毫米到约0.5毫米，更特别地从约0.2毫米到约0.3毫米的厚度t2。取决于要制造的器件300的功能和被包括在器件300中的半导体芯片的数目，层压材料19可以包括为简单起见未图示出的另外的载体。
可以将第二半导体芯片14布置在第二载体15之上。可以通过任何适当技术和材料将第二半导体芯片14附着到第二载体15，例如借助于扩散焊料、胶水、粘合剂等等。例如，第二半导体芯片14可以对应于垂直功率半导体芯片，该垂直功率半导体芯片可以包括布置在其主表面之上的电接触。例如，第二半导体芯片14可以是低电压NMOS芯片。在图3D的示例中，这些电接触可以包括可以被布置在第二半导体芯片14面对第二载体15的主表面之上的漏电极24。因此，可以建立在漏电极24与第二载体15之间的电耦合。此外，这些电接触可以包括可以被布置在第二半导体芯片14背对第二载体15的主表面之上的栅电极25和源电极26。
在图3E中，可以将包括第二载体15的层压材料19布置在密封材料18之上。特别地，可以布置层压材料19使得可以将第二半导体芯片14至少部分地横向设置在第一半导体芯片11的轮廓外部。此外，由于层压材料19的定位，可以将第一半导体芯片11的主表面和第二半导体芯片14的主表面布置在不同层次上。层压材料19可以在密封材料18与第二载体15之间和/或在密封材料18与层压材料19之间提供机械连接。在一个示例中，可以通过将层压材料19放置到密封材料18上并且使该布置暴露于升高的温度使得层压材料19和密封材料18可以至少部分地变得凝聚来提供机械连接。为此目的，可以将该布置例如放置在烤箱内，该烤箱可以被配置成提供凝聚要机械连接的材料所需的温度。在另外的示例中，可以通过应用层压、胶合等等中的至少一个来提供机械连接。
在图3F中，可以在第一半导体芯片11之上和在第二半导体芯片14之上形成一个或多个再分布层。这些再分布层可以包括一个或多个导电层以及可以被布置在这些导电层之间的一个或多个电绝缘层。可以通过导电通孔连接（或直通连接）将堆叠的导电层彼此电耦合。特别地，可以基于平面技术来形成再分布层的各个层，其中可以以平面层的形式来沉积这些层。
可以通过使用溅射、无电沉积、蒸发或任何其他适当技术来沉积被包括在再分布层中的导电层。导电层可以包括铝、镍、钯、钛、钛钨、银、锡、金、钼、钒或铜以及金属合金中的至少一个或者可以由铝、镍、钯、钛、钛钨、银、锡、金、钼、钒或铜以及金属合金中的至少一个制成。例如，可以通过应用蚀刻技术来构造这些导电层。此处，可以适当地构造抗蚀刻层，其中可以通过蚀刻步骤来移除未被相应的抗蚀刻层覆盖的导电层部分，使得可以提供结构化的导电层。
可以从气相或从溶液来沉积被包括在再分布层中的电绝缘层或者可以将它们层压在相应的表面之上。附加地或替换地，可以将薄膜技术或标准PCB工业工艺流程用于电绝缘层的应用。这些电绝缘层可以由聚合物制作，例如聚降冰片烯、聚对二甲苯、光阻材料、酰亚胺、环氧基树脂、热固塑料、硅酮、氮化硅、二氧化硅或无机物、诸如硅酮-碳复合物之类的类陶瓷材料。电绝缘层的厚度可以高达10μm（微米）或甚至更高。可以构造电绝缘层并且其可以在要提供电直通连接的位置开口。通过示例方式，可以通过使用光刻方法、蚀刻方法、激光钻孔等等中的至少一个来提供电绝缘层的构造和电绝缘层中的开口。
第一再分布层可以包括一个或多个导电连接，它们中的每一个可以包括一个或多个导电层和一个或多个导电通孔连接。可以将第一再分布层的导电连接特别地耦合到第一半导体芯片11的电接触。在图3F的示例中，以简化方式图示了这些导电连接。即，并非所有导电层和可被包括在相应导电连接中的通孔连接可以被明确地示出。
导电连接27可以穿过层压材料19和再分布层的电绝缘层28从漏电极23延伸到所图示布置的上表面29。因此可以有可能经由导电连接27而电接触漏电极23。另外的导电连接30可以穿过层压材料19和再分布层的电绝缘层28从栅电极22延伸到所图示布置的上表面29。因此可以经由导电连接30而电接触栅电极22。另外的导电连接31可以在第一半导体芯片11的源电极21与第二载体15之间提供电耦合。此外，导电连接31可以在源电极21与第一载体12之间提供电耦合，使得可以将第一载体12设定到一电势。在图3F的示例中，导电连接31可以包括通孔连接31A，该通孔连接31A可以电耦合到第一载体12和第二载体15。
第二再分布层可以包括一个或多个导电连接，它们中的每一个可以包括一个或多个导电层和一个或多个导电通孔连接。可以将第二再分布层的导电连接特别地耦合到第二半导体芯片14的电接触。在图3F的示例中，以简化方式图示了这些导电连接，即并非所有可以被包括在相应导电连接中的传导层和通孔连接可以被明确示出。
导电连接32可以穿过再分布层的电绝缘层28从第二半导体芯片14的栅电极25延伸到该布置的上表面29。因此，可以经由导电连接32而电接触栅电极25。另外的导电连接33可以穿过再分布层的电绝缘层28从源电极26延伸到再分布层的上表面29。因此可以经由导电体连接33而电接触源电极26。可以将上面描述的导电连接31视作第二再分布层的另外的部分。导电连接31可以提供到第二载体15的电耦合，该第二载体15可以电耦合到第二半导体芯片14的漏电极24。因此有可能经由导电连接31而电接触漏电极24。第一半导体芯片11的源电极21可以经由第二载体15和导电连接31电耦合到第二半导体芯片14的漏电极24。
在一个示例中，当稍后可以将该布置布置在外部组件之上（例如在PCB之上）时，这些导电连接在该布置的上表面29上暴露的表面可以充当接触焊盘。在另外的示例中，可以将附加的接触元件布置在这些导电连接（例如焊料球、焊料仓（depot）等等）的暴露表面之上。
在图3G中，可以将电介质层34布置在该布置的下表面35之上。电介质层34可以被配置成将第一载体12与其他组件电绝缘。电介质层34可以包括类似于密封材料18的材料或者可以由类似于密封材料18的材料制成。电介质层34的材料和密封材料18可以是相同的或者可以不相同。可以将任何适当的技术用于将电介质层34沉积在下表面35之上，例如层压、刮擦（squeegee）、印刷、分配、旋涂、涂敷胶粘箔等等中的至少一个。
结合图3A和3G描述的方法可以包括为简单起见而未明确图示的另外的动作。例如，可以对于以并排方式进行布置的多个类似布置已经执行了图3A到3G的动作。在对多个布置执行所描述的动作之后，可以通过分离在图3G中由虚线所指示的位置处的各个所制作的器件来使这些布置形成单片。可以将任何合适的技术用于分离所制造的器件，例如锯切、激光分割、湿蚀刻、等离子蚀刻等等中的至少一个。单片化器件300可以具有从约5毫米到约13毫米，更特别地从约8毫米到约10毫米的长度。在器件300的操作期间，漏电流可能在该器件300可能已经被分离所在的侧表面处发生。由于第一载体12的厚度t1的原因，可以增大用于此类漏电流的泄漏路径。
布置在半导体芯片11和14之上的再分布层可以提供扇出结构，在该扇出结构中器件300的上表面29之上的电接触可以至少部分地位于半导体芯片11、14中的相应一个的轮廓外部。例如，再分布层的导电层可以延伸超过半导体芯片的轮廓多于1毫米或多于2毫米或多于3毫米。例如，单片化器件300在顶部俯视图中的形状可以是方形或矩形。可以由为简单起见而未图示的另外的动作来处理被分离的器件300。被分离的器件300可以电耦合到其他电子组件，例如其可以被安装于PCB上。
图3G的器件300可以被配置成作为直接驱动电路操作。在图6中提供直接驱动电路600的示例性示意图。例如，此类直接驱动电路可以包括例如GaN HEMT的复合半导体芯片和例如NMOS的低电压功率MOS。当将图3G的器件300用作直接驱动电路时，第一半导体芯片11可以包括复合半导体芯片，而第二半导体芯片14可以包括低电压功率MOS。在另外的示例中，可以将类似于图3G的器件300的器件配置成作为全桥电路、半桥电路、共源共栅（cascode）电路等等操作。
图4示意性地图示出根据本公开的器件400的横截面视图。器件400可以类似于图3G的器件300。结合图3A到3G做出的评述因此也可以适用于图4。和图3的器件300对比，器件400在第一载体12与再分布层的导电层之间可以不一定包括电连接。在图4中，缺失器件300的电耦合第一载体12和导电层31的直通连接31A。因此，器件400的第一载体12可以不一定具有电气功能。然而，第一载体12可以支持在远离第一半导体芯片11的方向上热耗散，并且因此可以具有热功能。由于第一载体12的厚度t1和第二载体15的厚度t2可以不同，所以经由载体12、15在远离半导体芯片11、14的垂直方向上的热传输也可以不同。特别地，经由第一载体12在垂直方向上的第一热传输可以大于经由第二载体15在垂直方向上的第二热传输。例如，第一热传输与第二热传输之间的比可以大于二的值、更特别地大于五的值，并且甚至更特别地大于十的值。
图5示意性地图示出根据本公开的器件500的横截面视图。器件500可以类似于上面讨论的器件300和400中的一个。结合先前的图做出的评述因此也可以适用于图5。和图3G的器件300对比，第一半导体芯片11可以不一定对应于横向半导体芯片，而对应于可以包括在面对第一载体12的下表面和背对第一载体12的上表面上的电接触的垂直半导体芯片。在图5中，可以经由第一载体12接触第一半导体芯片11的下表面上的电接触。图3G和5的第一半导体芯片11可以具有类似的电子和/或热功能。以类似的方式，可以由垂直第一半导体芯片取代图4的器件400中包括的横向第一半导体芯片11。
图6图示出直接驱动电路600的示意图。例如，可以以图3G、4和5的器件中的一个的形式来实现直接驱动电路600。直接驱动电路600可以包括具有与常断半导体组件的电流路径串联耦合的电流路径的常通半导体组件。对于用作开关的半导体组件，可以有可能定义两个不同的状态：传导（导通状态）和隔断（断开状态）。当将零伏电压施加到组件的控制端子，例如其栅电极时，常通组件可以是传导的。因此，常断组件可以仅仅当将有限电压施加到该组件的控制端子时才是传导的。例如，由复合半导体形成的高性能器件可以对应于常通器件。
在图6的示例中，直接驱动电路600可以包括常通JFET 36、常断MOSFET 37、第一驱动器38和第二驱动器40。JFET 36和MOSFET 37的漏极、源极和栅极被分别标记为D、S和G。第一驱动器38可以具有输入39并且可以耦合到JFET 36的栅极。例如，第一驱动器38可以被配置成将位于从约0V到约5V范围中的电压施加到JFET 36的栅极。第二驱动器40可以具有输入41并且可以耦合到MOSFET 37的栅极。例如，第二驱动器40可以被配置成将位于从约0V到约5V范围中的电压施加到MOSFET 37的栅极。MOSFET 37的源极可以位于约0V（即，在接地处）的电势，而JFET 36的漏极可以位于约600V的电势。JFET 36的源极与MOSFET 37的漏极之间的电感LSD可以例如小于1nH。可以密封直接驱动电路600的至少一部分的封装42由虚线矩形指示。
JFET 36可以具有与MOSFET 37的电流路径串联耦合的电流路径。特别地，JFET 36可以包括GaN HEMT，并且MOSFET 37可以包括NMOS。返回参考图3G的器件300，JFET 36可以对应于第一半导体芯片11，而MOSFET 37可以对应于第二半导体芯片14。MOSFET 37的栅极可以耦合到第二驱动器40以在过渡操作状况期间提供JFET 36和MOSFET 37的常断串联布置。例如，在不存在偏置电压的情况下启动时，第二驱动器40可以被设计成向MOSFET 37的栅极呈现零伏。相应地，MOSFET 37可以被布置成在此类启动或其他过渡操作状况期间在其源极和漏极之间呈现开路电路。一旦已由该电路建立偏置电压并且开关逻辑处于正常操作状况，第二驱动器40就可以被配置成响应于第二驱动器40的输入41处的信号使能在MOSFET 37中的传导。包括可以是低电压器件、其电流路径与JFET 36的电流路径串联耦合的MOSFET 37由于可以使用的MOSFET 37的低电压额定值的原因可以向电路添加相对小的串联电阻。MOSFET 37的电阻可以大致作为其额定闭塞电压的2.5次幂的倒数而变化。因此，低电压额定MOSFET 37可以一般展示低的导通状态电阻。
第一驱动器38可以向JFET 36的栅极提供信号以便例如以小的损耗在高开关频率处开关JFET 36。相应地，第一驱动器38可以被配置成向JFET 36的栅极呈现负电压以便在电路的正常操作状况期间禁用其中的传导。由于在JFET 36的高频率开关期间MOSFET 37可以被维持在完全传导的状态中，所以可以保留JFET 36的低损耗、高频率开关特性。第一驱动器38可以被配置成利用相对于MOSFET 37的源极，即相对于局部电路地（见MOSFET 37的源极）的驱动电压来驱动JFET 36的栅极。相应地，例如在当MOSFET 37的栅极电压可以相对于其源极为零时的启动处，当MOSFET 37被禁用传导时，可以由直接驱动电路600保持JFET 36的高电压闭塞能力。
总结在启动、停机或故障状况期间直接驱动电路600的操作，两个驱动器输出都可以相对于局部地在零伏处。在MOSFET 37的漏极处发展的小的正电压可以禁用JFET 36的传导性，使得JFET 36能够成为闭塞直接驱动电路的传导性的主电路元件。在正常高频率开关操作期间，可以通过施加到MOSFET 37的栅极的正电压使MOSFET 37能够传导。可以通过施加到JFET 36的栅极的交变的零和负栅极驱动电压来产生直接驱动电路的高频率开关动作。
独立控制JFET 36的栅极和MOSFET 37的栅极可以维持耗尽型JFET的低损耗、高频率开关特性，同时通过穿过增强型硅MOSFET的串联电流路径保证在过渡操作状况期间的安全操作。对MOSFET 37的栅极的独立控制可以用来在故障状况期间禁用直接驱动电路600的传导性。
图7图示出半桥电路700的示意图。半桥电路700可以被布置在节点N1和N2之间。半桥电路700可以包括串联连接的开关S1和S2。可以向节点N1和N2施加恒定的电势。例如，可以将诸如10、12、18、50、110、230、500或1000V之类的高电势施加到节点N1，并且可以将例如0V的低电势施加到节点N2。可以在从1kHz到100MHz的范围中的频率处使开关S1和S2进行开关，但是开关频率也可以在此范围之外。这意味着在半桥电路的操作期间可以向布置在开关S1和S2之间的节点N3施加变化的电势。节点N3的电势可以在低与高电势之间的范围中变化。
可以将半桥电路700例如实现在用于转换DC电压的电子电路（所谓DC-DC转换器）中。DC-DC转换器可以用来将电池或可充电电池所提供的DC输入电压转换成与下游连接的电子电路的需求匹配的DC输出电压。DC-DC转换器可以体现为降压转换器，其中输出电压小于输入电压，或者体现为升压转换器，其中输出电压大于输入电压。可以将数MHz或更高的频率施加到DC-DC转换器。此外，高达100A或甚至更高的电流可以流经DC-DC转换器。
由于图6的直接驱动电路600可以作为开关操作，所以可以基于两个直接驱动电路600来实现图7的半桥电路700。因此，可以使用两个器件实现半桥电路700，其中每个器件可以对应于结合图3G、4和5所描述的器件中的一个。因此根据本公开的器件可以被配置成作为半桥电路或者至少其一部分而操作。以类似的方式，根据本公开的器件可以被配置成作为任何其他桥电路或共源共栅电路的至少一部分而操作。
图8示意性地图示出根据本公开的器件800的横截面视图。器件800可以包括驱动器电路43和第一半导体芯片44，其中驱动器电路43和第一半导体芯片44可以被单片集成在第一半导体材料45中。器件800可以还包括第二半导体芯片46，该第二半导体芯片46可以被集成在第二半导体材料47中。第二半导体材料47可以包括复合半导体。结合图9描述类似于器件800的更详细的器件。
在一个示例中，器件800可以对应于直接驱动电路或者可以被包括在直接驱动电路中。返回参考图6的示例性直接驱动电路600，器件800的第一半导体芯片44可以对应于直接驱动电路600的MOSFET 37。此外，器件800的驱动器电路43可以对应于直接驱动电路600的第一驱动器38和第二驱动器40中的一个或两者。例如，这些组件可以被集成在基本半导体材料（诸如例如硅）中。器件800的第二半导体芯片46可以对应于直接驱动电路600的JFET 36。例如，该组件可以被集成在诸如GaN之类的复合半导体材料中。在另外的示例中，器件800可以至少部分地对应于半桥电路、全桥电路、共源共栅电路等等中的至少一个或者可以至少部分地被包括在半桥电路、全桥电路、共源共栅电路等等中的至少一个中。
图9示意性地图示出根据本公开的器件900的横截面视图。例如，器件900可以对应于QFN（四方扁平无引线）封装并且可以被配置成作为半桥电路而操作。在一个示例中，器件900可以至少部分地对应于图7的半桥电路700。结合图7做出的评述因此也可以适用于器件900。在图9的示例中，由线条指示器件900的各个组件之间的电连接。提供电连接的导电元件的类型可以取决于器件900的功能。例如，所指示的电连接中的每一个可以包括一个或多个导线、一个或多个接合导线、一个或多个接触夹等等中的至少一个。
器件900可以包括输入48，该输入48可以耦合到控制电路49使得控制电路49从器件900的外部可以是可访问的。控制电路49可以包括第一输出，该第一输出可以耦合到第一直接驱动电路600A。此外，控制电路49可以包括第二输出，该第二输出可以耦合到第二直接驱动电路600B。直接驱动电路600A和600B中的每一个可以类似于图6的直接驱动电路600。结合图6做出的评述因此也可以适用于图9的器件。在一个示例中，直接驱动电路600A和600B可以类似或相同。直接驱动电路600A和600B可以邻近于彼此设置，即直接驱动电路600A可以特别地被横向设置在直接驱动电路600B的轮廓外部，并且反之亦然。
直接驱动电路600A可以包括第一半导体芯片50A和第二半导体芯片51A。例如，第一半导体芯片50A可以包括类似于图6的器件600的一个或多个驱动器（未明确示出）和MOSFET（未明确示出）。第一半导体芯片50A可以被单片集成在半导体材料中，特别是基本半导体材料，诸如例如硅。在器件900的操作期间，第一半导体芯片50A的驱动器中的至少一个可以由控制电路49控制。第二半导体芯片51A可以包括类似于图6的器件600的JFET（未明确示出）。第二半导体芯片51A可以被耦合到第一半导体芯片50A，从而形成类似于图6的直接驱动电路。特别地，第二半导体芯片51A可以被集成在诸如例如GaN之类的复合半导体材料中。
器件900可以包括端子52，该端子52可以被耦合到第一直接驱动电路600A，特别是耦合到第二半导体芯片51A。因此，可以经由端子52从器件900的外部访问第一直接驱动电路600A。第一直接驱动电路600A可以耦合到第二直接驱动电路600B，从而形成半桥电路。器件900可以包括另外的端子53，该另外的端子53可以耦合到第二直接驱动电路600B，特别是耦合到第一半导体芯片50B。因此可以经由端子53从器件900的外部访问第二直接驱动电路600B。
虽然可能已经关于数个实现方式中的仅一个公开了本公开的特别的特征或方面，但是此类特征或方面可以与如可以被期望且对于任何给定或特别的应用有利的其他实现方式的一个或多个其他特征或方面进行组合。此外，在将术语“包括”、“具有”、“有”或其其他变体用在详细描述或权利要求中方面来说，此类术语意图以类似于术语“包含”的方式是开放性的。同样，术语“示例性”仅仅意指作为示例，而非最佳或最优。还应认识到的是，出于简单和容易理解的目的，本文中描绘的特征和/或元件被图示为具有相对于彼此的特别的尺寸，并且实际尺寸可以实质上不同于本文中所图示的尺寸。
尽管本文中已经图示和描述了特定方面，但是本领域普通技术人员将认识到的是，在不偏离本公开的范围的情况下，多种替换和/或等同的实现方式可以代替所示出和所描述的特定方面。本申请意图覆盖本文中讨论的特定方面的任何调适或变化。因此，所意图的是本公开仅由权利要求及其等同形式所限制。

Claims (20)

1. 一种器件，包括：
第一半导体芯片，被布置在第一载体之上并且包括第一电接触；以及
第二半导体芯片，被布置在第二载体之上并且包括被布置在所述第二半导体芯片的表面之上的第二电接触，该第二电接触面对所述第二载体，其中所述第二载体电耦合到所述第一电接触和所述第二电接触。
2. 权利要求1所述的器件，还包括：
至少部分地密封所述第一半导体芯片的密封材料，其中所述第二载体被布置在所述密封材料之上。
3. 权利要求2所述的器件，还包括：
被布置在所述密封材料之上的层压材料，其中所述第二载体至少部分地嵌入所述层压材料中。
4. 权利要求3所述的器件，其中所述层压材料在所述密封材料和所述第二载体之间提供机械连接。
5. 权利要求1所述的器件，其中所述第一半导体芯片被布置在所述第一载体的第一表面之上，并且所述第二半导体芯片被布置在所述第二载体的第二表面之上，其中所述第一表面和所述第二表面被布置在不同层次上。
6. 权利要求1所述的器件，其中所述第二半导体芯片被横向设置在所述第一半导体芯片的轮廓外部。
7. 权利要求1所述的器件，其中所述第一载体和所述第二载体中的至少一个包括引线框架。
8. 权利要求1所述的器件，其中所述第一载体和所述第二载体由不同材料制成。
9. 权利要求1所述的器件，其中所述第一半导体芯片包括复合半导体。
10. 权利要求1所述的器件，还包括：
电耦合到所述第一半导体芯片的第一再分布层；以及
电耦合到所述第二半导体芯片的第二再分布层。
11. 权利要求1所述的器件，其中所述第一半导体芯片的源电极电耦合到所述第二半导体芯片的漏电极。
12. 权利要求1所述的器件，还包括：
电耦合到所述第一半导体芯片的栅电极和所述第二半导体芯片的栅电极的驱动器电路。
13. 权利要求1所述的器件，还包括：
电耦合到所述第一载体和所述第二载体的通孔连接。
14. 一种器件，包括：
第一半导体芯片，被布置在第一载体之上；
密封材料，至少部分地密封所述第一半导体芯片；
层压材料，被布置在所述密封材料之上；
第二载体，至少部分地嵌入所述层压材料中；以及
第二半导体芯片，被布置在所述第二载体和所述层压材料之上。
15. 权利要求14所述的器件，其中所述第二载体电耦合到所述第一半导体芯片的第一电接触并且电耦合到所述第二半导体芯片的第二电接触，其中所述第二电接触被布置在所述第二半导体芯片面对所述第二载体的表面之上。
16. 一种器件，包括：
驱动器电路；
第一半导体芯片，其中所述驱动器电路和所述第一半导体芯片被单片集成在第一半导体材料中；以及
第二半导体芯片，被集成在第二半导体材料中，其中所述第二半导体材料包括复合半导体。
17. 权利要求16所述的器件，还包括：
被配置成控制所述驱动器电路的控制电路。
18. 权利要求16所述的器件，其中所述第一半导体芯片和所述第二半导体芯片被包括在共源共栅电路或半桥电路中。
19. 权利要求16所述的器件，其中所述驱动器电路被配置成控制所述第一半导体芯片的栅电极和所述第二半导体芯片的栅电极。
20. 权利要求16所述的器件，其中所述第一半导体芯片被横向设置在所述第二半导体芯片的轮廓外部。
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