CN102403296A - 半导体模块及其制造方法 - Google Patents
半导体模块及其制造方法 Download PDFInfo
- Publication number
- CN102403296A CN102403296A CN2011103320188A CN201110332018A CN102403296A CN 102403296 A CN102403296 A CN 102403296A CN 2011103320188 A CN2011103320188 A CN 2011103320188A CN 201110332018 A CN201110332018 A CN 201110332018A CN 102403296 A CN102403296 A CN 102403296A
- Authority
- CN
- China
- Prior art keywords
- contact element
- module
- insulating material
- semiconductor chip
- outstanding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05669—Platinum [Pt] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05672—Vanadium [V] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29344—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29355—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/8309—Vacuum
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8382—Diffusion bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85455—Nickel (Ni) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/8546—Iron (Fe) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10271—Silicon-germanium [SiGe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明涉及半导体模块及其制造方法。本发明涉及一种包括半导体芯片、至少两个接触元件和两个接触元件之间的绝缘材料的模块。此外,本发明还涉及用于制造这种模块的方法。一种模块,包括:半导体芯片;第一接触元件和第二接触元件,其与半导体芯片隔开并电耦合到半导体芯片,其中第一接触元件的表面和第二接触元件的表面被布置在公共平面中;电绝缘材料,其具有在第一接触元件和第二接触元件之间的区域中的平坦表面;从电绝缘材料的平坦表面突出的突出元件和/或在电绝缘材料的平坦表面中的凹陷。
Description
技术领域
本发明涉及一种包含半导体芯片和至少两个接触元件的模块。此外,本发明涉及这种模块的制造方法。
背景技术
典型地,包括半导体芯片的半导体模块具有至少两个或者更多的接触元件,其中向这些接触元件施加不同的电压。当操作所述模块时,应当防止接触焊盘的不希望的电耦合。这在减小模块尺寸和/或在向不同接触元件施加差别很大的电压时尤其重要。
附图说明
附图被包含以用于提供对实施例的进一步理解,并且其结合在该说明书中并构成说明书的一部分。所述附图阐明了实施例并且与描述一起用于解释实施例的原理。在其他实施例和实施例通过参考下面的详细描述将变得更好理解时,其众多预期优点将很容易理解。附图的元件相对彼此未必是按比例绘制的。同样的附图标记表示相似的部件。
图1A-1B示意性地图示模块的一个实施例的截面图和顶视图,该模块包括半导体芯片、第一接触元件、第二接触元件和位于第一和第二接触元件之间的绝缘材料;
图2A-2D示意性地图示模块的实施例的截面图,该模块包括半导体芯片、第一接触元件、第二接触元件和位于第一和第二接触元件之间的绝缘材料;
图3A-3D示意性地图示模块制造方法的实施例的截面图,该模块包括半导体芯片、第一接触元件、第二接触元件和位于第一和第二接触元件之间的绝缘材料;
图4A-4J示意性地图示模块制造方法的实施例的截面图,该模块包括半导体芯片、第一接触元件、第二接触元件和位于第一和第二接触元件之间的绝缘材料;
图5A-5G示意性地图示模块制造方法的实施例的截面图,该模块包括半导体芯片、第一接触元件、第二接触元件和位于第一和第二接触元件之间的绝缘材料;以及
图6A-6H示意性地图示位于第一和第二接触元件之间的绝缘材料的不同布置的截面图。
具体实施方式
在以下具体实施方式中,参照了附图,这些附图形成以下具体实施方式的一部分,并且其中以示意的方式示出了可实施本发明的具体实施例。在这一点上,参照所描述的(多个)附图的定向,使用了方向性术语,如“顶”、“底”、“前”、“后”、“首”、“尾”等等。由于实施例的组件可以以多个不同定向而定位,因此方向性术语用于示意的目的而决不进行限制。应当理解,在不脱离本发明的范围的前提下,可以利用其他实施例并且可以进行结构上或逻辑上的改变。因此,以下详细描述不应视为具有限制意义,并且本发明的范围由所附权利要求限定。
应当理解,这里所描述的各种示范性实施例的特征可以相互组合,除非另外特别说明。
正如本说明书中所采用的,术语“耦合”和/或“电耦合”并非意味着元件必须直接耦合在一起;在“耦合”或“电耦含”的元件之间可以提供介于其间的元件。
下面将描述包含半导体芯片的模块。所述模块也可以称为半导体封装、器件或设备,或可以使用任何其他适当的术语。半导体芯片可以是不同类型,可以采用不同的技术制造,并且可以包括例如集成电路,电光电路或电机械电路或无源元件。例如,半导体芯片可以配置为功率半导体芯片,如功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)、JFET(结栅场效应晶体管)、功率双极晶体管或功率二极管。此外,半导体芯片可以包括控制电路、微处理器或微机电组件。特别地,可以包含具有垂直结构的半导体芯片,也就是说半导体芯片采用电流沿垂直于半导体芯片的主表面的方向流动的方式制造。具有垂直结构的半导体芯片可以具有接触元件,特别地,在其两个主表面上,也就是说在其顶面(top side)和底面(bottom side)。特别地,功率半导体芯片可具有垂直结构。作为例子,功率MOSFET的源电极和栅电极可以位于一个主表面上,而功率MOSFET的漏电极被布置在另一主表面上。此外,下文所描述的模块可以包括集成电路,用于控制其他半导体芯片的集成电路,如功率半导体芯片的集成电路。半导体芯片不需要采用特定的半导体材料如Si,SiC,SiGe,GaAs制造,并且还可以包含并非半导体的无机和/或有机材料,如绝缘体、塑料或金属。此外,半导体芯片可以是封装的或未封装的。
半导体芯片可以具有电极(或接触焊盘),其允许和包含在半导体芯片中的集成电路形成电接触。对半导体芯片的电极施加一个或多个金属层。金属层可以以任意期望的几何形状和任意期望的材料成分来制造。例如,金属层为覆盖一区域的层的形式。任何期望的金属或金属合金,例如铝、钛、金、银、铜、钯、铂、镍或镍钒,可以作为材料。金属层不需要是同质的或仅由一种材料制造,也就是说金属层中可以包含多种成分和浓度的材料。电极可以位于半导体芯片的有源主表面或半导体芯片的其他表面上。
下文所描述的模块可包括外部接触元件(或外部接触焊盘),其可以为任意形状和尺寸。外部接触元件可以与模块的外部接近,并且因此可以允许从模块的外部形成与半导体芯片的电接触。此外,外部接触元件可以是导热的并且可以作为热沉以用于耗散由半导体芯片产生的热量。外部接触元件可以由任何期望的导电材料构成,例如金属,如铜,铝或金,金属合金或导电有机材料。焊接材料,如焊球或焊接凸点,可以沉积在外部接触元件上。
半导体芯片可以放置于载体上。载体可以为任何形状、尺寸和材料。在模块的制造期间载体可以彼此连接。载体也可以整件地形成。在制造过程中,载体可以以将一些载体分离为目的,通过连接方式在彼此之间连接。载体的分离可以通过机械锯(mechanical sawing)、激光束、切割、冲压、磨、蚀刻或任何其它合适的方法实现。载体可以是导电的。它们可以采用金属或金属合金制造,特别得,铜、铜合金、铁镍、铝、铝合金、钢、不锈钢或其它合适的材料。载体可以整体采用金属或金属合金制造。例如,载体可以是引线框或引线框的一部分。此外,载体可以镀有导电材料,例如,铜、银、铁镍或镍磷。
模块可以包括电绝缘材料。电绝缘材料可以覆盖该模块的任意数量的组件表面的任意部分,如集成在模块中的接触元件和半导体芯片。电绝缘材料可以用于使模块的组件彼此和/或与外部组件电绝缘,但是也可以用作安装其它组件的平台,例如,配线层或接触元件。电绝缘材料可以采用多种技术沉积,例如,采用模版印刷、丝网印刷或任何其他合适的印刷技术。可替换地,电绝缘材料可以作为箔或者片通过施加真空以及加热和加压一段合适的时间而层压到基础结构上。还可以提供:电绝缘材料也从溶液或气相沉积来提供并且可以以逐层的方式构造达到期望的厚度。可以采用的用于这类沉积的技术,例如是,物理或化学气相沉积、旋压(spinning)、调剂(dispensing)、浸渍(dipping)、或喷射(spraying)。电绝缘材料可以由聚合物,如聚对二甲苯、光阻材料、酰亚胺、环氧树脂、热固塑料(duroplast)、硅、氮化硅或无机、陶瓷类材料,如硅-碳化合物形成。此外,模塑材料(mold material)可以用作电绝缘材料。模塑材料可以是任何合适的热塑性或热固性材料。可以采用多种技术来利用模塑材料覆盖组件,例如压缩模塑(compression molding)、注射模塑(injection molding)、粉料模塑(powder molding)或液体模塑(liquid molding)。
模块可以具有安装表面。安装表面用于将模块安装到另一组件上,例如,如电路板的衬底,例如,印刷电路板(PCB)。例如,模块可以是所谓的表面安装模块(SMD),其可以利用多种表面安装技术(SMT)而安装到衬底如印刷电路板上。外部接触元件可以设置在安装表面上以允许将模块电耦合到其上安装模块的组件。可以使用焊料沉淀物,如焊球,或其它合适的连接元件,在模块及在其上安装模块的组件之间建立电连接和尤其是机械连接。
图1A和1B示意性地举例说明一个模块100。图1A绘出了模块100的截面图,并且图1B绘出了模块100的顶平面图。模块100包括半导体芯片10、第一接触元件13、第二接触元件14和绝缘材料16。半导体芯片10是功率半导体芯片,其具有第一主表面10A和与第一主表面10A相对的第二主表面10B。第一电极11被布置在第一主表面10A处,并且第二电极12被布置在第二主表面10B处。半导体芯片10还具有布置在第二主表面10B上的第三电极28。
在图1A和1B示范性示出的功率MOSFET的情况下,第一和第二电极11、12可以分别是漏和源电极(负载电极),并且第三电极28可以是栅电极(控制电极)。一般地,半导体芯片10可以具有任意数量的电极。例如,半导体芯片10可以具有两个电极(如,在二极管的情况下,阴极和阳极)或可以具有三个或更多的电极。在一个实施例中(没有在附图中示出),半导体芯片10可以只在一个有源表面上布置其所有的电极。例如,半导体芯片10可以在一个主表面上具有多个电极并且可以适合于倒装芯片安装。
在模块100中,半导体芯片10被安装,其中其第一主表面10A位于第一接触元件13上,使得其第一电极11电耦合到第一接触元件13。电极12和28通过接合线15电耦合到第二接触元件14。尽管在图1A和1B中仅示出每个电极一条接合线,但是任意数量的接合线可以用于连接电极到接触焊盘。可以采用多种其他电连接方式来替代接合线,例如,预制金属夹(pre-fabricated metalclips)、金属箔或电镀或CVD沉积的导电层。
例如,接触元件13和14可以是载体的部分,如可以是引线框的部分。引线框可以具有任意的几何形状并且其(外部)接触元件13和14可以以任意方式布置。引线框并不限定于任何尺寸,例如,引线框可以具有从100μm到1mm范围的厚度或甚至可以更厚。引线框可以整体采用金属,例如铜,或金属合金制造。可以冲压(stamp)或碾磨引线框以便产生如图1B示出的引线框的外部形状。引线框可以包括图1A和1B中未示出的另外的管芯焊盘和/或外部接触元件。
功率半导体芯片10可以放置在接触元件13之上,所述接触元件13作为如图1A或1B示出的管芯焊盘。漏电极11可以电连接到接触元件13,并且例如,电连接可以通过回流焊接、真空焊接、扩散焊接(diffusion soldering)或依靠导电粘合剂的粘合来实现。
如果采用扩散焊接作为连接技术,则可以使用由于界面扩散工艺而在焊接操作结束之后,在接触元件13和功率半导体芯片10之间的界面导致金属间相的焊接材料。在这种情况下,可以想到采用Sn、AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi或Au焊料。如果功率半导体芯片10粘合到接触元件13上,则可以使用基于环氧树脂并且富集金、银、镍或铜以便产生导电性的导电粘合剂。
接触元件13和14可以布置于公共平面100A上。在图1A和1B描述的实施例中,接触元件13、14分别具有第一和第二表面13A、13B和14A、14B,并且布置在公共平面上,使得第一表面13A、14A布置在公共平面100A中并且第二表面13B、14B布置在与平面100A共面的公共平面中。平面100A可以形成安装表面。接触元件13、14可以用作外部接触元件以从模块100外部电接入(electrically access)半导体芯片10。模块100可以是无引线模块,如接触元件13、14都是焊盘而不是从模块100横向突出的引脚。
模块100还包括包埋(embed)半导体芯片10并且填充第一和第二接触元件13、14之间的空间的绝缘材料16。绝缘材料16例如可以是模塑材料并且可以通过注射模塑方式施加到模塑腔中,在模塑腔中已经布置了具有第一和第二接触元件13、14和电连接元件15的半导体芯片10。
在图1A和1B所示的实施例中,绝缘材料16具有平坦的第一主表面16A和平坦的第二主表面16B。第一接触元件13的第一表面13A、第二接触元件14的第一表面14A和绝缘材料16的第一主表面16A布置在平面100A内,但是也可以布置在不同平面内。由绝缘材料16、第一和第二接触元件13、14形成的表面可以形成安装表面。安装表面并非必须是平坦表面,而是可以是平坦表面。第一和第二接触元件13、14也可以布置于不同平面。
在图1A和1B所示的实施例中,绝缘材料16具有突出元件17,其从绝缘材料16的第一表面16A突出。在布置于第一和第二接触元件13和14之间的绝缘材料16的表面的部分处,突出元件17A被布置于第一和第二接触元件13和14之间。突出元件17可以被配置以延长在沿着绝缘材料16的表面测量时第一和第二接触元件13、14之间的距离。这个距离,所谓的爬电距离,被定义为沿绝缘体表面两个导体之间的最短距离,其确定在哪个电压下两个导体之间发生电击穿。通过在绝缘材料的表面16A上布置突出元件17,相较于完全平坦表面增大了第一和第二接触元件13、14之间的爬电距离。因此添加突出元件17允许以第一和第二接触元件13、14之间更高的电压差来操作相似模块。在模块100的操作期间,可以在接触元件或电极13、14之间施加高于600V、800V、1000V、1200V或甚至更高的电压差。
在图1A和1B所示的实施例中,突出元件17与绝缘材料16整体地形成(formed integrally)。例如,突出元件17可以与绝缘材料16采用相同的材料同时形成。
突出元件17可以具有任意合适的高度h、宽度w和长度l。例如,高度h可以大于0.1mm或0.2mm或0.3mm或0.4mm或0.5mm或0.6mm或0.7mm或0.8mm或0.9mm或1mm或1.5mm或2.0mm或2.5mm。突出元件17的宽度w可以小于第一和第二接触元件13、14之间的距离。特别地,宽度w可以是第一和第二接触元件13、14之间的距离的几分之一,如该距离的一半或三分之一。例如,宽度w可以大于0.1mm或0.2mm或0.3mm或0.4mm或0.5mm或0.6mm或0.7mm或0.8mm或0.9mm或1mm或1.5mm或2.0mm或2.5mm。突出元件17的长度1可以与模块100的尺寸相同,如图1B所示,或可以更小。例如,突出元件17的长度1可以小于接触焊盘的尺寸或可以略微更大。依照一个实施例,可以选择突出元件17的长度使得其阻隔接触元件各部分之间的任何直接连接(视线(line-of-sight)连接)。可以添加具有与突出元件17的高度相近的长度的附加端部。在一个实施例中,可以使用多个突出元件17替代单个突出元件17。在这种情况下,突出元件17的宽度w相应地减小,如可以对应于第一和第二接触元件13、14之间距离除以突出元件17的数量。
如2A示出一实施例,其中突出元件18与绝缘材料16不是整体地形成。作为替代,突出元件18单独地形成并且附着于第一和第二接触元件13、14之间区域中的绝缘材料16的平坦表面。例如,突出元件18可以是用相同或不同的绝缘材料制造的杆,并且例如可以通过粘合剂附着于绝缘材料16。当将突出元件18附着于绝缘材料16时,可能希望确保在突出元件18和绝缘材料16之间没有间隙以便防止具有较小爬电距离的捷径。在可替换的实施例中,突出元件18可以从液相或气相沉积到绝缘材料16上并且可以在不需要额外的粘合剂的情况下粘附于绝缘材料16。
图2B示意性地图示一实施例,其中凹陷(recess)19形成在绝缘材料16中。与上文所描述的突出元件17、18相似,凹陷19允许相较于绝缘材料16的完全平坦表面增大爬电距离。例如,凹陷19可以通过从绝缘材料16移除材料或通过不向将形成凹陷19的区域施加绝缘材料,例如,通过使用合适的模塑腔,来形成。凹陷19的尺寸可以与上文描述的突出部分的尺寸相似。
图2C示意性地图示一实施例,其中绝缘材料16的第一表面16A和由第一和第二接触元件13、14的第一表面13A、14A形成的公共平面100A布置在不同的平面中。第一和第二接触元件13、14的侧面仅部分被绝缘材料16覆盖,并且由表面13A、14A和16A形成的安装表面没有形成平坦表面。绝缘材料16的第一表面16A可以布置在由第一接触元件13的第一表面13A和第二表面13B之间所限定的平面之间的任意位置。与上文所描述的实施例相似,向绝缘材料16的第一表面16A施加突出元件20。
图2D示意性地图示一实施例,其中与图2C中示出的实施例相似,绝缘材料16的第一表面16A相对于接触元件13、14缩回。图2D中图示出的实施例与图2C中图示出的实施例的区别在于在绝缘材料16的第一表面16A中提供凹陷21来替代突出元件20。
图3A-3D示意性地图示出图3D示出的模块的制造方法。图3D示出的模块是图2A示出的模块的实现。因此下文关于图3A-3D所描述的模块的细节可以同样应用到图2A示出的模块,并且反之亦然。相似的或相同的模块组件由采用相同的附图标记表示。
图3A示意性地图示第一步骤,其中提供了接触元件13、14。例如,接触元件13、14可以是引线框的部分并且可以被提供在公共平面100A上。第一接触元件13具有第一表面13A和第二表面13B。提供半导体芯片10,其包括具有第一电极11的第一主表面10A和与第一主表面10A相对的第二主表面10B。半导体芯片10被放置并附着于第一接触元件13上,例如,采用焊接、金属间接合或导电粘合剂,以使得第一接触元件13电耦合到第一电极11。在图3A示出的实施例中,半导体芯片10在其第二主表面10B上还具有第二电极12。
图3B示意性地图示第二步骤,其中半导体芯片10的第二电极12通过接合线15电耦合到第二接触元件14。如上文所解释的,可以采用多种其他技术来连接第二电极12到第二接触元件14。在一个实施例中(未示出),还可以提供:第二电极12还被布置于半导体芯片10的第一主表面10A上,并且半导体芯片10放置在第一和第二接触元件13、14之上。
图3C示意性地图示第三步骤,其中用绝缘材料16覆盖图3B中示出的模块。例如,可以使用模塑工艺来施加绝缘材料16。在一个实施例中,图3B描述的模块可以放置于模塑腔内。在另一个实施例中,图3A示出的接触元件13、14可以放置于模塑板上,该模塑板形成模塑腔的一部分,如模塑腔的下半部。例如,模塑板可以提供图3A所示的公共平面100A。模塑腔可以通过提供在下半部之上施加的上半部来形成。在模塑步骤之后,可以移除模塑腔以获得图3C所示的模块。绝缘材料16可以具有第一主表面16A和与第一表面16A相对的第二主表面16B。绝缘材料16的主表面16A可以布置于平面100A中并且可以与接触元件13、14一起形成平坦的安装表面。
图3D示意性地图示第四步骤,其中添加突出元件18到图3C所示的模块。例如,突出元件18可以被预制并可以通过粘合剂附着于第一和第二接触元件13、14之间的区域中的绝缘材料16。突出元件18也可以由液相或气相沉积到绝缘材料16上并且可以被硬化以得到图3D所示的模块。
图4A-4J示意性地图示了图1A和1B所示模块的制造方法。因此下文关于图4A-4J所描述的模块细节可以同样地应用到图1A和1B示出的模块,并且反之亦然。相似的或相同的模块组件采用相同的附图标记来表示。
图4A和4B示意性地图示第一和第二制造步骤,其与上文关于图3A和3B所描述的第一和第二步骤相同。
图4C示出使用模塑材料作为绝缘材料的情况的第三步骤。半导体芯片10和第一和第二接触元件13、14被放置在模塑腔M1和M2内以用于施加绝缘模塑材料16。更具体地,图4B描述的模块放置在模塑板M1上,并且被模塑腔M1、M2的上半部M2覆盖,所述模塑板M1形成了模塑腔M1、M2的下半部。模塑腔的下半部M1具有凹陷R,其用于形成从由第一和第二接触元件13、14限定的公共平面100A突出的突出元件17。
图4D示出在从模塑腔M1、M2中移除模塑的半导体模块之后的第四步骤。模塑的半导体模块放置于衬底30上。衬底30包括第一和第二端子34、35,第一和第二接触元件13、14放置在第一和第二端子34、35上。第一和第二接触元件13、14应当与衬底30上的第一和第二端子34、35电耦合并应当机械附着于第一和第二端子34、35。这例如可以通过在第一和第二接触元件13、14上添加焊料32、33,如图4D所示,并通过焊接第一和第二接触元件13、14到衬底30上的第一和第二端子34、35来实现。模塑的半导体模块可以放置在衬底30上,以使得突出元件17被放置于衬底30中提供的凹陷31上。衬底30中的凹陷30可以配置为容纳突出元件17,该突出元件17从绝缘材料16的第一表面16A突出,如图4E所示。在一个实施例中,替代向第一和第二接触元件13、14施加焊接材料32、33,可以向衬底30的第一和第二端子34、35施加焊接材料32、33。在一个实施例中,可以向接触元件13、14和端子34、35中的每一个施加焊接材料32、33。
衬底30中的凹陷31可以稍大于突出元件17以便充裕地容纳突出元件17,并且可以足够大以允许模塑的半导体模块和衬底20之间的一定未对准。
在一个实施例中,凹陷31的尺寸可以足够小,使得突出元件17能够防止焊接材料32、33在模塑芯片被压到衬底30上时流向各其他触点。换句话说,凹陷31可以足够小,使得突出元件17能够有效地密封第一和第二接触元件13、14之间的连接。因此,由于适合凹陷31的突出元件17,焊接材料32不会流向接触元件14、35,并且焊接材料33不会流向接触元件13、34。
图4E示意性地图示在焊接模块100到衬底30之后所得到的系统。焊接材料32’、33’在将模塑芯片压到衬底30上期间已经被横向延展,但是装入凹陷31中的突出元件17有效地防止了两个焊接材料32’、33’彼此电接触以及变得彼此过于接近而允许经由爬电电流的电连接。
图4F和4G示意性地图示了一实施例,其中图4D和4E中示出的凹陷31是一个通孔36,其延伸穿过整个衬底30。例如,凹陷31可以通过蚀刻或钻孔形成,而通孔36也可以通过冲压或其它工艺形成。
图4H-4J示出施加绝缘材料16的可替换方式。
图4H示出这个方法的第一步骤,其中模块的组件被放置在模塑板M1上。从而,先提供模塑板M1。模塑板M1具有一个有凹陷R的平坦表面。之后,施加第一和第二接触元件13、14到模塑板M1。模塑板M1的表面,以及第一和第二接触元件13、14的表面13A、14A形成公共平面100A。包括具有电极11的第一主表面10A和具有第二电极12的第二主表面10B的半导体芯片10被放置并附着于第一接触元件13,以使得第一电极11电耦合在第一接触元件13。
图4I示意性地图示了第二步骤,其中接合线15附着于第二电极12和第二接触元件14。之后,模塑腔M2被放置在模块上以便将半导体芯片10、第一和第二接触元件13、14以及接合线15包埋在模塑化合物16中。模塑材料16也填充模塑板M1中的凹陷R。
图4J示出了在移除模塑腔M2和模塑板M1之后的模块。
图5A-5G示意性地图示了用于制造如图2B所示的模块的方法的实施例。下文关于图5A-5G所描述的模块的细节因此可以同样地应用到图2B示出的模块,并且反之亦然。相似的或相同的模块组件采用相同的附图标记来表示。
图5A-5C示意性地图示了第一、第二和第三步骤,其与上文关于图3A-3C所描述的第一、第二和第三步骤相同。
图5D示出第四步骤,其中通过从第一和第二接触元件13、14之间区域中的绝缘材料的平坦表面上移除材料来在绝缘材料16中形成凹陷19。例如,材料可以通过蚀刻、钻孔、光刻技术或其它合适方法移除。
图5E示出第五步骤,其中图5D示出的模块被放置在衬底30上。与图4D示出的实施例相似,衬底30具有第一和第二端子34和35。在图5E所示的实施例中的衬底30不具有凹陷31,但是相反具有从衬底30的主表面30B突出的突出元件36。
在图5E示出的实施例中,模塑的半导体芯片放置于衬底30上以进行焊接步骤,使得模塑半导体模块中的凹陷19容纳从衬底30突出的突出元件36。
凹陷19相对于突出元件36的尺寸可以与上文描述的相似,即可以虑及横向未对准和/或可以虑及两个组件之间的间隙的密封。
图5F示意性地图示了在焊接模塑芯片到衬底30之后所得到的模块。焊接材料32’、33’在将模塑芯片压到衬底30上期间已经被横向延展,但是突出元件36和容纳凹陷19有效地防止了两个焊接材料32’、33’彼此之间电接触以及变得彼此过于接近而允许经由爬电电流的电连接。
图5G示意性地图示了图5C所示的方法步骤的可替换方案。在图5G所示的实施例中,具有突出元件50的模塑腔被用于在绝缘材料16中产生凹陷19。这允许与施加绝缘材料16同时地产生凹陷。
图6A-6H示意性地图示了在绝缘材料16上或中形成突出元件或凹陷的实施例。
图6A示出一实施例,其中凹陷具有矩形截面。截面不必是精确的矩形,而是也可以具有略圆的边缘。
图6B示出一实施例,其中凹陷具有三角形截面。同样,截面不必是精确的三角形,但是也可以具有略圆的边缘。
图6C示出一实施例,其中凹陷具有凹曲(concave curved)截面。例如,这样的截面可以通过蚀刻工艺获得。
图6D示出一实施例,其具有多个矩形凹陷。凹陷不必是均等的。例如,也可以是多个不同形状的凹陷。
图6E-6H示出了具有与图6A-6D示出的相同形状的实施例,但是采用突出元件替代了凹陷。
除图6A-6H示出的实施例外,还可以存在结合不同形状和/或不同尺寸的突出元件或凹陷的实施例。突出元件和凹陷也可以相结合。其上放置模块的衬底的突起元件或凹陷的尺寸和形状可以相应地改变。
对本领域技术人员来说显而易见的是,上文所描述的模块仅仅指的是示范性实施例,并且可以进行多种变化。例如,上文讨论的模块可以通过批量生产来制造,其中多个相似模块被同时且并行制造。如果需要,模块可以通过引线框的分离而彼此分离。例如,分离引线框可以通过锯、切割、蚀刻或激光束或其它电磁辐射来执行。
此外,虽然本发明实施例的特定特征或方面可能已经关于多个实现中的一个被公开,但是,对于任意给定的或特定的应用,根据期望的或有利地,这种特征或方面可以与其它实现的一个或多个其它特征或方面相结合。此外,作为扩展,在详细描述或权利要求中使用的术语“包括”、“具有”、“有”或其它类似变型,这些术语与术语“包含”类似旨在表示包含性的。而且,应当理解本发明实施例可以应用于分立电路、部分集成电路或完全集成电路或编程装置。同样,术语“示范性”仅仅意味着例子,而不是最佳的或最优的。也应该意识到,出于简单并且容易理解的目的,这里所描述的特征和/或元件相对彼此具有特定尺寸,并且实际的尺寸与这里示出的尺寸可以有很大不同。
尽管这里示出并描述了特定实施例,但是应该意识到对于本领域技术人员,在不脱离本发明的范围的情况下多种替换和/或等效实施方式可以替代所示出并描述的特定实施例。本申请意在涵盖这里所讨论的特定实施例的任意改变或变化。因此,本发明意在仅由权利要求及其等价物来限定。
Claims (23)
1.一种模块,包括:
半导体芯片;
第一接触元件和第二接触元件,其与半导体芯片隔开并电耦合到半导体芯片,其中第一接触元件的表面和第二接触元件的表面被布置在公共平面中;
电绝缘材料,其具有在第一接触元件和第二接触元件之间的区域中的平坦表面;以及
从电绝缘材料的平坦表面突出的突出元件和/或在电绝缘材料的平坦表面中的凹陷。
2.权利要求1的模块,其中突出元件或凹陷包括与电绝缘材料整体地形成的突出元件。
3.权利要求1的模块,其中电绝缘材料的平坦表面被布置在所述公共平面中。
4.权利要求1的模块,其中半导体芯片具有在第一主表面上的第一电极和在与第一主表面相对的第二主表面上的第二电极,并且第一接触元件电耦合到第一电极且第二接触元件电耦合到第二电极。
5.权利要求1的模块,其中第一接触元件和第二接触元件是其上放置半导体芯片的引线框的部分。
6.权利要求1的模块,还包括衬底,所述衬底包括与第一接触元件电接触的第一端子和与第二接触元件电接触的第二端子。
7.权利要求6的模块,其中所述衬底具有突出元件和/或凹陷,所述突出元件伸入到电绝缘材料中的凹陷中,所述凹陷容纳从电绝缘材料突出的突出元件。
8.权利要求6的模块,其中所述衬底是印刷电路板。
9.一种模块,包括:
半导体芯片;
第一接触元件和第二接触元件,其与半导体芯片隔开并电耦合到半导体芯片;
电绝缘材料,其包埋半导体芯片,其中电绝缘材料、第一接触元件和第二接触元件形成安装表面;以及
突出元件,其从第一接触元件和第二接触元件之间的安装表面突出。
10.权利要求9的模块,其中所述突出元件与电绝缘材料整体地形成。
11.权利要求9的模块,其中所述模块是无引线模块。
12.权利要求9的模块,其中第一接触元件和第二接触元件被包埋在电绝缘材料中,并且第一接触元件的表面和第二接触元件的表面在安装表面处从电绝缘材料暴露出来。
13.一种系统,包括:
模块,包括:
半导体芯片;
第一接触元件和第二接触元件,其与半导体芯片隔开并电耦合到半导体芯片;
电绝缘材料,其包埋半导体芯片,其中电绝缘材料、第一接触元件和第二接触元件形成安装表面;
突出元件,其从第一接触元件和第二接触元件之间的安装表面突出;以及
衬底,其包括凹陷,其中模块以如下方式被安装在衬底上,其中模块的安装表面面向衬底并且衬底的凹陷容纳模块的突出元件。
14.权利要求13的系统,其中所述模块为无引线模块。
15.权利要求13的系统,其中所述衬底是印刷电路板。
16.一种方法,包括:
提供半导体芯片、电耦合到半导体芯片的第一接触元件和电耦合到半导体芯片的第二接触元件,其中第一接触元件的表面和第二接触元件的表面被布置在公共平面中;
在电绝缘材料中包埋半导体芯片,其中电绝缘材料具有在第一接触元件和第二接触元件之间的区域中的平坦表面;以及
形成突出元件和/或凹陷,所述突出元件从电绝缘材料的平坦表面突出,所述凹陷位于电绝缘材料的平坦表面中。
17.权利要求16的方法,其中所述突出元件或凹陷在半导体芯片被包埋在电绝缘材料中时形成。
18.权利要求16的方法,其中所述电绝缘材料的平坦表面被布置在公共平面中。
19.权利要求16的方法,其中所述半导体芯片具有在第一主表面上的第一电极和在与第一主表面相对的第二主表面上的第二电极,并且第一接触元件电耦合到第一电极且第二接触元件电耦合到第二电极。
20.权利要求16的方法,还包括:
将衬底附着于第一和第二接触元件,其中衬底具有凹陷或通孔以用于容纳从电绝缘材料突出的突出元件,或者具有伸入到电绝缘材料中的凹陷中的突出元件。
21.一种方法,包括:
提供模块,包括:
半导体芯片;
第一接触元件和第二接触元件,其与半导体芯片隔开并电耦合到半导体芯片;
电绝缘材料,其包埋半导体芯片,其中电绝缘材料、第一接触元件和第二接触元件形成安装表面;
突出元件,其从第一接触元件和第二接触元件之间的安装表面突出;以及
在衬底上安装模块,其中模块以如下方式被安装在衬底上,其中模块的安装表面面向衬底并且衬底的凹陷容纳模块的突出元件。
22.权利要求21的方法,其中所述模块是无引线模块。
23.权利要求21的系统,其中所述衬底是印刷电路板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/881003 | 2010-09-13 | ||
US12/881,003 US8314489B2 (en) | 2010-09-13 | 2010-09-13 | Semiconductor module and method for production thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102403296A true CN102403296A (zh) | 2012-04-04 |
Family
ID=45805843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011103320188A Pending CN102403296A (zh) | 2010-09-13 | 2011-09-13 | 半导体模块及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8314489B2 (zh) |
CN (1) | CN102403296A (zh) |
DE (1) | DE102011113269A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106449614A (zh) * | 2015-08-13 | 2017-02-22 | 富士电机株式会社 | 半导体装置 |
CN108269771A (zh) * | 2017-01-03 | 2018-07-10 | 英飞凌科技股份有限公司 | 包括限定出凹口的包封材料的半导体装置 |
CN109326571A (zh) * | 2018-09-26 | 2019-02-12 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装组件及其制造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569099B (zh) * | 2010-12-28 | 2014-12-10 | 万国半导体(开曼)股份有限公司 | 一种倒装芯片的封装方法 |
DE102011114635A1 (de) * | 2011-10-04 | 2013-04-04 | Smartrac Ip B.V. | Chipkarte und Verfahren zur Herstellung einer Chipkarte |
JP5974667B2 (ja) * | 2012-06-25 | 2016-08-23 | 株式会社デンソー | 電子装置 |
US20140001622A1 (en) * | 2012-06-27 | 2014-01-02 | Infineon Technologies Ag | Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages |
US8877555B2 (en) * | 2012-11-16 | 2014-11-04 | Alpha & Omega Semiconductor, Inc. | Flip-chip semiconductor chip packing method |
DE102014108916B4 (de) | 2014-06-25 | 2019-12-05 | Heraeus Deutschland GmbH & Co. KG | Bandförmiges Substrat zur Herstellung von Chipträgern, elektronisches Modul mit einem solchen Chipträger, elektronische Einrichtung mit einem solchen Modul und Verfahren zur Herstellung eines Substrates |
US9768087B2 (en) * | 2014-10-08 | 2017-09-19 | Infineon Technologies Americas Corp. | Compact high-voltage semiconductor package |
DE102015109073B4 (de) * | 2015-06-09 | 2023-08-10 | Infineon Technologies Ag | Elektronische Vorrichtungen mit erhöhten Kriechstrecken |
US9373569B1 (en) | 2015-09-01 | 2016-06-21 | Texas Instruments Incorporation | Flat no-lead packages with electroplated edges |
US10128169B1 (en) * | 2017-05-12 | 2018-11-13 | Stmicroelectronics, Inc. | Package with backside protective layer during molding to prevent mold flashing failure |
JP6881238B2 (ja) * | 2017-10-31 | 2021-06-02 | 三菱電機株式会社 | 半導体モジュール、その製造方法及び電力変換装置 |
DE102017220160A1 (de) * | 2017-11-13 | 2019-05-16 | Zf Friedrichshafen Ag | Sensorschutzvorrichtung für einen Sensor zum Sensieren in Getriebeöl, Sensor mit einer Sensorschutzvorrichtung und Verfahren zum Herstellen einer Sensorschutzvorrichtung |
DE102020131070B4 (de) | 2020-11-24 | 2023-03-09 | Infineon Technologies Ag | Package mit einer erhöhten Leitung und einer Struktur, die sich vertikal vom Boden des Verkapselungsmittels erstreckt, elektronisches Gerät sowie Verfahren zur Herstellung eines Packages |
JP7484770B2 (ja) | 2021-02-26 | 2024-05-16 | 三菱電機株式会社 | 半導体パッケージ |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121654A (ja) * | 1982-01-12 | 1983-07-20 | Seiko Epson Corp | パツケ−ジic |
JPH0737932A (ja) * | 1993-07-22 | 1995-02-07 | Toshiba Corp | 半導体装置およびその実装方法 |
CN1179626A (zh) * | 1996-09-05 | 1998-04-22 | 国际整流器公司 | 一种改进的表面封装的大功率半导体封壳及其制造方法 |
JPH11251621A (ja) * | 1998-02-27 | 1999-09-17 | Sharp Corp | 光結合装置及びその製造方法 |
US20020005576A1 (en) * | 2000-07-05 | 2002-01-17 | Noriaki Sakamoto | Semiconductor device and method of manufacturing the same |
CN1397092A (zh) * | 2000-02-02 | 2003-02-12 | 康宁股份有限公司 | 用倾斜壁基座进行的被动对齐 |
US6776663B2 (en) * | 2000-11-08 | 2004-08-17 | Infineon Technologies Ag | Electronic component with isolation barriers between the terminal pins |
TW200623286A (en) * | 2004-12-22 | 2006-07-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with support structure and fabrication method thereof |
CN101211904A (zh) * | 2006-12-28 | 2008-07-02 | 株式会社日立制作所 | 双向开关模块 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476481B2 (en) | 1998-05-05 | 2002-11-05 | International Rectifier Corporation | High current capacity semiconductor device package and lead frame with large area connection posts and modified outline |
TWI249828B (en) * | 2001-08-07 | 2006-02-21 | Advanced Semiconductor Eng | Packaging structure for semiconductor chip and the manufacturing method thereof |
KR100958422B1 (ko) | 2003-01-21 | 2010-05-18 | 페어차일드코리아반도체 주식회사 | 고전압 응용에 적합한 구조를 갖는 반도체 패키지 |
JP2007073743A (ja) | 2005-09-07 | 2007-03-22 | Denso Corp | 半導体装置 |
-
2010
- 2010-09-13 US US12/881,003 patent/US8314489B2/en active Active
-
2011
- 2011-09-13 CN CN2011103320188A patent/CN102403296A/zh active Pending
- 2011-09-13 DE DE102011113269A patent/DE102011113269A1/de not_active Ceased
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121654A (ja) * | 1982-01-12 | 1983-07-20 | Seiko Epson Corp | パツケ−ジic |
JPH0737932A (ja) * | 1993-07-22 | 1995-02-07 | Toshiba Corp | 半導体装置およびその実装方法 |
CN1179626A (zh) * | 1996-09-05 | 1998-04-22 | 国际整流器公司 | 一种改进的表面封装的大功率半导体封壳及其制造方法 |
JPH11251621A (ja) * | 1998-02-27 | 1999-09-17 | Sharp Corp | 光結合装置及びその製造方法 |
CN1397092A (zh) * | 2000-02-02 | 2003-02-12 | 康宁股份有限公司 | 用倾斜壁基座进行的被动对齐 |
US20020005576A1 (en) * | 2000-07-05 | 2002-01-17 | Noriaki Sakamoto | Semiconductor device and method of manufacturing the same |
US6776663B2 (en) * | 2000-11-08 | 2004-08-17 | Infineon Technologies Ag | Electronic component with isolation barriers between the terminal pins |
TW200623286A (en) * | 2004-12-22 | 2006-07-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with support structure and fabrication method thereof |
CN101211904A (zh) * | 2006-12-28 | 2008-07-02 | 株式会社日立制作所 | 双向开关模块 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106449614A (zh) * | 2015-08-13 | 2017-02-22 | 富士电机株式会社 | 半导体装置 |
CN106449614B (zh) * | 2015-08-13 | 2021-05-11 | 富士电机株式会社 | 半导体装置 |
CN108269771A (zh) * | 2017-01-03 | 2018-07-10 | 英飞凌科技股份有限公司 | 包括限定出凹口的包封材料的半导体装置 |
CN108269771B (zh) * | 2017-01-03 | 2021-11-23 | 英飞凌科技股份有限公司 | 包括限定出凹口的包封材料的半导体装置 |
CN109326571A (zh) * | 2018-09-26 | 2019-02-12 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装组件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20120061819A1 (en) | 2012-03-15 |
US8314489B2 (en) | 2012-11-20 |
DE102011113269A1 (de) | 2012-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102403296A (zh) | 半导体模块及其制造方法 | |
US9147637B2 (en) | Module including a discrete device mounted on a DCB substrate | |
CN101447442B (zh) | 包括在基底上放置半导体芯片的制造装置的方法 | |
CN101364548B (zh) | 集成电路模块的制造方法 | |
US9609748B2 (en) | Semiconductor module comprising printed circuit board and method for producing a semiconductor module comprising a printed circuit board | |
US10418319B2 (en) | Method of manufacturing a semiconductor device | |
CN101419964B (zh) | 具有多个半导体芯片的装置 | |
US8410590B2 (en) | Device including a power semiconductor chip electrically coupled to a leadframe via a metallic layer | |
US9018744B2 (en) | Semiconductor device having a clip contact | |
CN101393899B (zh) | 半导体器件 | |
US8324739B2 (en) | Semiconductor device | |
US8643176B2 (en) | Power semiconductor chip having two metal layers on one face | |
CN103367313A (zh) | 电子装置及制造电子装置的方法 | |
US11776882B2 (en) | Method of fabricating a semiconductor package | |
US20160365296A1 (en) | Electronic Devices with Increased Creepage Distances | |
US9837380B2 (en) | Semiconductor device having multiple contact clips | |
CN104051363A (zh) | 芯片封装和用于制造该芯片封装的方法 | |
JP2010034350A (ja) | 半導体装置 | |
US9818730B2 (en) | Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement | |
US12002739B2 (en) | Semiconductor device including an embedded semiconductor die | |
CN104037152A (zh) | 芯片载体结构、芯片封装及其制造方法 | |
US10304751B2 (en) | Electronic sub-module including a leadframe and a semiconductor chip disposed on the leadframe | |
US9263421B2 (en) | Semiconductor device having multiple chips mounted to a carrier | |
EP4369394A1 (en) | Power semiconductor package and method for fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120404 |