CN1397092A - 用倾斜壁基座进行的被动对齐 - Google Patents
用倾斜壁基座进行的被动对齐 Download PDFInfo
- Publication number
- CN1397092A CN1397092A CN01804479A CN01804479A CN1397092A CN 1397092 A CN1397092 A CN 1397092A CN 01804479 A CN01804479 A CN 01804479A CN 01804479 A CN01804479 A CN 01804479A CN 1397092 A CN1397092 A CN 1397092A
- Authority
- CN
- China
- Prior art keywords
- chip
- recess
- matrix
- recesses
- projectioies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 12
- 238000010309 melting process Methods 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 47
- 239000011159 matrix material Substances 0.000 description 77
- 238000005516 engineering process Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- 238000003466 welding Methods 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000005272 metallurgy Methods 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 241001074085 Scophthalmus aquosus Species 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/423—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using guiding surfaces for the alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Wire Bonding (AREA)
- Semiconductor Lasers (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
提供一种装置(10),它包括具有多个焊接隆起部(20)和多个形成在预定部位的凹部(18)的第一芯片(12)。一第二芯片(14)设置有多个焊接垫片(26)和凸起(24)。多个焊接结合剂(30)连接在第一和第二芯片之间。凹部和凸起中的至少一方包括倾斜壁,在焊接结合剂进行软熔过程中用于捕获和引导另一方,使得第一芯片在焊接结合剂的表面张力的作用于相对所述第二芯片对齐。如果需要,在软熔过程中,对第一和第二芯片施加振动波,以辅助凸起相对凹部移动。
Description
有关申请的参照
本申请要求2000年2月10日申请的欧洲申请00400283.8的利益。
发明背景
1.技术领域
本发明总的涉及光电子/光子器件,更具体地说,本发明涉及将一光电子/光子器件与一匹配基体被动地对齐、紧贴和结合在一起的方法和装置。
2.论述
电子元件混合涉及到将一基体上的光学元件与光电子/光子器件整合在一起。该技术包括用电气和机械手段使光电子/光子器件与基体上的光学元件(例如波导、光栅等等)连接在一起。光子元件混合的一个基本问题是器件相对基体的精确定位。确保这种定位精度的企图包括主动和被动对齐工艺。
广泛使用的被动对齐工艺包括使用倒装焊接法。美国专利5,499,312公开了一种用倒装焊接工艺将光电子元件被动对齐和封装到光波导的方法。该方法完全依赖于焊料表面张力和可湿垫片的设计,使波导与光电子元件对齐。在该结合顺序中,用一抓取和放置机构,使一上面形成有多个焊接隆起部的芯片(例如器件)在一基体上大致对齐,然后将组装件的温度上升到焊料熔化温度之上,焊料熔化时,在所有的界面出现表面张力,使芯片运动到最低势能点上,该点对应于与基体对齐。一旦芯片被对齐,即冷却焊料。
测试显示,这种被动对齐工艺的精度由于在焊料结合过程中的振动而在亚微米级到10微米以上的范围。而目前对光子元件混合的精度要求在X、Y和Z方向约在0.5微米。这样一来,这种工艺的精度的不确定导致它不适合用在光子组件中。
为了取消对焊料结合过程的对齐精度的依赖,所用的一些工艺中采用止动件和支座(standoff)。例如,德国专利19 644 758 A1公开了一种工艺,其中要连接的芯片具有插入基体上的凹部的凸起,以形成精确配合。凸起和凹部的尺寸精度取决于光刻术或微铣或微钻公差,通常小于一微米。
被动对齐技术的另一个例子公开在美国专利5,077,878中。在该工艺中,在一个芯片的表面上设置两个前基座和一个侧基座,在另一芯片上设置一垂直的侧壁。在安装时,第二芯片的前表面接触第一芯片的两个前基座,第二芯片的侧壁与第一芯片的侧基座匹配。在理论上它能使两个芯片精确对齐。
尽管测试显示,用上述的工艺可获得一些很好的结果,但结果仍然取决于在一个芯片上的止动件与在另一芯片上的边缘或凹部之间的摩擦力。这对于批量生产是一个严重的缺陷。为了该缺陷,有些制造商就采用主动对齐工艺。
主动对齐工艺的一类是采用能够进行很精密和准确的放置的抓取和放置机构。采用市场上有售的抓取和放置机构的主动对齐证实了准确度公差约为0.5微米。但是,这种抓取和放置机构很昂贵。同样,这种主动对齐工艺是不合算的。除了机器的价格之外,使用这样的机器不允多芯片结合。这导致生产率很低。因此,使用这种机器的制造过程不仅成本高,而且生产率低。
由此可见,需要提供一种将芯片对齐和结合到一基体上的方法和装置,而这种方法和装置克服了已有技术的缺陷。
发明概要
上述和其它的目的可通过一具有多个焊接隆起部和多个在相对于多个焊接隆起部的预定部位的凹部的第一芯片来实现。一第二芯片设置有多个焊接垫片和多个在相对于多个焊接垫片的预定部位的凸起。多个焊接结合剂置于多个焊接隆起部与多个焊接垫片之间和多个凸起与多个凹部之间的至少一个之间。多个凹部和多个凸起中的至少一方包括倾斜壁,在焊接结合剂进行软熔过程中用于捕获和引导多个凹部和多个凸起中的另一方,使得第一芯片在焊接结合剂的表面张力的作用下相对第二芯片对齐。根据本发明的另一方面,在软熔过程中对第一和第二芯片施加振动波,以辅助多个凸起相对多个凹部移动。
附图简要说明
为了更清楚地理解本发明的优点和目的,下面参考在附图中示出的具体的实施例来详细地说明本发明。要理解的是,这些附图仅仅示出了本发明的较佳实施例,因此,不能认为它们是限制本发明的范围的,因此将用附图和附加的特征和细节来描述和说明本发明,附图中:
图1是本发明的一被被动地对齐、紧贴和结合的光电子/光子器件和匹配的基体的侧视图;
图2是图1的器件和基体在预对齐之后但在结合之前的侧视图;
图3是基体上一凸起与器件的另一实施例的凹部啮合的侧视图;
图4是器件上的另一实施例的凸起与基体的倾斜壁凹部啮合的侧视图;
图5是器件的凸起与基体的另一实施例的凹部啮合的侧视图;
图6a-6b示出了器件的凸起进入基体的另一实施例的凹部;
图7a-7c示出了在振动波的辅助下器件的凸起进入基体的凹部;
图8a-8c示出了在振动波和湿润材料的辅助下另一实施例的器件的凸起进入基体的凹部;
图9a-9c示出了器件的其上沉积焊料球的凸起进入基体的凹部;
图10a-10c示出了器件的呈放大的焊料球形式的凸起进入基体的凹部;
图11a-11f示出了器件的凸起在振动波和一机械止动件的辅助下进入基体的凹部;
图12a-12b示出了根据本发明多个光电子/光子器件固定于一通用基体;以及
图13a-13b示出了根据本发明多个光电子/光子器件固定于一定制的基体。
较佳实施例的详细说明
本发明涉及用机械和电气手段使光电子器件与支承光学元件的基体互连。根据本发明的内容,形成在器件和/或基体上的多个凸起和多个凹部中,至少有一个包括带角度的壁,以捕获和引导其它凹部和凸起,从而在互连用的焊接结合剂软熔的过程中,该器件相对基体对齐。根据本发明的另一个方面,对器件和基体施加振动波,以辅助凸起相对凹部对齐。
参阅附图,图1示出按照本发明内容组装的装置10。该装置10包括一呈光电子/光子器件12形式的第一芯片,一呈光学元件支承基体14的第二芯片与之对置。器件12包括一本体16,在该本体16中形成多个凹部18。凹部18最好形成在相对于和本体16相连的多个粘接或焊接隆起部20的预选定位置。
基体14包括一基部22和多个伸出基部的凸起24。这些凸起24最好位于相对于和基部22相连的多个粘接或焊接垫26的预选定位置。选定凸起24的数量和位置,使之与器件12中的凹部18的数量和位置相匹配。凸起24包括与器件12的相邻凹部18啮合的倾斜壁28。通过改变倾斜壁28的斜度和/或凹部18的大小来控制器件12相对基体14的取向。
呈焊接结合剂30形式的结合部分置于每一焊接隆起部20与焊接垫片26之间,使器件12和基体14互连。如下面将要详细描述的,在软熔过程中利用焊接结合剂30的表而张力,使器件12相对基体14移动,同时通过凸起24与器件12的相邻凹部18的相互作用而使器件12相对基体14对齐。
下面参阅图2,描述用机械和电气手段使器件12和基体14互连的方法。器件12设置有多个最好用干刻工艺形成的凹部18。凹部18的直径尺寸取决于光刻和蚀刻参数。器件12的各向异性蚀刻(anisotropic etching)与高精度的光刻术相组合更有利于获取精确形状的凹部8。
然后将焊接隆起部20连接到器件12上。可用各种工艺制造欠压实冶金(under bump metallurgy)和焊接隆起部20。例如,可用电镀、热蒸发、模板印刷或焊料喷射来沉积焊接隆起部20。最好用光刻术和蒸发/电镀的组合来形成欠压实冶金部。
用湿或干刻工艺在基体14上形成凸起24。为了获得所需的几何形状,为基体14选择材料是很重要的。已经在硅树脂制成的基体14用湿刻工艺获得精确成形的倾斜凸起24。凸起24的倾斜角度通过硅树脂的结晶结构控制,而不取决于蚀刻过程。
然后将焊接垫片26连接于基体14。可用电镀、热蒸发、模板印刷或焊料喷射以及其它工艺来沉积焊接垫片26。可用光刻术和蒸发/电镀的组合来形成欠压实冶金部。
基体14上的凸起24和器件12上的凹部18相对焊接隆起部20和焊接垫片26的放置可以是任意的。但是,凸起24和凹部18的数量最好要优化,使凸起24与器件12的相邻凹部18之间的摩擦不会影响焊接结合剂30的垂直和水平的表面张力恢复力。
组装顺序包括将器件12定位在基体14上,使焊接结合剂30夹在焊接隆起部20和焊接垫片26之间。如果需要,在通过焊接结合剂30将器件12定位焊接到基体14的点上短时间内施加热量和压力。由于器件12和基体14的几何形状,凸起24现应该大致地与凹部18对齐。对于上述的初始放置过程最好使用一抓放机器。
将器件12定位在基体14上之后,装置10受到一软熔循环。在软熔循环过程中,焊接结合剂30熔化,使装置10的高度缩短。在缩短过程中,凸起24与器件12的相邻凹部18啮合并引导器件12相对基体14移动。凸起24和凹部18的几何形状限定了器件12相对基体14的对齐精度。
在大量制造的环境中,用一抓取和放置机构在一开始将器件12定位在基体14上。然后将装置10传送到一传统的软熔炉中以熔化焊接结合剂30。在抓取和放置机构与软熔炉之间进行传送的过程中以及在软熔的初始阶段中,使器件12相对基体14保持不动是很重要的。在这些过程中,上述的几何形状使器件12相对基体14锁定和紧贴在位,而不需要使用焊剂或熔化有机或无机的紧贴材料。此外,器件12在软熔过程中相对基体12的移动受到凸起24与凹部18相互作用的制约。
凸起24的包括高度和角度的几何形状、欠压实冶金部的几何形状和凹部18的直径导致了如图1所示的沙漏形(即凹陷)的焊接结合剂30。该形状导致焊接结合剂30有一较高的低周热疲劳寿命。还有,对于一定体积的焊料材料和一定直径的欠压实冶金,焊接结合剂30具有在软熔过程中导致大恢复力的较大的表面面积。
下面参阅图3,该图更详细地示出了凸起24和凹部18。图中还用假想线示出了另一实施例的凹部18’。器件12相对基体14的X、Y和Z向的对齐由基体14上的凸起24和器件12的凹部18的形状控制。较大的凹部18’使得器件12较之器件12的凹部18更靠近基体14定位。但是,凸起24的锥形和凹部18和18’的圆柱形使器件12相对基体14在X和Y的取向保持不变。有利的是,尺寸不正确的凹部18仅在Z方向导致不对准,而在X和Y方向不会形成不对准。
参阅图4,图中示出了另一实施例的装置10。在该实施例中,器件12a设置有圆柱形凸起24a,而基体14a设置有锥形凹部18a。凹部18a的倾斜壁28a使器件12a与基体14a的对齐能够几乎不受凸起24a的宽度和高度的影响,如图中用假想线所示的另一器件12a’的凸起24a’。
参阅图5,倾斜壁28a也使器件12a与基体14a的对齐不受凹部18a的宽度和高度变化的影响,如图中用假想线示出的将器件12定向成用标号12a’表示的另一实施例的凹部18a’。
参阅图6a和6b,示出了另一实施例的凹部18b。这种凹部18b的重要用途是允许器件12b相对基体14b粗略的预对齐。用非垂直壁的特征替代的凹部结构提供了这种功能。同样,倾斜壁28b制成圆弧形的,从而形成球形凹部18b。这类凹部尤其适合用干或蚀刻形成在用非结晶质材料制成的基体14b上。
参阅图7a-7c,这些图图示了使器件12c相对基体14c对齐的另一方法。该方法基本上与结合图1和2描述的方法相似,因此,在此不再重复相似步骤的描述。根据该方法,焊料32沿凸起24c和凹部18c内的基体14c沉积。然后器件12c大致地相对基体14c对齐。接着施加振动波34,使器件12c和基体14c彼此相对运动。借助重力,凸起24c落入凹部18c中。然后进行热循环,以熔化焊料32,从而在器件12c与基体14c之间形成结合。较佳的是,振动波采用声波或超声波,并具有对应于器件12c和基体14c几何形状的频率和波幅。
振动波34较佳的由与软熔炉相关联的超声波发生器提供。这种炉子能够在与批量生产相一致的单一时间内处理许多元件。此外,使用振动波34能够控制引起对齐的力的强度和波形。这使得对齐过程最佳化,从而提高产量。
采用图8a-8c,图中图示了使器件12d相对基体14d对齐的另一实施例的方法。在该实施例中,器件12d设置有电气垫片36。此外,将湿润材料38沉积在基体14d的凹部18d内。湿润材料38控制器件12d在Z方向相对基体14d的对齐。这是由于表面张力与VWA-FC工艺的相似。当凸起24d上的焊料32熔化时,焊料32弄湿湿润材38,由此引起垂直力。湿润材料38足够大,使器件12d上的垂直力将器件12d朝下拖向基体14d,如果需要,用振动波34帮助对齐。在正确对齐时,电气垫片36接触基体14d。
参阅图9a-9c,图中图示了使器件12e相对基体14e对齐的另一方法。在该实施例中,沉积在凸起24e上的焊料32e经受软熔过程,以便形成焊料球。焊料球32e的这种球形降低了凹部18e内的器件12e与凸起24e之间的摩擦。这样提高了振动波34的对齐效率。此外,焊料球32e的高度与非球形焊接结合剂相比有所增加,这种高度增加有可能增加在Z方向的移动范围,这使得在Z方向上的对齐更有效。
参阅图10a-10c,图中图示了使器件12f相对基体14f对齐的另一实施例。在该实施例中,凸起24f采用大焊料球32f的形式。焊料球凸起24f首先大致地相对凹部18f对齐。如果需要,则可用振动波34使焊料球凸起24f预对齐。此后,热循环熔化焊料球凸起24f,从而在器件12f与基体14f之间形成结合。
参阅图11a-11f,图中图示了使器件12g相对基体14g对齐的另一实施例。在该实施例中,在基体14g上靠近凹部18g设置机械止动件40,以将器件12g止挡在接近凹部18g的预选定区域。在施加振动波34时,器件12g似乎随意地相对基体14g移动。一段时间后,凸起24g落入凹部18g中。振动波34的频率、振幅和方向最好最佳化,以提高过程的效率。如图示,振动波34最好在整个过程中具有不同的波形。
参阅图12a-12b,图中图示了本发明的另一实施例。在该实施例中,将具有一有源器件42和一无源器件44的多个器件12h固定到一单个的通用基体14g上。有源和无源器件42和44可例如由若干激光器、波导(waveguide)、相位计(phasar)、组合器、SOA、光电二极管以及其它组成。有源器件42和无源器件44都设置有多个凸起24h,它们是根据预选定的、标准化规格形成的。有源器件42靠近凸起24h还设置有电气垫片36h。在每一凸起24h上都有焊料32h。
通用基体14g中包括多个凹部18h,它们是根据预选定的标准化规格形成的。每一凹部18h包括一倾斜壁28h,用于捕获和引导凸起24h。如果需要,各凹部18h还衬有湿润材料。电气垫片46沉积在通用基体14每一凹部18h附近。由于凸起24h和凹部18h的标准化规格,有利于通用基体14h连接于具有一组互补的凸起的任何器件中。
参阅图13a-13b,图中图示了本发明另一实施例。在该实施例中,将多个光电子/光子器件12i固定于一单个的专门设计的基体14i。器件12i由一激光器48、一开关50、一MMIC52和一ASIC54组成,当然,也可用其它器件替换。每一器件12i设置有多个根据预选定规格形成的凸起24i。这些器件12i中的一些设置有靠近凸起24i的电气垫片36i。图示的焊料32i在开关50的凸起24i上。
基体14i中形成多个与每一器件12i的凸起24i的结构相一致的凹部18i。每一凹部18i包括倾斜壁28i,以捕获和引导凸起24i。如果需要,每一凹部18i还可衬有湿润材料。在基体14i上沉积电气垫片46,与器件12i上的电气垫片36i匹配。由于凹部18i和凸起24i的规格互补,可将多个单个的器件12i连接到一公共的基体上。
图12A-13B示出的实施例尤其可用在需要将许多器件连接到单个基体上的光学模块。例如,这种模块可包括在一共用基体上具有光电二极管、MMIC、隔离器、过滤器和激光芯片的收发机、一交叉连接/相位计组件和一在SOA阵列与光电二极管之间设置相位计的可变光学放大器。
因此,本发明提供一种使光电子/光子器件相对一基体对齐的装置和方法。在器件和基体中的一方设置有若干凸起,同时在另一方设置有互补的凹部。凸起和凹部中的至少一方设置有倾斜壁,以捕获和引导另一方。用设置在器件和基体之间的焊料的表面张力获得自对齐。如果需要,还可对组件施加振动波,以加强对对齐的控制。
本领域的技术人员现在从上述的说明中应该了解到本发明的内容可以以种种形式实现。因此,尽管已根据其中的特定例子描述了本发明,但不应对本发明的范围进行如此的限定,因为,很显然,本领域的技术人员在阅读了附图、说明书和下面的权利要求书之后还可进行其它的改变。
Claims (10)
1.一装置,它包括:
一第一芯片,其上形成有多个结合块,所述第一芯片中还形成多个在相对于多个结合块的预定部位的凹部;
一第二芯片,其上形成有多个结合垫片,所述第二芯片还包括多个在相对于所述多个结合垫片的预定部位伸出的凸起;以及
多个结合部分连接在所述多个结合块与所述多个结合垫片之间和所述多个凸起与所述第二芯片的相邻的所述多个凹部之间的至少一种之间;
其中所述多个凹部和所述多个凸起中的至少一方包括倾斜壁,在所述结合部分进行软熔过程中用于捕获和引导所述多个凹部和所述多个凸起中的另一方,使得所述第一芯片相对所述第二芯片对齐。
2.如权利要求1所述的装置,其特征在于,所述多个凸起还包括多个圆锥形件和角锥形件中的一种。
3.如权利要求1所述的装置,其特征在于,所述多个凹部还包括多个圆锥形、角锥形和弯曲形凹部的一种。
4.如权利要求1所述的装置,其特征在于,所述多个凸起还包括所述多个结合部分的至少一部分。
5.如权利要求1所述的装置,其特征在于,还包括夹在所述多个凸起与所述第二芯片的相邻的所述多个凹部之间的湿润材料。
6.如权利要求1所述的方法,其特征在于,在所述软熔过程中还对所述第一和第二芯片施加振动波,以辅助所述多个凸起相对所述多个凹部移动。
7.如权利要求6所述的方法,其特征在于,所述振动波进一步由声波和超声波之一构成。
8.一种互连一对芯片的方法,该方法包括如下的步骤:
提供一第一芯片;
在所述第一芯片的预选定部位形成多个凹部;
提供一第二芯片;
在所述第二芯片的相对于所述多个凹部的预选定部位形成多个凸起;
将所述多个凸起靠近所述多个凹部安置;以及
对所述第一和第二芯片施加振动波,使所述第一芯片相对所述第二芯片移动,直到所述多个凸起进入所述多个凹部中。
9.如权利要求8所述的方法,其特征在于,所述振动波进一步由声波和超声波之一构成。
10.如权利要求8所述的方法,其特征在于,选择所述振动波的频率和振幅与所述第一和第二芯片的几何形状匹配。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00400283A EP1122567A1 (en) | 2000-02-02 | 2000-02-02 | Passive alignement using slanted wall pedestal |
EP00400283.8 | 2000-02-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1397092A true CN1397092A (zh) | 2003-02-12 |
Family
ID=8173528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN01804479A Pending CN1397092A (zh) | 2000-02-02 | 2001-01-11 | 用倾斜壁基座进行的被动对齐 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6643434B2 (zh) |
EP (1) | EP1122567A1 (zh) |
JP (1) | JP2003523085A (zh) |
CN (1) | CN1397092A (zh) |
AU (1) | AU2001230901A1 (zh) |
CA (1) | CA2399031A1 (zh) |
TW (1) | TW584946B (zh) |
WO (1) | WO2001059838A1 (zh) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102142402A (zh) * | 2010-02-02 | 2011-08-03 | 力成科技股份有限公司 | 维持焊接定位的覆晶封装构造 |
CN102403296A (zh) * | 2010-09-13 | 2012-04-04 | 英飞凌科技股份有限公司 | 半导体模块及其制造方法 |
CN104040398A (zh) * | 2012-01-31 | 2014-09-10 | 惠普发展公司,有限责任合伙企业 | 应用于光电学中的装置 |
CN105263262A (zh) * | 2015-11-10 | 2016-01-20 | 武汉华星光电技术有限公司 | 一种背光fpc金手指结构 |
CN104037142B (zh) * | 2013-03-06 | 2017-04-12 | 台湾积体电路制造股份有限公司 | 封装对准结构及其形成方法 |
CN106816417A (zh) * | 2017-01-13 | 2017-06-09 | 南京大学 | 一种高密度封装及其制造方法 |
CN109585390A (zh) * | 2017-09-29 | 2019-04-05 | 三星电子株式会社 | 半导体封装件 |
CN110676242A (zh) * | 2018-07-03 | 2020-01-10 | 三星电子株式会社 | 半导体封装件及其制造方法 |
CN111919154A (zh) * | 2018-03-20 | 2020-11-10 | 国立研究开发法人产业技术综合研究所 | 光连接器以及搭载其的机器 |
CN112378934A (zh) * | 2021-01-15 | 2021-02-19 | 同源微(北京)半导体技术有限公司 | 光学芯片、探测器以及制作方法 |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6546172B2 (en) | 2001-02-20 | 2003-04-08 | Avanti Optics Corporation | Optical device |
US6956999B2 (en) * | 2001-02-20 | 2005-10-18 | Cyberoptics Corporation | Optical device |
US20040212802A1 (en) * | 2001-02-20 | 2004-10-28 | Case Steven K. | Optical device with alignment compensation |
US6546173B2 (en) * | 2001-02-20 | 2003-04-08 | Avanti Optics Corporation | Optical module |
GB2379995B (en) * | 2001-09-21 | 2005-02-02 | Kamelian Ltd | An optical coupling |
US8286046B2 (en) | 2001-09-28 | 2012-10-09 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
US6696320B2 (en) * | 2001-09-30 | 2004-02-24 | Intel Corporation | Low profile stacked multi-chip package and method of forming same |
US20040264870A1 (en) * | 2002-08-20 | 2004-12-30 | Skunes Timothy A. | Optical alignment mount with height adjustment |
US8063650B2 (en) | 2002-11-27 | 2011-11-22 | Rambus Inc. | Testing fuse configurations in semiconductor devices |
US6756305B1 (en) * | 2003-04-01 | 2004-06-29 | Xilinx, Inc. | Stacked dice bonded with aluminum posts |
WO2005001933A2 (de) * | 2003-06-28 | 2005-01-06 | Infineon Technologies Ag | Multichip-halbleiterbaustein und verfahren zu seiner herstellung |
EP1765724B1 (en) | 2004-07-08 | 2013-12-18 | International Business Machines Corporation | Method for improving alignment precision of parts in mems |
JP2006156544A (ja) * | 2004-11-26 | 2006-06-15 | Denso Corp | 基板の実装構造およびその実装方法 |
US7518251B2 (en) * | 2004-12-03 | 2009-04-14 | General Electric Company | Stacked electronics for sensors |
US7393719B2 (en) * | 2005-04-19 | 2008-07-01 | Texas Instruments Incorporated | Increased stand-off height integrated circuit assemblies, systems, and methods |
US8957511B2 (en) * | 2005-08-22 | 2015-02-17 | Madhukar B. Vora | Apparatus and methods for high-density chip connectivity |
US7745301B2 (en) * | 2005-08-22 | 2010-06-29 | Terapede, Llc | Methods and apparatus for high-density chip connectivity |
US7701045B2 (en) | 2006-04-11 | 2010-04-20 | Rambus Inc. | Point-to-point connection topology for stacked devices |
US9899312B2 (en) * | 2006-04-13 | 2018-02-20 | Rambus Inc. | Isolating electric paths in semiconductor device packages |
US9250399B2 (en) * | 2006-08-31 | 2016-02-02 | Optogig, Inc. | High density active modular optoelectronic device for use with push-release mechanism and method for using same |
US7824111B2 (en) * | 2006-10-27 | 2010-11-02 | Fujitsu Limited | Optical module |
US7977778B2 (en) * | 2007-05-04 | 2011-07-12 | Stats Chippac Ltd. | Integrated circuit package system with interference-fit feature |
DE102007053849A1 (de) * | 2007-09-28 | 2009-04-02 | Osram Opto Semiconductors Gmbh | Anordnung umfassend ein optoelektronisches Bauelement |
US7768847B2 (en) | 2008-04-09 | 2010-08-03 | Rambus Inc. | Programmable memory repair scheme |
JP4754613B2 (ja) * | 2008-11-27 | 2011-08-24 | 日東電工株式会社 | 光電気混載基板およびその製造方法 |
CA2755376C (en) * | 2009-03-17 | 2014-09-09 | Shinya Watanabe | Optical waveguide device and method of manufacturing thereof |
US11181688B2 (en) | 2009-10-13 | 2021-11-23 | Skorpios Technologies, Inc. | Integration of an unprocessed, direct-bandgap chip into a silicon photonic device |
US9316785B2 (en) | 2013-10-09 | 2016-04-19 | Skorpios Technologies, Inc. | Integration of an unprocessed, direct-bandgap chip into a silicon photonic device |
US9923105B2 (en) | 2013-10-09 | 2018-03-20 | Skorpios Technologies, Inc. | Processing of a direct-bandgap chip after bonding to a silicon photonic device |
US8115319B2 (en) * | 2010-03-04 | 2012-02-14 | Powertech Technology Inc. | Flip chip package maintaining alignment during soldering |
US8265436B2 (en) * | 2010-05-12 | 2012-09-11 | Industrial Technology Research Institute | Bonding system for optical alignment |
JP2012145910A (ja) * | 2010-12-24 | 2012-08-02 | Mitsumi Electric Co Ltd | 構造体 |
JP5608125B2 (ja) * | 2011-03-29 | 2014-10-15 | 日東電工株式会社 | 光電気混載基板およびその製法 |
WO2013025338A1 (en) | 2011-08-17 | 2013-02-21 | Rambus Inc. | Multi-chip package and interposer with signal line compression |
US9977188B2 (en) | 2011-08-30 | 2018-05-22 | Skorpios Technologies, Inc. | Integrated photonics mode expander |
WO2013033628A1 (en) | 2011-09-01 | 2013-03-07 | Rambus Inc. | Testing through-silicon-vias |
WO2013099415A1 (ja) * | 2011-12-26 | 2013-07-04 | 株式会社フジクラ | 光モジュール |
TWI455264B (zh) * | 2012-02-04 | 2014-10-01 | Lextar Electronics Corp | 晶片接合結構及晶片接合的方法 |
JP5869686B2 (ja) * | 2012-09-27 | 2016-02-24 | 株式会社フジクラ | 光モジュール |
JP2014071228A (ja) * | 2012-09-28 | 2014-04-21 | Kyocera Corp | 光配線基板および光伝送モジュール |
US9217836B2 (en) * | 2012-10-23 | 2015-12-22 | Kotura, Inc. | Edge coupling of optical devices |
US8873903B2 (en) * | 2012-11-28 | 2014-10-28 | Seagate Technology Llc | Method and apparatus for aligning a laser to a waveguide |
JP6070168B2 (ja) * | 2012-12-24 | 2017-02-01 | 株式会社デンソー | 回路基板 |
EP2948975A4 (en) * | 2013-01-28 | 2016-12-21 | Hewlett Packard Entpr Dev Lp | ROUNDING ALIGNMENT PIN FOR BASIC MATERIAL |
US9773724B2 (en) * | 2013-01-29 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages |
JP6160128B2 (ja) * | 2013-03-05 | 2017-07-12 | 日本電気株式会社 | 3次元積層半導体装置 |
US9055701B2 (en) | 2013-03-13 | 2015-06-09 | International Business Machines Corporation | Method and system for improving alignment precision of parts in MEMS |
WO2014176561A1 (en) * | 2013-04-25 | 2014-10-30 | Skorpios Technologies, Inc. | Method and system for height registration during chip bonding |
US9679868B2 (en) | 2013-06-19 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ball height control in bonding process |
JP6009998B2 (ja) * | 2013-06-25 | 2016-10-19 | 日本電信電話株式会社 | 位置合わせ構造および方法 |
US20150153524A1 (en) * | 2013-12-03 | 2015-06-04 | Forelux Inc. | Integrated optoelectronic module |
JP6334945B2 (ja) * | 2014-02-17 | 2018-05-30 | スタンレー電気株式会社 | 半導体発光装置、半導体発光素子、及び、半導体発光装置の製造方法 |
US9664855B2 (en) | 2014-03-07 | 2017-05-30 | Skorpios Technologies, Inc. | Wide shoulder, high order mode filter for thick-silicon waveguides |
EP3149522A4 (en) | 2014-05-27 | 2018-02-21 | Skorpios Technologies, Inc. | Waveguide mode expander using amorphous silicon |
US10319693B2 (en) * | 2014-06-16 | 2019-06-11 | Skorpios Technologies, Inc. | Micro-pillar assisted semiconductor bonding |
US9230918B1 (en) * | 2014-07-02 | 2016-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package structure, alignment structure, and alignment method |
US9606308B2 (en) | 2015-02-27 | 2017-03-28 | International Business Machines Corporation | Three dimensional self-alignment of flip chip assembly using solder surface tension during solder reflow |
US9829631B2 (en) | 2015-04-20 | 2017-11-28 | Skorpios Technologies, Inc. | Vertical output couplers for photonic devices |
US10168497B2 (en) | 2015-06-15 | 2019-01-01 | Rwth Aachen | Self-alignment for apparatus comprising photonic device |
US11495560B2 (en) * | 2015-08-10 | 2022-11-08 | X Display Company Technology Limited | Chiplets with connection posts |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US9704822B2 (en) * | 2015-11-10 | 2017-07-11 | International Business Machines Corporation | Bonding substrates using solder surface tension during solder reflow for three dimensional self-alignment of substrates |
JP2018124394A (ja) * | 2017-01-31 | 2018-08-09 | 国立大学法人福井大学 | 光ビーム投影装置 |
JP6977267B2 (ja) * | 2017-02-02 | 2021-12-08 | 富士通オプティカルコンポーネンツ株式会社 | 光デバイス及び光デバイスの製造方法 |
US10649148B2 (en) | 2017-10-25 | 2020-05-12 | Skorpios Technologies, Inc. | Multistage spot size converter in silicon photonics |
DE102018103431A1 (de) * | 2018-02-15 | 2019-08-22 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Verbindung zwischen Bauteilen und Bauelement aus Bauteilen |
DE102018125901A1 (de) | 2018-10-18 | 2020-04-23 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines elektronischen Bauelements, Halbleiterchip, elektronisches Bauelement und Verfahren zur Herstellung eines Halbleiterchips |
US11171464B1 (en) | 2018-12-14 | 2021-11-09 | Apple Inc. | Laser integration techniques |
US11360263B2 (en) | 2019-01-31 | 2022-06-14 | Skorpios Technologies. Inc. | Self-aligned spot size converter |
EP4100776A1 (en) * | 2020-02-03 | 2022-12-14 | Senko Advanced Components Inc. | Elastic averaging coupling |
CN113131713B (zh) * | 2021-05-17 | 2022-06-07 | 苏州昀冢电子科技股份有限公司 | 音圈马达的基座及其组合 |
EP4316224A1 (en) * | 2021-09-17 | 2024-02-07 | IQM Finland Oy | Chip fabrication method and product |
US20230102967A1 (en) * | 2021-09-24 | 2023-03-30 | Apple Inc. | Chip-to-Chip Optical Coupling for Photonic Integrated Circuits |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4542397A (en) * | 1984-04-12 | 1985-09-17 | Xerox Corporation | Self aligning small scale integrated circuit semiconductor chips to form large area arrays |
EP0312217A1 (en) * | 1987-09-30 | 1989-04-19 | AT&T Corp. | Integrated circuit chip assembly |
US4949148A (en) * | 1989-01-11 | 1990-08-14 | Bartelink Dirk J | Self-aligning integrated circuit assembly |
CA2034703A1 (en) * | 1990-01-23 | 1991-07-24 | Masanori Nishiguchi | Substrate for packaging a semiconductor device |
US5182782A (en) | 1990-07-11 | 1993-01-26 | Gte Laboratories Incorporated | Waferboard structure and method of fabricating |
US5077878A (en) | 1990-07-11 | 1992-01-07 | Gte Laboratories Incorporated | Method and device for passive alignment of diode lasers and optical fibers |
US5205032A (en) * | 1990-09-28 | 1993-04-27 | Kabushiki Kaisha Toshiba | Electronic parts mounting apparatus |
DE69331876T2 (de) * | 1992-01-28 | 2002-11-28 | British Telecommunications P.L.C., London | Ausrichtung von integrierten optischen Komponenten |
JPH05251831A (ja) * | 1992-03-05 | 1993-09-28 | Sony Corp | マルチビーム半導体レーザ装置とその組立て方法 |
FR2694841B1 (fr) * | 1992-08-14 | 1994-09-09 | Commissariat Energie Atomique | Procédé d'hybridation et de positionnement d'un composant opto-électronique et application de ce procédé au positionnement de ce composant par rapport à un guide optique intégré. |
US5499312A (en) | 1993-11-09 | 1996-03-12 | Hewlett-Packard Company | Passive alignment and packaging of optoelectronic components to optical waveguides using flip-chip bonding technology |
JP3658426B2 (ja) * | 1995-01-23 | 2005-06-08 | 株式会社日立製作所 | 光半導体装置 |
US5801452A (en) * | 1996-10-25 | 1998-09-01 | Micron Technology, Inc. | Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member |
DE19644758A1 (de) | 1996-10-29 | 1998-04-30 | Sel Alcatel Ag | Zentrieranordnung zum Positionieren von mikrostrukturierten Körpern |
SE9604678L (sv) * | 1996-12-19 | 1998-06-20 | Ericsson Telefon Ab L M | Bulor i spår för elastisk lokalisering |
US6198172B1 (en) * | 1997-02-20 | 2001-03-06 | Micron Technology, Inc. | Semiconductor chip package |
US5998868A (en) * | 1998-02-04 | 1999-12-07 | International Business Machines Corporation | Very dense chip package |
US6114221A (en) * | 1998-03-16 | 2000-09-05 | International Business Machines Corporation | Method and apparatus for interconnecting multiple circuit chips |
EP1178340A1 (en) * | 2000-08-02 | 2002-02-06 | Corning Incorporated | Vertically-tolerant alignment using slanted wall pedestal |
-
2000
- 2000-02-02 EP EP00400283A patent/EP1122567A1/en not_active Withdrawn
-
2001
- 2001-01-11 AU AU2001230901A patent/AU2001230901A1/en not_active Abandoned
- 2001-01-11 CA CA002399031A patent/CA2399031A1/en not_active Abandoned
- 2001-01-11 WO PCT/US2001/000893 patent/WO2001059838A1/en active Application Filing
- 2001-01-11 CN CN01804479A patent/CN1397092A/zh active Pending
- 2001-01-11 JP JP2001559062A patent/JP2003523085A/ja not_active Withdrawn
- 2001-01-17 US US09/764,839 patent/US6643434B2/en not_active Expired - Fee Related
- 2001-01-21 TW TW090101733A patent/TW584946B/zh not_active IP Right Cessation
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102142402A (zh) * | 2010-02-02 | 2011-08-03 | 力成科技股份有限公司 | 维持焊接定位的覆晶封装构造 |
CN102403296A (zh) * | 2010-09-13 | 2012-04-04 | 英飞凌科技股份有限公司 | 半导体模块及其制造方法 |
CN104040398A (zh) * | 2012-01-31 | 2014-09-10 | 惠普发展公司,有限责任合伙企业 | 应用于光电学中的装置 |
CN104037142B (zh) * | 2013-03-06 | 2017-04-12 | 台湾积体电路制造股份有限公司 | 封装对准结构及其形成方法 |
US9627325B2 (en) | 2013-03-06 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package alignment structure and method of forming same |
CN105263262A (zh) * | 2015-11-10 | 2016-01-20 | 武汉华星光电技术有限公司 | 一种背光fpc金手指结构 |
CN106816417A (zh) * | 2017-01-13 | 2017-06-09 | 南京大学 | 一种高密度封装及其制造方法 |
CN106816417B (zh) * | 2017-01-13 | 2019-02-12 | 南京大学 | 一种高密度封装及其制造方法 |
CN109585390A (zh) * | 2017-09-29 | 2019-04-05 | 三星电子株式会社 | 半导体封装件 |
CN109585390B (zh) * | 2017-09-29 | 2024-04-19 | 三星电子株式会社 | 半导体封装件 |
CN111919154A (zh) * | 2018-03-20 | 2020-11-10 | 国立研究开发法人产业技术综合研究所 | 光连接器以及搭载其的机器 |
CN111919154B (zh) * | 2018-03-20 | 2022-11-01 | 国立研究开发法人产业技术综合研究所 | 光连接器以及搭载其的机器 |
TWI800627B (zh) * | 2018-03-20 | 2023-05-01 | 國立研究開發法人產業技術總合研究所 | 光連接器及搭載光連接器之機器 |
TWI841158B (zh) * | 2018-03-20 | 2024-05-01 | 國立研究開發法人產業技術總合研究所 | 光連接器及搭載光連接器之機器 |
CN110676242A (zh) * | 2018-07-03 | 2020-01-10 | 三星电子株式会社 | 半导体封装件及其制造方法 |
CN112378934A (zh) * | 2021-01-15 | 2021-02-19 | 同源微(北京)半导体技术有限公司 | 光学芯片、探测器以及制作方法 |
CN112378934B (zh) * | 2021-01-15 | 2021-09-10 | 同源微(北京)半导体技术有限公司 | 光学芯片、探测器以及制作方法 |
Also Published As
Publication number | Publication date |
---|---|
AU2001230901A1 (en) | 2001-08-20 |
CA2399031A1 (en) | 2001-08-16 |
US20010010743A1 (en) | 2001-08-02 |
WO2001059838A1 (en) | 2001-08-16 |
US6643434B2 (en) | 2003-11-04 |
TW584946B (en) | 2004-04-21 |
EP1122567A1 (en) | 2001-08-08 |
JP2003523085A (ja) | 2003-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1397092A (zh) | 用倾斜壁基座进行的被动对齐 | |
CN1187633C (zh) | 具有芯片级精确对位的光学器件 | |
US6995469B2 (en) | Semiconductor apparatus and fabricating method for the same | |
US7239767B2 (en) | Packaging apparatus for optical interconnection on optical printed circuit board | |
US5703406A (en) | Interconnection structure for attaching a semiconductor device to a substrate | |
JP2006237369A (ja) | 電子装置及びスタンドオフ部材及び電子装置の製造方法 | |
Nah et al. | Flip chip assembly with sub-micron 3D re-alignment via solder surface tension | |
CN1161835C (zh) | 半导体器件及其制造方法 | |
US6695492B2 (en) | Optical module and production method therefor | |
US20090065678A1 (en) | Systems and methods for a tilted optical receiver assembly | |
JP2002503355A (ja) | 光学構成エレメントの心合わせ | |
EP1168011A1 (en) | Hybrid alignment of optical components using calibrated substrates | |
JP3068762B2 (ja) | 対向する被加工物間の相互位置決め方法 | |
DE10058949A1 (de) | Hochgeschwindigkeits-Infrarot-Sende/Empfangs-Vorrichtung mit hohem Wirkungsgrad und niedrigen Kosten | |
JP2014027243A (ja) | 自重を用いる半田ボール実装装置、これを含む半田ボール実装システム、及びこれを用いる半田ボール実装方法 | |
JPH05251454A (ja) | はんだ付けされた結合部を形成するための方法 | |
JP2004006879A (ja) | 光モジュール光軸整列方法 | |
JPH11214431A (ja) | 電子部品及びその製造方法 | |
JPH09199540A (ja) | 半導体装置及び実装構造体及びその製造方法及び実装構造体検査方法及びその装置 | |
Tsunetsugu et al. | Micro-alignment technique using 26-/spl mu/m diameter microsolder bumps and its shear strength | |
KR100317397B1 (ko) | 자유공간 광연결 모듈 구조 | |
JP2004264382A (ja) | 光導波路基板及びその製造方法、光電気複合実装配線基板及びその製造方法 | |
Nieweglowski et al. | Novel optical transmitter and receiver for parallel optical interconnects on PCB-level | |
JP2018105925A (ja) | 半導体装置およびその製造方法 | |
CN1508582B (zh) | 光学装置之制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |