CN104716121A - 包含多个半导体芯片和层压板的半导体器件 - Google Patents

包含多个半导体芯片和层压板的半导体器件 Download PDF

Info

Publication number
CN104716121A
CN104716121A CN201410754725.XA CN201410754725A CN104716121A CN 104716121 A CN104716121 A CN 104716121A CN 201410754725 A CN201410754725 A CN 201410754725A CN 104716121 A CN104716121 A CN 104716121A
Authority
CN
China
Prior art keywords
semiconductor chip
semiconductor device
laminated sheet
type surface
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410754725.XA
Other languages
English (en)
Inventor
A.凯斯勒
P.帕尔姆
T.沙尔夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Publication of CN104716121A publication Critical patent/CN104716121A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48855—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48863—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48864—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20641—Length ranges larger or equal to 100 microns less than 200 microns

Abstract

本发明涉及包含多个半导体芯片和层压板的半导体器件。一种半导体器件包含层压板、至少部分嵌入在层压板中的第一半导体芯片、安装在层压板的第一主表面上的第二半导体芯片以及布置在层压板的第一主表面上的第一电接触。该第二半导体芯片被电耦合到该第一电接触。

Description

包含多个半导体芯片和层压板的半导体器件
技术领域
本公开涉及包含多个半导体芯片和层压板（laminate）的半导体器件。此外，本公开涉及用于制造这样的半导体器件的方法。
背景技术
半导体器件可以包含可以具有不同类型的一个或多个半导体芯片。此外，半导体器件的设计可以基于层压板。必须不断地改进半导体器件和用于制造半导体器件的方法。改进半导体器件的性能和质量可能是所希望的。特别地，提高集成度并且改进半导体器件的电性能可能是所希望的。
附图说明
附图被包含来提供对方面的进ー步理解并且被合并在本说明书中并且构成本说明书的一部分。附图图示方面并且与描述一起用来解释方面的原理。将容易认识到其它的方面和方面的许多预期优点，因为通过参考下面的详细描述它们变得更好理解。附图中的元件不必相对彼此成比例。同样的参考数字可以指定对应类似的部分。
图1示意性图示依照本公开的半导体器件的横截面视图。
图2示意性图示依照本公开的半导体封装的横截面视图。
图3示意性图示依照本公开的半导体器件的横截面视图。
图4示意性图示依照本公开的半导体器件的横截面视图。
图5示意性图示依照本公开的半导体器件的横截面视图。
图6示意性图示依照本公开的半导体器件的横截面视图。
图7示意性图示依照本公开的半导体器件的横截面视图。
图8示意性图示依照本公开的半导体器件的横截面视图。
图9示意性图示依照本公开的半导体器件的横截面视图。
图10A至10D示意性图示用于依照本公开来制造半导体器件的方法的横截面视图。
图11图示半桥电路的示意图。
具体实施方式
在下面的详细描述中参考附图，附图形成本文的部分并且在附图中通过图示的方式示出了在其中可以实践本公开的特定方面。在这点上，可以参考正被描述的附图的定向来使用方向术语诸如“顶”、“底”、“前”、“后”等。因为可以以多种不同的定向将所描述的器件的部件定位，所以方向术语可以是为了图示的目的使用的而绝非加以限制。在不脱离本公开的范围的情况下，可以利用其它方面并且可以做出结构的或逻辑的改变。因此，下面的详细描述不要以限制的意义理解，并且本公开的范围由所附权利要求书来限定。
如在本说明书中采用的，术语“连接”、“耦合”、“电连接”和/或“电耦合”不意图必定意味着元件必须直接连接或耦合在一起。在“连接”、“耦合”、“电连接”或“电耦合”的元件之间可以提供介入元件。
本文描述半导体器件和用于制造半导体器件的方法。与所描述的半导体器件有关而做出的注释也可以适用于对应的方法，并且反之亦然。例如，如果描述了半导体器件的特定部件，则用于制造半导体器件的对应的方法可以包含以合适方式来提供该部件的动作，即使在附图中没有明确描述或图示这样的动作。此外，本文描述的各种示例性方面的特征可以彼此结合，除非特别地另外指明。在本说明书中，术语“半导体器件”和“半导体封装”可以是可交换使用的。特别地，半导体封装可以是包含密封材料的半导体器件，该密封材料可以至少部分密封该半导体器件的一个或多个部件。
本文描述的半导体器件可以包含一个或多个半导体芯片。半导体芯片可以具有不同类型并且可以通过不同的技术被制造。例如，半导体芯片可以包含集成电路、电光电路或电机电路、无源电路等。集成电路可以被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储器电路、集成无源电路、微机电系统等。不需要从特定的半导体材料例如Si、SiC、SiGe、GaAs中制造半导体芯片，而且半导体芯片可以含有无机的和/或有机的材料，其不是半导体诸如例如绝缘体、塑料或金属。而且，半导体芯片可以是封装的或未封装的。
半导体芯片可以包含一个或多个有源侧面（或有源表面）。半导体芯片的有源侧面可以被定义为含有微电子结构或半导体结构的半导体芯片的物理部分。例如，有源侧面可以包含至少一个半导体结构，特别是二极管、晶体管、熔丝、电阻器、电容器等中的至少一个。
特别地，半导体芯片可以包含一个或多个功率半导体。半导体芯片（或功率半导体芯片）可以具有垂直的结构，即该半导体芯片可以被制作使得电流可以以与半导体芯片的主面正交的方向流动。具有垂直结构的半导体芯片可以在它的两个主面之上或在它的两个主面上（即在它的顶侧面和底侧面之上或在它的顶侧面和底侧面上）具有电极。特别地，功率半导体芯片可以具有垂直的结构并且可以在两个主面之上或在两个主面上具有负载电极。例如，垂直功率半导体芯片可以被配置为二极管、功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极型晶体管）、JFET（结型栅场效应晶体管）、超级结器件、功率双极型晶体管等。功率MOSFET的源电极和栅电极可以被布置在一面之上或在一面上，而功率MOSFET的漏电极可以被布置在另一面之上或在另一面上。本文描述的半导体器件可以进一步包含半导体芯片或集成电路以控制和/或驱动功率半导体芯片的集成电路。与功率半导体芯片相比，这样的逻辑芯片可以是基于更复杂的架构和设计。
本文描述的半导体器件可以包含具有低引脚数（LPC）的一个或多个半导体芯片。例如，功率半导体芯片如例如功率MOSFET、IGBT、JFET等可以具有低引脚数。特别地，具有低引脚数的芯片可以至少部分被嵌入在半导体器件的层压板中。本文描述的半导体器件可以进一步包含具有高引脚数（HPC）的一个或多个半导体芯片。具有高引脚数的芯片可以特别地至少部分被嵌入在层压板中或可以被布置在半导体器件的层压板的外面，例如在层压板的主表面之上或在层压板的主表面上。例如，逻辑芯片或存储器芯片可以具有高引脚数。通常，具有高引脚数的半导体芯片可以包含比具有低引脚数的半导体芯片更多的引脚或电接触。不同引脚数的半导体芯片可以被配置以在半导体器件的操作期间彼此协作或通信。例如，具有高引脚数的半导体芯片可以被配置以控制和/或驱动具有低引脚数的半导体芯片。
半导体芯片可以具有电接触，例如，形式为可以允许与被包含在半导体芯片中的集成电路达成电接触的接触焊盘（或接触元件或接触端子或接触电极）。对于功率半导体芯片的情况，接触焊盘可以对应于栅电极、源电极或漏电极。接触焊盘可以包含一个或多个金属层，该一个或多个金属层可以被施加到半导体材料。可以以任何所希望的几何形状和任何所希望的材料成分来制造该金属层。任何所希望的金属或金属合金，例如铝、钛、金、银、铜、钯、铂、镍、铬、镍钒等中的至少一种，可以被用作为该材料。金属层不需要是同质的或仅从一种材料中被制造，即金属层中含有的各种成分和浓度的材料可以是可能的。
本文描述的半导体器件可以包含层压板。该层压板不需要是同质的或仅从一种材料中被制造，即层压板中含有的各种成分和浓度的材料可以是可能的。例如，层压板可以包含环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、填充或未填充的热塑性聚合物材料、填充或未填充的热固性聚合物材料、填充或未填充的聚合物混合物等中的至少一种。层压板可以被配置来嵌入电子部件例如一个或多个半导体芯片。此外，层压板可以被配置来充当载体，在载体之上或在载体上可以布置或安装电子部件，例如半导体芯片、无源电子部件、有源电子部件、微机电系统（MEMS）等中的至少一个。可以采用各种技术用于制造层压板并且将像半导体芯片的部件嵌入在该层压板中。例如，可以使用压缩成型、注入成型、粉末成型、液体成型、层压等中的至少一种。
本文描述的半导体器件可以包含密封材料，该密封材料可以至少部分覆盖半导体器件中的一个或多个部件。密封材料可以是电绝缘的并且可以形成密封基体。密封材料可以包含环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、填充或未填充的热塑性聚合物材料、填充或未填充的热固性聚合物材料、填充或未填充的聚合物混合物、热固材料、成型化合物、顶部密封（glob-top）材料、层压材料等中的至少一种。可以使用各种技术（例如压缩成型、注入成型、粉末成型、液体成型、层压等中的至少一种）利用密封材料来密封半导体器件的部件。
本文描述的半导体器件可以包含一个或多个无源电子部件。例如，可以将无源电子部件集成在半导体材料中。可以采用多互连金属层用于实施无源电子部件。无源电子部件可以包含任何种类的电阻器、电容器、像电感器或线圈的感应部件、天线等。可以使用任何适当的技术用于制造无源电子部件。
本文描述的半导体器件可以包含一个或多个有源电子部件。例如，可以基于任意适当的制造技术将有源电子部件集成在半导体材料中。有源电子部件可以包含任何种类的二极管、晶体管、数字或模拟电路、光电子部件、MEMS等。
本文描述的半导体器件可以基于表面安装技术并且因此可以表示表面安装器件，例如球栅阵列（BGA）、芯片级封装（CSP）、四方扁平无引线（QFN）封装、平面栅格阵列（LGA）等。表面安装器件可以包含至少一个安装表面，该安装表面可以用于将半导体器件安装到另一个部件（例如，印刷电路板（PCB））上。外部接触元件以及特别是外部接触表面可以被设置在安装表面之上或在安装表面上以支持半导体器件的表面安装。外部接触元件可以允许将半导体器件电耦合到部件，半导体器件要被安装在该部件之上或在该部件上。焊料淀积物诸如焊料球、焊料凸块、焊料焊盘、可焊接焊盘等或其它适当的连接元件可以被用来建立半导体器件与部件之间的电连接和/或机械连接，半导体器件被安装在该部件之上或在该部件上。
本文描述的半导体器件可以包含一个或多个再分布层。例如，再分布层可以被布置在层压板的至少一个表面之上，该层压板也可以被包含在半导体器件中。在进一步的示例中，可以在层压板中至少部分布置再分布层。再分布层可以包含一个或多个金属层，该一个或多个金属层可以具有导体线或导体面的形状并且可以被电耦合到半导体器件的半导体芯片。可以采用金属层作为接线层以从半导体器件外面与半导体芯片达成电接触和/或与半导体器件中含有的部件和/或其它半导体芯片达成电接触。金属层可以将半导体芯片的接触焊盘耦合到外部的接触焊盘。在进一步的示例中，金属层可以提供经过层压板从层压板的一个表面到层压板的另一个表面的电连接。可以以任何所希望的几何形状和任何所希望的材料成分来制造金属层。例如，金属层可以包含铝、镍、钯、银、锡、金、铜、对应的金属合金等或其组合中的至少一种。金属层可以包含由这些材料制成的一个或多个单金属层。替代地或附加地，金属层可以包含由该材料制成的一个或多个多层，例如铜/镍/金。可以在电绝缘层之上或在电绝缘层之下或在电绝缘层之间布置金属层。
本文描述的半导体器件可以包含导电元件，该导电元件可以被配置来在半导体器件的部件之间提供电连接。在一个示例中，可以在半导体芯片与电接触之间提供电连接，半导体芯片和电接触两者都可以被布置在层压板之上或在层压板上。提供这样的电连接的适当元件可以是接合接线、焊料凸块、扩散焊料接合、导电胶等中的至少一种。可以用任意合适的材料来制造导电元件。例如，所采用的接合接线可以包含Cu、Au、Al、Pd涂覆的Cu、Ag等中的至少一种。例如，能够形成扩散焊料接合的焊料材料可以包含Sn、SnAg、SnAu、In、InAg、InAu、SnAgCu、PbSn、PbInAg等中的一个或多个。在进一步的示例中，可以在至少部分被嵌入在层压板中的半导体芯片与在层压板之上或在层压板上布置的电接触之间提供电连接。例如，可以由一个或多个微通孔来提供这样的电连接，该一个或多个微通孔可以由任意合适的导电材料例如金属或金属合金制成。
图1示意性图示依照本公开的半导体器件100的横截面视图。半导体器件100可以包含层压板1和第一半导体芯片2，第一半导体芯片2可以至少部分被嵌入在层压板1中。在图1的示例中，第一半导体芯片2被示例性嵌入在层压板1的第一主表面4处。然而，在其它的示例中，第一半导体芯片2也可以被嵌入在层压板1中的另一个任意的位置，例如在与第一主表面4相对的层压板1的主表面处。半导体器件100可以进一步包含第二半导体芯片3，第二半导体芯片3可以被安装在层压板1的第一主表面4之上或在层压板1的第一主表面4上。可以在层压板1的第一主表面4之上或在层压板1的第一主表面4上布置第一电接触5。可以将第二半导体芯片3电耦合到第一电接触5。在图1的示例中，第二半导体芯片3与第一电接触5之间的电耦合不被明确图示以便阐明电耦合可以具有任何合适类型。下面描述用于合适电耦合的示例。此外，在下面描述与图1的半导体器件100类似的更详细的半导体器件。
图2示意性图示依照本公开的半导体封装200的横截面视图。半导体封装200可以包含层压板1和第一半导体芯片2，第一半导体芯片2可以至少部分被嵌入在层压板1中。半导体封装200可以进一步包含第二半导体芯片3和电接触5，其中第二半导体芯片3和电接触5中的每个可以被布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上。可以将第二半导体芯片3电耦合到电接触5。由于上面所解释的原因，再次将电耦合的明确图示省略。半导体封装200可以进一步包含密封材料6，该密封材料6可以至少部分密封第二半导体芯片3、电接触5和层压板1。下面描述与图2的半导体封装200类似的更详细的半导体封装。
图3示意性图示依照本公开的半导体器件300的横截面视图。半导体器件300可以包含层压板1，该层压板1具有第一主表面4和与第一主表面4相对的第二主表面7。层压板1可以包含环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、填充或未填充的热塑性聚合物材料、填充或未填充的热固性聚合物材料、填充或未填充的聚合物混合物等中的至少一个。在与主表面4、7正交的方向上的层压板1的厚度可以处在从大约60μm（微米）到大约250μm（微米）的范围内。
第一半导体芯片2和第三半导体芯片8可以至少部分被嵌入在层压板1中。通常，半导体芯片2、8可以具有任意类型。特别地，半导体芯片2、8中的一个或两个可以包含功率半导体。例如，第一半导体芯片2、8中的每个可以是MOSFET芯片，该MOSFET芯片具有在相应的半导体芯片的主表面之上或在相应的半导体芯片的主表面上布置的栅电极和源电极以及在相应的半导体芯片的相对主表面之上或在相应的半导体芯片的相对主表面上布置的漏电极。包含栅电极和源电极的半导体芯片2、8的主表面可以被定义为半导体芯片2、8的有源侧面。在一个示例中，第一半导体芯片2的有源侧面可以面向朝着层压板1的第二主表面7的方向，而第三半导体芯片8的有源侧面可以面向朝着层压板1的第一主表面4的方向。在进一步的示例中，两个半导体芯片2、8的有源侧面可以面向相同的方向，例如朝着层压板1的第一主表面4或朝着层压板1的第二主表面7。
第一半导体器件300可以包含第一接线层（或第一导电层）9，其可以被布置在层压板1的第二主表面7之上或在层压板1的第二主表面7上。在与主表面4、7正交的方向上的第一接线层9的厚度可以处在从大约5μm（微米）到大约50μm（微米）的范围内。第一接线层9可以由任何适当的导电材料制成并且可以依赖于针对半导体器件300的所希望的操作可能需要的电连接被结构化。例如，第三半导体芯片8的漏电极可以被电连接到第一接线层9的部分9A使得漏电极可以从层压板1外面经由第一接线层9的部分9A被接入。例如，接线层9的进一步部分9B可以向直通连接（through-connection）提供电连接，该直通连接可以从层压板1的第一主表面4延伸到层压板1的第二主表面7。第一接线层9的进一步部分可以被配置来给电连接提供第一半导体芯片2和/或第三半导体芯片8的进一步电接触。特别地，可以设计半导体器件300使得半导体芯片2、8的所有电接触可以从半导体器件300外面（或周界）被接入。特别地，第一接线层9可以被配置来支持表面安装焊接技术。那就是半导体器件300可以是表面安装器件并且第一接线层9的至少部分可以被配置来支持在另一个部件（未图示）例如印刷电路板（PCB）之上或在所述另一个部件上半导体器件300的表面安装。
半导体器件300可以包含第二接线层（或第二导电层）10，第二接线层10可以被布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上。在与主表面4、7正交的方向上的第二接线层10的厚度可以处在从大约5μm（微米）到大约50μm（微米）的范围内。第二接线层10可以依赖于针对半导体器件300的所希望的操作可能需要的电连接被结构化。例如，第二接线层10可以包含布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的电接触10A、10B。例如，电接触10A可以借助于例如微通孔11向布置在第三半导体芯片8的主表面之上或在第三半导体芯片8的主表面上的电极提供电连接。进一步微通孔可以给电接触提供第三半导体芯片8的进一步电接触。在一个示例中，电接触10B可以向直通连接提供电连接，该直通连接可以经过层压板1从层压板1的第一主表面4延伸到层压板1的第二主表面7。第二接线层10可以由任何适当的导电材料制成。特别地，第二接线层10的材料可以依赖于应当如何建立与第二接线层10的部分的电连接。在图3的示例中，第二接线层10可以特别被配置来支持接线接合工艺，其中第二接线层10的部分可以被电耦合到接合接线。
半导体器件300可以包含布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的第二半导体芯片3。通常，第二半导体芯片3可以具有任意类型。特别地，第二半导体芯片3可以被配置来控制和/或驱动嵌入在层压板1中的半导体芯片2、8中的一个或两个。在这种情况下，第二半导体芯片3可以是逻辑芯片或可以包含逻辑芯片。第二半导体芯片3可以经由第一接合接线12A被电连接到第二接线层10的部分10A。这样，第二半导体芯片3可以例如接入第三半导体芯片8的电极。此外，第二半导体芯片3可以经由第二接合接线10B被电连接到第二接线层10的部分10B。这样，第二半导体芯片3可以例如接入第一半导体芯片2的电极。
第二半导体芯片3可以包含比嵌入在层压板1中的每个半导体芯片2、8更复杂的电路。例如，第二半导体芯片3可以具有高引脚数，而半导体芯片2、8中的一个或两个可以具有低引脚数。此外，第一半导体芯片2的厚度t1和第三半导体芯片8的厚度t2中的每个可以小于第二半导体芯片3的厚度t3。例如，第一半导体芯片2的厚度t1和第三半导体芯片8的厚度t2可以小于大约120μm（微米）。例如，第二半导体芯片3的厚度t3可以大于大约100μm（微米）。厚度t1、t2、t3可以彼此不同，但也可以是相等的。
半导体器件300可以包含可以布置在层压板1的第一主表面4之上的密封材料6。密封材料6可以包含环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、热塑性聚合物材料、热固性聚合物材料、聚合物混合物、热固材料、成型化合物、顶部密封材料、层压材料等中的至少一种。在与主表面4、7正交的方向上的密封材料6的厚度可以处在从大约100μm（微米）到大约1000μm（微米）的范围内。密封材料6可以至少部分密封层压板1、第二接线层10、接合接线12A、12B、第二半导体芯片3中的至少一个。在图3的示例中，密封材料6可以覆盖在层压板1的第一主表面4之上布置的所有部件。密封的半导体器件300因此可以表示完整的系统级封装（system in package）或一个封装解决方案。
在一个示例中，半导体器件300可以被配置成操作为DC/DC转换器，该DC/DC转换器可以基于半桥电路。因为图3具有定性特性，所以它不必图示针对半桥电路的实际操作可能需要的所有电连接。然而，与图11相关地描述了半桥电路1100的示例性示意图，该半桥电路1100可以通过与图3中的一个半导体器件类似的半导体器件来实施。当使用图3的多芯片器件300作为半桥电路时，第一半导体芯片2可以包含低侧开关，并且第三半导体芯片8可以包含高侧开关。特别地，第一半导体芯片2的漏电极可以被电连接到第三半导体芯片8的源电极。
如已经提到的，图3具有定性特性，并且也可以在半导体器件300的基础上实施进一步电子功能性，该进一步电子功能性可以与包含半桥电路的DC/DC转换器不同。为了这个目的，附加的半导体芯片可以被包含在半导体器件300中。特别地，半导体器件300可以包含在层压板1中嵌入的任意数目的半导体芯片和布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的任意数目的半导体芯片。采用的半导体芯片和在半导体芯片和/或接线层9和10之间提供的关联的电连接的特定数目可以依赖于半导体器件300的所希望的功能性。进一步，可以不仅仅经由布置在层压板1的第一主表面7之上或在层压板1的第一主表面7上的第一接线层9来接触部件。例如，也可以从半导体器件300的侧表面来接入第一接线层9和第二接线层10中的每个。在图3的示例中，半导体器件300的侧表面基本上分别与层压板1的主表面4、7正交。
图4示意性图示依照本公开的半导体器件400的横截面视图。半导体器件400可以与图3的半导体器件300类似并且可以包含类似的部件。与图3相关而做出的所有注释因此也可以适用于图4的半导体器件400。
半导体器件400可以包含可以布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的电子部件13。例如，电子部件13可以包含无源电子部件、有源电子部件、微机电部件等中的至少一个。在图4的示例中，仅一个示例性电子部件13被图示。在进一步的示例中，半导体器件400可以包含任意数目的进一步电子部件，该进一步电子部件可以被布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上，其中采用的电子部件的布置和选择可以依赖于半导体器件400的所希望的操作。对于半导体器件400操作为DC/DC转换器的示例性情况，例如，电子部件13可以包含启动电容器（boot capacitor）。电子部件13可以被电耦合到半导体器件400的其它部件中的一个或多个。在图4的示例中，例如借助于一个或多个微通孔11可以将电子部件13耦合到第三半导体芯片8。此外，例如借助于第二接线层10可以将电子部件13耦合到第二半导体芯片3。与布置在层压板1的第一主表面4之上的进一步部件类似，通过密封材料6可以将电子部件13至少部分密封。
半导体器件400可以进一步包含一个或多个导电元件14A、14B，该导电元件14A、14B可以延伸经过密封材料6。在图4的示例中，两个导电元件14A、14B可以从层压板1的第一主表面4分别延伸到密封材料6的上表面15。例如，导电元件14A、14B可以是由金属或金属合金例如Cu制成的块，并且可以例如借助于焊接技术将导电元件14A、14B电耦合到第二接线层10。导电元件14A、14B的高度h1可以大于第二半导体芯片3和接合接线12A、12B的接线回路的高度h2。可以通过密封材料6将导电元件14A、14B至少部分密封。在图4的示例中，可以通过密封材料6将导电元件14A、14B除了它们的上表面以外完全覆盖。
导电元件14A、14B在密封材料6的上表面15上可以是暴露的。例如，使导电元件14A、14B暴露可以通过如下方式来实现：首先利用密封材料6将导电元件14A、14B密封并且然后从密封材料6的上表面15中去除密封材料6的部分直到导电元件14A、14B的上侧面变为暴露。在这一点上，例如可以使用研磨工艺。每个导电元件14A、14B可以提供从密封材料6的上表面15电接触第二接线层10的机会。这样，可以经由导电元件14A、14B电接触半导体芯片2、3、8中的一个或多个。
半导体器件400可以进一步包含电接触16A、16B，该电接触16A、16B可以被布置在导电元件14A、14B的暴露的表面之上或在导电元件14A、14B的暴露的表面上。例如，电接触16A、16B可以由一个或多个层的金属和/或金属合金制成。此外，半导体器件400可以包含电子部件17，该电子部件17可以被安装在密封材料6的主表面15之上或在密封材料6的主表面15上。例如，电子部件17可以包含无源电子部件、有源电子部件、微机电部件等中的至少一个。电接触16A、16B可以改进导电元件14A、14B的暴露的表面与电子部件17的电接触之间的电连接和/或热导率/传递。因为电接触16A、16B可以在密封材料6的表面15之上延伸，所以可以在密封材料6与电子部件17之间出现间隙。
对于半导体器件400操作为DC/DC转换器的示例性情况，例如，电子部件17可以包含对于DC/DC转换可能需要的电流存储电感器。在图4中，通过平行线示例性指示这样的电流存储电感器的线圈18。电子部件17可以经由电接触16A、16B被电耦合到导电元件14A、14B。在进一步的示例中，铜或铝块可以被安装在密封材料6的表面15之上并且可以充当提供顶侧面冷却的热管以便改进半导体器件400的热性能。
半导体器件400可以被看作为具有三层系统的半导体封装。在第一层19A中，可以借助于在层压板1中至少部分嵌入的一个或多个半导体芯片来实施电子功能性。在第二层19B中，可以借助于一个或多个半导体芯片和/或一个或多个电子部件来实施电子功能性，所述一个或多个半导体芯片和/或一个或多个电子部件被布置在层压板1之上或在层压板1上并且至少部分通过密封材料6被密封。在第三层19C中，可以在密封材料6之上或在密封材料6上安装进一步电子部件，从而提供进一步电子功能性。如能够从先前的注释中看到，在个别层19A至19C中含有的部件可以在半导体器件400的操作期间彼此相互作用。三层19A至19C的组合可以表示一个封装解决方案。
图5示意性图示依照本公开的半导体器件500的横截面视图。例如，半导体器件500可以与图4的半导体器件400类似并且可以包含类似的部件。与图4有关做出的所有注释因此也可以适用于图5的半导体器件500。
在图5中，电磁屏蔽20可以代替图4的电接触16A、16B和电子部件17，该电磁屏蔽20可以被布置在密封材料6之上。电磁屏蔽20可以被电连接到导电元件14A、14B。例如，电磁屏蔽20可以包含铜块、铜环、溅射的铜、镀覆的铜等中的至少一个。在其它示例中，可以采用类似的金属或金属合金用于制造电磁屏蔽20。特别地，电磁屏蔽20可以被连接到地电势。
图6示意性图示依照本公开的半导体器件600的横截面视图。半导体器件600可以与先前描述的半导体器件中的一个类似使得与图5有关的先前注释也可以适用。
半导体器件600可以包含一个或多个再分布层，该一个或多个再分布层可以被布置在层压板1的第一主表面4之上和/或在层压板1的第二主表面7之上和/或至少部分在层压板1里面。在图6的示例中，示例性再分布层21可以经过层压板1从层压板1的第一主表面4延伸到层压板1的第二主表面7。所形成的再分布层的数目和布置可以特别依赖于半导体器件600的所希望的功能性。
图7示意性图示依照本公开的半导体器件700的横截面视图。半导体器件700可以与先前描述的半导体器件中的一个类似使得与图6有关的先前注释也可以适用。
半导体器件700可以包含布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的半导体芯片3A。半导体芯片3A可以具有任意类型并且例如可以与图3的半导体芯片3类似。半导体芯片3A可以经由接合接线12A、12B被电连接到第二接线层10的部分，使得例如可以建立半导体芯片3A和在层压板1中嵌入的一个或多个半导体芯片和/或第二接线层10之间的电连接。
半导体器件700可以包含布置在半导体芯片3A之上或在半导体芯片3A上的进一步半导体芯片3B。半导体芯片3B可以具有任意类型并且例如可以与图3的半导体芯片3类似。半导体芯片3B可以经由接合接线12C、12D被电连接到接线层10的部分，使得可以建立半导体芯片3B和在层压板1中嵌入的一个或多个半导体芯片和/或第二接线层10之间的电连接。此外，叠堆的半导体芯片3A、3B可以例如在半导体芯片3A、3B之间的接触表面处被彼此电连接。替代地，可以在半导体芯片3A、3B之间布置电绝缘层（未图示）。
图8示意性图示依照本公开的半导体器件800的横截面视图。例如，半导体器件800可以与图3的半导体器件300类似。与图3对比，布置在层压板1的第一主表面4之上或在层压板1的第一主表面4上的半导体芯片3可以不必经由接合接线12A、12B被连接到第二接线层10。作为替代，半导体芯片3可以以倒装芯片方式被布置使得可以经由（流动的）焊料元件22（或焊料球或焊料凸出）来建立在布置在半导体芯片3的下表面之上或在半导体芯片3的下表面上的电接触与第二接线层10的电接触之间的电连接。
图9示意性图示依照本公开的半导体器件900的横截面视图。例如，半导体器件900可以与图3和8中的半导体器件300和800中的一个类似。与图3对比，布置在层压板1的第一主表面4之上的半导体芯片3可以不必经由接合接线12A、12B被连接到第二接线层10。作为替代，可以借助于扩散焊接工艺来建立半导体芯片3与第二接线层10的电接触之间的电连接。当执行这样的扩散焊接工艺时，焊料材料可以或者被施加在半导体芯片3的表面之上或在半导体芯片3的表面上，被施加在层压板1的第一主表面4之上或在层压板1的第一主表面4上，或者被施加在两者之上或在两者上。这里可以使用能够形成扩散焊料接合的任何焊料材料，例如包括Sn、SnAg、SnAu、In、InAg、InAu等中的一个或多个的焊料材料。扩散焊料接合可以包含一个或多个焊接层，该焊接层可以由相同或不同的焊料材料制成。在进一步的示例中，例如通过使用表面安装技术可以在层压板的第一主表面4之上或在层压板的第一主表面4上安装封装的芯片。
图10A至10D示意性图示用于依照本公开来制造多芯片器件1000的方法的横截面视图。通过该方法获得的半导体器件1000的横截面被图示在图10D中。例如，半导体器件1000可以与图1的半导体器件100类似。然而，所描述的方法也可以提供用于依照本文所描述的本公开来制造半导体器件中的任何一个的基础。在图10A中，第一半导体芯片2可以被嵌入在层压板1中。在图10B中，可以在层压板1的第一主表面4之上或在层压板1的第一主表面4上形成电接触5。在图10C中，可以在层压板1的第一主表面4之上或在层压板1的第一主表面4上安装第二半导体芯片3。在图10D中，可以将第二半导体芯片3电耦合到电接触5。在图10D的示例中，通过示例性接合接线12来图示第二半导体芯片3与电接触5之间的电耦合。然而，也可以通过本文描述的任何其它电耦合来提供电耦合。
所描述的方法可以包含进一步的动作，为了简单起见本文不明确图示该进一步的动作。例如，可以通过密封材料将第二半导体芯片3、电接触5和层压板1至少部分密封。例如，所产生的器件然后可以与图2的器件200类似。在进一步的示例中，与图3至9有关所描述的任何的部件可以被添加到半导体器件1000。
依照本文所描述的本公开的半导体器件可以具有下面的效应。当将依照本公开的半导体器件与提供类似功能性但包含多个芯片器件而不表示一个封装解决方案的半导体器件相比时，这些效应可能特别变得明显。所列出的效应既不是排他的也不是限制的。
与其它半导体器件相比，依照本公开的半导体器件可以提供提高的集成度。
与其它半导体器件相比，依照本公开的半导体器件可以更小。
当实施所希望的功能性的半导体器件时，采用与依照本公开的方法和/或半导体器件有关所描述的特征可以提供提高的设计自由度。
与其它半导体器件相比，依照本公开的半导体器件可以提供改进的电性能和/或热性能，特别是关于杂散电感、电容、效率等。
图11图示半桥电路1100的示意图。依照本公开的半导体器件可以被配置成操作为这样的半桥电路。半桥电路1100可以被布置在节点N1与N2之间。半桥电路可以包含串联连接的开关S1和S2。半导体器件300的如例如图3所示出的功率半导体芯片2和8可以被实施为开关S1和S2。可以施加恒定的电势到节点N1和N2。例如，诸如10、12、18、50、110、230、500或1000V或任何其它电势的高电势可以被施加到节点N1并且例如0V的低电势可以被施加到节点N2。因此，第一半导体芯片2可以被配置来充当低侧开关，然而第三半导体芯片8可以被配置来充当高侧开关。开关S1和S2可以在从1kHz到100MHz的范围内的频率处被切换，但是切换的频率也可以在这个范围外面。这意味着变化的电势可以在半桥的操作期间被施加到布置在开关S1和S2之间的节点N3。节点N3的电势可以在低电势与高电势之间的范围内变化。
例如，半桥电路可以被实施在用于将DC电压转换的电子电路（所谓的DC-DC转换器）中。DC-DC转换器可以用来将电池或可再充电电池所提供的DC输入电压转换成与下游连接的电子电路的要求匹配的DC输出电压。DC-DC转换器可以被具体化为降压转换器，其中输出电压小于输入电压；或被具体化为升压转换器，其中输出电压大于输入电压。可以将几MHz或更高的频率施加到DC-DC转换器。而且，高达100A或甚至更高的电流可以流经DC-DC转换器。
虽然可能已关于几个实施方式中的仅一个来公开本公开的特别特征或方面，但是可以将这样的特征或方面与其它实施方式的一个或多个其它特征或方面组合，如对于任何给定或特别的应用可能是所希望的或有利的。而且，就术语“包含”、“具有”、“带有”或它们的其它变体被用在详细描述或权利要求书中而言，这样的术语旨在以与术语“包括”类似的方式是包括的。而且，术语“示例性”仅仅表示为示例，而不是最好的或最优的。还要意识到的是：为了简化和容易理解的目的，利用彼此相对的特别尺寸来图示本文所描绘的特征和/或元件；并且实际的尺寸可以基本上不同于本文图示的尺寸。
尽管本文已图示和描述特定的方面，但是本领域普通技术人员将意识到各种替代和/或等价实施方式可以代替所示出和描述的特定方面而没有脱离本公开的范围。本申请旨在覆盖本文所讨论的特定方面的任何适配或变化。因此，本公开旨在仅由权利要求书及其等价物所限制。

Claims (22)

1.一种半导体器件，包括：
层压板；
第一半导体芯片，至少部分嵌入在层压板中；
第二半导体芯片，安装在层压板的第一主表面上；以及
第一电接触，布置在层压板的第一主表面上，其中所述第二半导体芯片被电耦合到所述第一电接触。
2.权利要求1的所述半导体器件，其中所述层压板包括环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、填充或未填充的热塑性聚合物材料、填充或未填充的热固性聚合物材料和聚合物混合物中的至少一种。
3.权利要求1的所述半导体器件，进一步包括：
密封材料，所述密封材料将所述层压板和所述第二半导体芯片至少部分密封。
4.权利要求3的所述半导体器件，其中所述密封材料包括环氧树脂、玻璃纤维填充的环氧树脂、玻璃纤维填充的聚合物、酰亚胺、填充或未填充的热塑性聚合物材料、填充或未填充的热固性聚合物材料、填充或未填充的聚合物混合物、成型化合物、顶部密封材料和层压材料中的至少一种。
5.权利要求1的所述半导体器件，其中所述第二半导体芯片通过接合接线、焊料连接、扩散焊料接合和导电胶中的至少一种被电耦合到所述第一电接触。
6.权利要求1的所述半导体器件，进一步包括：
第二电接触，布置在所述层压板的主表面上，其中所述第一半导体芯片通过微通孔被电耦合到所述第二电接触。
7.权利要求1的所述半导体器件，进一步包括：
安装在所述层压板的表面上的无源电子部件、有源电子部件和微机电部件中的至少一个。
8.权利要求1的所述半导体器件，其中所述第一半导体芯片包括功率半导体。
9.权利要求1的所述半导体器件，其中所述第二半导体芯片被配置来控制和/或驱动所述第一半导体芯片。
10.权利要求1的所述半导体器件，其中所述第一半导体芯片的厚度小于120微米。
11.权利要求1的所述半导体器件，其中所述第二半导体芯片的厚度大于100微米。
12.权利要求1的所述半导体器件，其中所述第一半导体芯片具有比所述第二半导体芯片更低的引脚数。
13.权利要求1的所述半导体器件，进一步包括：
第三半导体芯片，至少部分嵌入在所述层压板中。
14.权利要求13的所述半导体器件，其中所述第一半导体芯片的有源侧面面向第一方向并且所述第三半导体芯片的有源侧面面向与第一方向相对的第二方向。
15.权利要求14的所述半导体器件，进一步包括：
半桥电路，包括高侧开关和低侧开关，其中所述第一半导体芯片包括高侧开关并且所述第三半导体芯片包括低侧开关。
16.权利要求1的所述半导体器件，进一步包括：
第三电接触，布置在与层压板的第一主表面相对的层压板的第二主表面上，其中所述半导体器件是表面安装器件并且所述第三电接触被配置来支持所述半导体器件的表面安装。
17.权利要求3的所述半导体器件，进一步包括：
导电元件，延伸经过所述密封材料并且被配置来提供层压板的第一主表面与密封材料的主表面之间的电耦合。
18.权利要求17的所述半导体器件，进一步包括：
电子部件，安装在所述密封材料的主表面上并且电耦合到所述导电元件。
19.权利要求1的所述半导体器件，进一步包括：
再分布层，布置在所述层压板的至少一个表面之上和/或布置在所述层压板中。
20.权利要求17的所述半导体器件，进一步包括：
电磁屏蔽，布置在所述导电元件之上。
21.一种半导体封装，包括：
层压板；
电接触，布置在层压板的第一主表面上，
第一半导体芯片，至少部分嵌入在层压板中；
第二半导体芯片，布置在所述层压板的第一主表面上并且电耦合到所述电接触；以及
密封材料，将所述第二半导体芯片、所述电接触和所述层压板至少部分密封。
22.一种方法，包括：
在层压板中嵌入第一半导体芯片；
在所述层压板的第一主表面上形成电接触；
在所述层压板的第一主表面上安装第二半导体芯片；
将所述第二半导体芯片电耦合到所述电接触。
CN201410754725.XA 2013-12-11 2014-12-11 包含多个半导体芯片和层压板的半导体器件 Pending CN104716121A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/102625 2013-12-11
US14/102,625 US9263425B2 (en) 2013-12-11 2013-12-11 Semiconductor device including multiple semiconductor chips and a laminate

Publications (1)

Publication Number Publication Date
CN104716121A true CN104716121A (zh) 2015-06-17

Family

ID=53185464

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410754725.XA Pending CN104716121A (zh) 2013-12-11 2014-12-11 包含多个半导体芯片和层压板的半导体器件

Country Status (3)

Country Link
US (1) US9263425B2 (zh)
CN (1) CN104716121A (zh)
DE (1) DE102014117953B4 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962040A (zh) * 2017-12-19 2019-07-02 三星电子株式会社 半导体封装件以及堆叠型无源组件模块
CN110197816A (zh) * 2018-02-26 2019-09-03 三星电子株式会社 扇出型半导体封装件
CN110556364A (zh) * 2018-06-04 2019-12-10 三星电子株式会社 半导体封装件

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016105096B4 (de) 2016-03-18 2021-05-27 Infineon Technologies Ag Halbleitervorrichtung mit einer in einer umverteilungsschicht ausgebildeten passiven komponente
GB2555659B (en) * 2016-11-07 2020-01-15 Cirrus Logic Int Semiconductor Ltd Package for MEMS device and process
CN110114870B (zh) * 2016-12-28 2023-07-21 株式会社村田制作所 电路模块
JP2018137342A (ja) * 2017-02-22 2018-08-30 株式会社村田製作所 半導体装置及びその製造方法
US11521907B2 (en) 2020-10-14 2022-12-06 Infineon Technologies Ag Hybrid embedded package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1829416A (zh) * 2005-02-28 2006-09-06 三星电机株式会社 嵌入式芯片印刷电路板及其制造方法
CN103179779A (zh) * 2011-12-22 2013-06-26 太阳诱电株式会社 电路基板
US20130234283A1 (en) * 2012-03-08 2013-09-12 Infineon Technologies Ag Semiconductor Packages and Methods of Forming The Same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557417B2 (en) * 2007-02-21 2009-07-07 Infineon Technologies Ag Module comprising a semiconductor chip comprising a movable element
US7884444B2 (en) * 2008-07-22 2011-02-08 Infineon Technologies Ag Semiconductor device including a transformer on chip
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1829416A (zh) * 2005-02-28 2006-09-06 三星电机株式会社 嵌入式芯片印刷电路板及其制造方法
CN103179779A (zh) * 2011-12-22 2013-06-26 太阳诱电株式会社 电路基板
US20130234283A1 (en) * 2012-03-08 2013-09-12 Infineon Technologies Ag Semiconductor Packages and Methods of Forming The Same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962040A (zh) * 2017-12-19 2019-07-02 三星电子株式会社 半导体封装件以及堆叠型无源组件模块
CN110197816A (zh) * 2018-02-26 2019-09-03 三星电子株式会社 扇出型半导体封装件
CN110197816B (zh) * 2018-02-26 2024-02-13 三星电子株式会社 扇出型半导体封装件
CN110556364A (zh) * 2018-06-04 2019-12-10 三星电子株式会社 半导体封装件
CN110556364B (zh) * 2018-06-04 2023-05-23 三星电子株式会社 半导体封装件

Also Published As

Publication number Publication date
DE102014117953B4 (de) 2021-04-15
US9263425B2 (en) 2016-02-16
DE102014117953A1 (de) 2015-06-11
US20150162319A1 (en) 2015-06-11

Similar Documents

Publication Publication Date Title
CN104716121A (zh) 包含多个半导体芯片和层压板的半导体器件
US8188596B2 (en) Multi-chip module
US20200083207A1 (en) Method of Manufacturing a Multi-Chip Semiconductor Power Device
US8709867B2 (en) Dual-leadframe multi-chip package and method of manufacture
US9048338B2 (en) Device including two power semiconductor chips and manufacturing thereof
US8951847B2 (en) Package leadframe for dual side assembly
CN104620372B (zh) 半导体装置
CN110785838B (zh) 具有暴露的端子区域的树脂封装功率半导体模块
CN105845661A (zh) 在封装结构下方具有芯片的半导体装置
CN104051363B (zh) 芯片封装和用于制造该芯片封装的方法
CN103426873A (zh) 多芯片封装及其制造方法
CN105023920A (zh) 包括多个半导体芯片和多个载体的器件
KR101924917B1 (ko) 신축성 전력 모듈 반도체 패키지
US9362240B2 (en) Electronic device
JP2019046899A (ja) 電子装置
TWI681523B (zh) 用於封裝上元件之電路之機械相容的以及導電及導熱的引線架
US9837380B2 (en) Semiconductor device having multiple contact clips
CN104810330A (zh) 电子器件和用于制作电子器件的方法
CN104103617B (zh) 多层半导体封装
JP6534677B2 (ja) スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ
CN103367350B (zh) 电子模块
KR20160045477A (ko) 전력 모듈 및 그 제조 방법
US20160315033A1 (en) Device Including a Logic Semiconductor Chip Having a Contact Electrode for Clip Bonding
CN105990275A (zh) 功率模块封装件及其制作方法
US20190318976A1 (en) Cooling techniques for semiconductor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20150617