CN104103617B - 多层半导体封装 - Google Patents

多层半导体封装 Download PDF

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Publication number
CN104103617B
CN104103617B CN201410129154.0A CN201410129154A CN104103617B CN 104103617 B CN104103617 B CN 104103617B CN 201410129154 A CN201410129154 A CN 201410129154A CN 104103617 B CN104103617 B CN 104103617B
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lead
semiconductor die
electrode
layer
nude film
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CN104103617A (zh
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R·奥特雷姆巴
J·赫格劳尔
K·希斯
钟蔡梅
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明涉及一种多层半导体封装。半导体封装包括：半导体裸片，具有在第一侧的第一电极和相对第一侧的、在第二侧处的第二电极；第一引线，在半导体裸片下，并且连接到在封装的第一层处连接到的第一电极；以及第二引线，具有大于第一引线的高度并且在封装中的第一层之上的第二层处终止，该第二层对应于半导体裸片的高度。在半导体裸片和第二引线之上的单个连续平面结构的连接器在封装的相同的第二层处连接到第二电极和第二引线。

Description

多层半导体封装
技术领域
本申请涉及半导体封装，并且更具体地涉及多层半导体封装。
背景技术
电子组件集成密度的增加以及相关联的对热导率和电导率的更大的需要要求具有更优的热导率和电导率的新式连接技术，并且还要求用于相对应连接元件的结构技术。近年来，金属夹（clip）已经在用于提供半导体裸片（芯片）电极和模制封装引线（lead）之间的电连接的线接合（wire bond）上获得了普及。金属夹提供在封装引线和裸片电极之间的大面积连接，与线接合相比允许封装的电导率和热导率的增加。然而，传统的模制封装在封装中提供的所有引线都在相同层，限制在封装中的电导率和热导率性能以及互连布局。
发明内容
本文所述的实施例提供一种半导体封装，具有终止于在封装中的不同层的引线。在封装中至少包括一个单个连续平面结构的连接器，用于将半导体裸片的电极连接至封装中的相同层处的封装引线。
根据半导体封装的一个实施例，封装包括：半导体裸片，具有在第一侧的第一电极和在相对所述第一侧的第二侧的第二电极；第一引线，在所述半导体裸片下，并且在封装的第一层处连接到所述第一电极；以及第二引线，具有大于所述第一引线的高度，并且终止于在封装中的所述第一层之上的第二层，所述第二层对应于所述半导体裸片的高度。在所述半导体裸片和所述第二引线之上的单个连续平面结构的连接器在封装的相同的第二层处连接到第二电极和第二引线两者。
根据制造半导体封装的方法的一个实施例，方法包括：提供具有在第一侧的第一电极和在相对所述第一侧的第二侧处的第二电极的半导体裸片；将在所述半导体裸片下的第一引线在封装的第一层处连接到的所述第一电极；提供具有大于所述第一引线的高度并且在封装中的在所述第一层之上的第二层处终止的第二引线，所述第二层对应于所述半导体裸片的高度；并且将布置在所述半导体裸片和所述第二引线之上的单个连续平面结构的连接器在所述相同的第二层处连接到所述第二电极和所述第二引线两者。
根据半导体封装的另一个实施例，封装包括：第一半导体裸片，具有上侧和下侧；以及第二半导体裸片，在所述第一裸片之上，并且具有朝向背离所述第一裸片的上侧和朝向所述第一裸片的所述上侧的下侧。在所述第一裸片上侧的电极在所述第一裸片和所述第二裸片之间连接到在所述第二裸片的所述下侧的电极。在所述第一裸片下的第一引线在所述封装的第一层处连接到在所述第一裸片的所述下侧的电极。具有大于所述第一引线的高度的第二引线终止于在所述封装中、在所述第一层之上的第二层，所述第二层对应于所述第二裸片的高度。在所述第二裸片和所述第二引线之上的单个连续平面结构的连接器在封装的相同的第二层处连接到所述第二裸片的所述上侧的电极和所述第二引线两者。
根据制造半导体封装的方法的另一个实施例，该方法包括：将在第一半导体裸片的下侧的电极在所述封装的第一层处连接到在所述第一裸片下的第一引线；将在所述第一裸片的上侧的电极连接到在布置在所述第一芯片之上的第二半导体裸片的下侧的电极；并且将在所述第二裸片的上侧的电极在所述封装的在所述第一层之上的相同的第二层处、经由布置在所述第二裸片和所述第二引线之上的单个连续平面结构的连接器，连接到所述第二引线，第二引线具有大于所述第一引线的高度并且终止于所述第二层，所述第二层对应于所述第二裸片的高度。
本领域技术人员基于阅读以下详细说明以及基于查看附图，将识别另外的特征和优点。
附图说明
附图中的组件不一定按比例绘制，而是将重点放在图示本发明的原理上。此外在附图中，相似的附图标记标示相同的部件。在附图中：
图1例图示根据本发明的一个实施的一种多层半导体封装的横截面图；
图2图示根据本发明的另一个实施例的一种多层半导体封装的横截面图；
图3图示由被包括在图2的封装中的组件实现的半桥式转换器电路的示例性电路图；
图4示出根据本发明的又一个实施例的一种多层半导体封装的俯视图；以及
图5示出图4的多层半导体封装的侧面透视图。
具体实施方式
本文所述的实施例提供一种半导体封装，具有终止于在封装中的不同层的引线。在封装中至少包括一个连接器，用于将一个或多个半导体裸片电极连接到终止于在封装中的与连接器相同的层的引线。因此，连接器可以具有单个连续平面结构，并且引线延伸到平面连接器，而不是必须向下向着封装的相同基础层弯曲的连接器，在该封装的相同基础层处通常封装的所有引线都终止于此。可以提供多个具有单个连续平面结构的连接器，从而多个裸片电极可以在封装中的多个层连接到不同的封装引线，每个层都被大体平面地布置。提供在半导体封装中的不同层处的引线，并且使用单个连续平面结构的连接器用于裸片的电极到引线连接，改进了封装的电和热的性能并且增加了设计的灵活性。
图1图示具有高度HPKG的多层半导体封装100的一个实施例的横截面图。封装100包括具有在封装100中的高度H裸片的至少一个半导体裸片102。裸片102具有在裸片102的第一侧103（在图1中的下侧）的第一电极104，以及与第一侧103相对的裸片102第二侧105（在图1中的上侧）处的第二电极106。在封装100中可以使用任何类型的半导体裸片102。裸片102的类型依赖于封装100被设计用于的应用，并且可以包括例如IGBT（绝缘栅双极晶体管）、MOSFET（金属氧化物半导体场效应晶体管）、JFET（结型场效应晶体管）、二极管等。在晶体管裸片102的情况下，可以在裸片102的第二（上）侧105提供第三电极108。在该情况下，在裸片102的第一（下）侧103的电极104可以是MOSFET的漏极电极或IGBT的集电极电极，并且在第二（上）侧105的电极106、108可以分别是MOSFET的源极电极或IGBT的发射极电极、以及栅极（控制）电极。对于二极管栅极（控制）电极108被省略。在封装100中可以包括多于一个个裸片。例如，在封装100中可以包括分离的高侧和低侧晶体管裸片以及用于控制上侧和下侧晶体管的栅极驱动器。备选地，可以在本文所述的多层封装的分离的层中包括高侧和低侧晶体管裸片，作为分立组件。
在每个情况下，多层封装100还在半导体裸片102下包括第一引线110。第一引线110在封装100的第一层处（“层A”）连接到裸片102的第一电极104。能够通过从封装100的背侧101延伸到第一引线108的导电插塞（plug）或其他导电结构形成到第一引线110的背侧111的连接。这类结构改进封装100的热性能，并且为了简化图示在图1中未示出。
具有大于第一引线110高度（HL1）的高度（HL2）的第二引线112终止于在封装100中的在第一层之上的第二层（“层B”）。第二层对应于裸片102的高度（H裸片）。裸片102的第一电极104经由结合层114（诸如导电焊料、粘合剂或胶带）附连到第一引线110。并且第二层占裸片102和结合层114的组合的厚度。该方式下第二引线112近似终止于与在裸片102的第二（上）侧105的第二电极106的相同的平面中，允许在第二电极106和第二引线112之间的大体平面的连接。
为此，在半导体裸片102和第二引线112之上放置单个连续平面结构的连接器116。连接器116在封装100中的相同的第二层处（层B）连接到第二引线112以及在裸片102第二（上）侧105的第二电极106两者，在裸片102的第二电极106以及第二引线112之间提供大面积平面连接。
如果半导体裸片102是晶体管裸片，那么封装100还包括具有小于第二引线112的高度（HL3）第三引线118，用于连接到在裸片102的第二（上）侧105的第二（栅极/控制）电极108。第三引线118终止于在封装100中的第一和第二层之间的第三层（“层C”）。接合线120将第三引线118连接到在裸片102的第二（上）侧105的第三电极108。半导体裸片102、连接器116的至少部分以及引线110、112、118的部分被诸如环氧树脂的模制化合物122封装，从而每个引线110、112、118的区段以及可选地连接器116的部分保持不被模制化合物122覆盖。
图2图示具有高度HPKG的多层半导体封装200的另一个实施例的横截面图。封装200包括在封装200中的、具有高度H裸片1的第一（低）半导体裸片202，以及在封装200中的、在第一裸片202之上并且具有高度H裸片2的第二（高）半导体裸片204，其中H裸片1<H裸片2<HPKG。第一裸片202具有上侧201和下侧203，并且第二裸片204具有朝向背离第一裸片202的上侧205以及朝向第一裸片202的上侧201的下侧207。
在第一裸片202的上侧201的电极206在第一和第二裸片202、204之间连接到在第二裸片204的下侧207处的电极208，从而该电极206、208在相同的电势上。在一个纯粹示例性的实施例中，被包括在图2的封装200中的、由裸片202、204所实现的电路是如图3中所示的半桥式变换器电路。半桥电路包括低侧晶体管（LS）、高侧晶体管（HS）以及耦合于半桥电路的正输入（Vin+）和负输入（Vin-）之间的输入电容（Cin）。在一些配置中负输入可以接地。低侧晶体管LS对应于在图2中示出的第一裸片202，高侧晶体管HS对应于第二裸片204，并且输入电容Cin在图2中的视图之外。在图3中示出的示例性的电路图中，晶体管是MOSFET，每个都具有栅极（G）、漏极（D）和源极（S）端子。
低侧晶体管LS的栅极、漏极和源极端子对应于在图2中示出的第一裸片202的栅极、源极和漏极电极。高侧晶体管HS的栅极、漏极和源极同样地对应于第二裸片204的栅极、源极和漏极电极。高侧晶体管HS的漏极端子电连接到半桥电路的正输入（Vin+）。高侧晶体管HS的源极端子电连接到低侧晶体管LS的漏极端子，以形成半桥电路的输出（Vout）。低侧晶体管LS的源极端子电连接到负输入（Vin-）。晶体管栅极用作控制信号输入（IN1、IN2）。IGBT可以代替MOSFET使用，其中IGBT的集电极连接将对应于MOSFET的漏极连接，并且IGBT的发射极连接将对应于MOSFET的源极连接。在任一情况下，半桥电路的正输入端子（Vin+）、负输入端子（Vin-）和输出端子（Vout）对应于图2中示出的封装200的不同的引线。大体上被包括于封装200中的半导体裸片的类型和数目依赖于封装200被设计用于的具体应用，并且本文所述的、裸片电极至引线互连的实施例可以用于每个情况。
如上所述，被包括于封装200中的每个半导体裸片202、204在裸片的每一侧上都具有一个或多个电极。例如，第一裸片202具有在裸片202的下侧203上的栅极电极201和源极电极212、以及在裸片202的上侧201上的漏极电极206。在相反的方式中，第二裸片204具有在裸片204的上侧207上的漏极电极208、以及在裸片204的上侧205上的源极电极214。第二裸片204的栅极电极在图2中的视图之外。第一裸片202具有根据该实施例的所称谓的“倒装芯片”配置。然而，可以使用其它裸片配置。
第一裸片202的源极/发射极电极212由第一结合层216（诸如导电焊料、粘合剂或胶带）连接到封装200的第一引线218。第一引线218布置在第一裸片202下，具有高度HLA，并且电连接到半桥电路的负输入（Vin-）。第一引线218具有朝向背离裸片202、204的、未被覆盖的第一侧219，以及经由在封装200的第一层（“层A”）处的第一结合层216而连接到在第一裸片202的下侧203的源极/发射极电极212的相对的第二侧221。第一裸片202的栅极电极210由第二结合层220（诸如导电焊料、粘合剂或胶带）在与第一裸片202的源极/发射极电极212相同的层（层A）处连接到封装200的第二引线222。第二引线222电连接到低侧晶体管LS的栅极输入（IN2）。
封装200还包括具有高度HLB>HLA并且终止于在封装200中的、在第一层之上的第二层（“层B”）处的第三引线224。第三引线224具有朝向背离裸片202、204的、未被覆盖的第一侧225以及终止于第二层处的相对的第二侧227。第二层对应于第二裸片204的高度，并且占裸片202、204和任何中间的结合层216、226、228的组合厚度。第三引线224电连接到半桥电路的正输入端子（Vin+）。
第二裸片204的漏极/集电极电极214由结合层230（诸如导电焊料、粘合剂或胶带）连接到由布置在第二裸片204和第三引线224之上的单个、连续的平面结构的第一（上）连接器232。第一平面连接器232在相同的第二层（层B）处连接到在第二裸片204的上侧205的漏极/集电极电极214以及第三引线224两者，在第二裸片204的漏极/集电极电极214和封装200的第三引线224之间提供大面积平面连接。
封装200还包括具有高度HLC（其中HLB>HLC>HLA）并且终止于在封装200中的第一和第二层之间的第三层（“层C”）的第四引线234。封装200的第三层对应于第一裸片202的高度，并且占第一裸片202以及在第一裸片202的下侧203的结合层216的组合厚度。
单个连续平面结构的第二连接器236在第一和第二裸片202、204之间延伸到第四引线234，并且将在第一裸片202的上侧201的漏极/集电极电极206以及在第二裸片204的下侧207的源极/漏极电极208连接到第四引线234。第二平面连接器236在相同的第三层（层C）处连接到在第一裸片202的上侧201的源极/漏极电极206以及第四引线234两者。平面连接器232、236可以由附加的结合层226、228、230、238、240（诸如导电焊料、粘合剂或胶带）分别连接到对应的引线。由模制化合物242（诸如环氧树脂）封装半导体裸片202、204、结合层216、226、228、230、238、240、平面连接器232、236的至少一部分、以及引线218、222、224、234的至少部分，从而每个引线218、222、224、234的区段以及可选地连接器232、236中的一个或两者的部分保持不被模制化合物242覆盖。
图4图示了多层半导体封装400的又一个实施例的顶视图，并且图5图示封装400的透视侧视图。类似于图2中示出的封装，图4和图5中示出的封装400包括形成在一个示例性实施例中示出的图3中示出的种类的半桥转换器电路的至少两个晶体管裸片402、404。可以依赖于被包括在封装400中的裸片的类型来实现其它电路配置。在图4和图5中示出的被包括在封装400中的裸片402、404被布置在相同的平面中，并且如图2中所示没有一个堆叠在另一个上。在该纯粹说明性的实施例中，到裸片402、404的电路连接与本文中前述的关于图3的半桥转换器电路相同。在图4中仅可见在第二裸片404的上侧的栅极电极406。第二裸片404的栅极电极406由接合线408连接到封装400的第一引线410，第一引线410电连接到高侧晶体管HS的栅极输入（N1）。第一引线410终止于在封装400中的第一层（“层A”）。单个连续平面结构的连接器412将在第二裸片404的上侧的源极电极在封装400中的相同层（“层B”）处连接到的第二引线414，并且在图4中隐藏了大部分的封装组件。
第二引线414电连接到半桥电路的输出端子（Vout）。在第一裸片402的上侧的漏极电极以及第二裸片404的上侧的源极电极两者都连接到平面连接器412。平面连接器412在裸片402、404两者之上延伸，并且分别连接到芯片402、404两者的漏极和源极电极，并且在封装400的相同第三层（层B）处连接到第二引线414，在这些裸片电极和封装400的第二引线414之间提供大面积平面连接。在一个实施例中，平面连接器412具有大于裸片402、404两者的组合表面面积的表面面积。
在第一裸片402的下侧的栅极电极在封装400的第一层（层A）处连接到第三引线416。第三引线416电连接到低侧晶体管LS的栅极输入（IN2）。在第一裸片402的下侧的源极电极连接到第四引线418，第四引线418也终止于封装400的第一层（层A）。第四引线418电连接到半桥电路的负输入（Vin-）。在第二裸片404下的第五引线420类似地连接到在第二裸片404的下侧的漏极电极。第五引线420电连接到半桥电路的正输入（Vin+）。可以由模制化合物来密封封装400。
本文所述的封装可以具有标准的形状因子（form-factor），诸如SO（小外形）、SOP（小外形封装）、SOT（小外形晶体管封装）、SuperSO（英飞凌科技制造）等。大体上，本文所述的封装具有在封装中的不同层的引线，并且使用单个连续平面结构的连接器用于裸片电极到引线的连接。
诸如“之上”、“之下”、“较低”、“上”、“较高”等的空间相关术语用于以便于解释一个元件相对于第二个元件的定位的解释。这些术语旨在于包含除了图中描绘的那些不同方位之外的设备的不同方位。此外，诸如“第一”、“第二”等的术语也用于描述各种元件、区域、部分等，并且也不旨在于限制。类似的术语贯穿说明书指代相似的元件。
如本文所使用的，“具有”、“包含”、“包括”、“含有”等是开放式的术语，指示描述的元件和特征的存在，但是不排除其它的元件或特征。除了其它本文明确指示的，冠词“一”、“一个”和“该”旨在于包括复数以及单数。
考虑以上变型和应用的范围，应当理解本发明不限于以上描述，也不由附图限制。相反，本发明仅通过以下权利要求和它们的法律等同限制。

Claims (6)

1.一种半导体封装，包括：
第一半导体裸片，具有上侧和下侧；
第二半导体裸片，在所述第一半导体裸片之上，并且所述第二半导体裸片具有背离所述第一半导体裸片的上侧和与所述第一半导体裸片的所述上侧面对的下侧；
在所述第一半导体裸片上侧的电极，在所述第一半导体裸片和所述第二半导体裸片之间连接到在所述第二半导体裸片的所述下侧的电极；
第一引线，在所述第一半导体裸片之下，并且所述第一引线在所述封装的第一层处连接到在所述第一半导体裸片的所述下侧处的电极；
第二引线，具有大于所述第一引线的高度，并且在所述封装中在所述第一层之上的第二层处终止，所述第二层对应于所述第二半导体裸片的高度；以及
单个连续平面结构的连接器，在所述第二半导体裸片和所述第二引线之上，所述连接器在相同的所述第二层处连接到在所述第二半导体裸片的所述上侧的电极和所述第二引线两者。
2.根据权利要求1所述的半导体封装，还包括：
第三引线，具有在所述第一引线和所述第二引线之间的高度，并且在所述封装中在所述第一层和所述第二层之间的第三层处终止，所述第三层对应于所述第一半导体裸片的高度；以及
单个连续平面结构的附加连接器，在所述第一半导体裸片和所述第二半导体裸片之间延伸到所述第三引线，并且将在所述第一半导体裸片的所述上侧的所述电极和在所述第二半导体裸片的所述下侧的所述电极连接到所述第三引线，所述附加连接器在相同的所述第三层处连接到在所述第一半导体裸片的所述上侧的所述电极和所述第三引线。
3.根据权利要求1所述的半导体封装，其中所述第一引线具有背离所述裸片的未被覆盖的第一侧，以及经由第一结合层连接到所述第一半导体裸片的所述下侧处的所述电极的相对的第二侧，其中所述第二引线具有背离所述裸片的未被覆盖的第一侧，以及在所述第二层处终止的相对的第二侧，并且其中所述连接器经由第二结合层连接到在所述第二半导体裸片的所述上侧的和在所述第二引线的所述第二侧的所述电极两者。
4.根据权利要求3所述的半导体封装，其中所述结合层中每一个都包括导电焊料、粘合剂或胶带。
5.根据权利要求1所述的半导体封装，还包括第三引线，所述第三引线具有与所述第一引线相同的高度，并且在所述封装的所述第一层处连接到在所述第一半导体裸片的所述下侧的附加电极。
6.根据权利要求1所述的半导体封装，其中：
所述第一半导体裸片是半桥转换器电路的低侧晶体管，并且所述第二半导体裸片是所述半桥转换器电路的高侧晶体管；
在所述第一半导体裸片的所述下侧的所述电极是所述低侧晶体管的源极电极；
在所述第一半导体裸片的所述上侧的所述电极是所述低侧晶体管的漏极电极；
在所述第二半导体裸片的所述上侧的所述电极是所述高侧晶体管的漏极电极；
在所述第二半导体裸片的所述下侧的所述电极是所述高侧晶体管的源极电极；
第三引线被指定作为所述半桥转换器电路的输出；并且
所述单个持续平面结构的连接器将所述第三引线在相同的第三层处经由结合层连接到所述低侧晶体管的所述漏极电极，并且连接到所述高侧晶体管的所述源极电极。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160172279A1 (en) * 2014-12-10 2016-06-16 Infineon Technologies Americas Corp. Integrated Power Assembly with Reduced Form Factor and Enhanced Thermal Dissipation
DE102015104995B4 (de) 2015-03-31 2020-06-04 Infineon Technologies Austria Ag Verbindungshalbleitervorrichtung mit einem mehrstufigen Träger
CN105405830A (zh) * 2015-12-09 2016-03-16 西安华为技术有限公司 系统级封装模块和封装方法
FR3060243B1 (fr) * 2016-12-12 2019-08-23 Institut Vedecom Module de commutation de puissance, convertisseur integrant celui-ci et procede de fabrication
CN110211887A (zh) * 2019-06-11 2019-09-06 山东海声尼克微电子有限公司 一种用于大电流电源模块引线键合的锁料孔铜片焊接工艺
CN110190004A (zh) * 2019-06-11 2019-08-30 山东海声尼克微电子有限公司 一种用于大电流电源模块键合的焊接工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174602A (zh) * 2006-10-06 2008-05-07 万国半导体股份有限公司 高电流半导体功率器件小外形集成电路封装
CN101595560A (zh) * 2007-01-24 2009-12-02 费查尔德半导体有限公司 预模制夹头结构
CN102194806A (zh) * 2010-03-18 2011-09-21 万国半导体股份有限公司 堆栈式双晶片封装及其制备方法
CN102468292A (zh) * 2010-10-29 2012-05-23 万国半导体股份有限公司 一种用于直流-直流转换器的封装体结构

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255722B1 (en) 1998-06-11 2001-07-03 International Rectifier Corp. High current capacity semiconductor device housing
US6677669B2 (en) 2002-01-18 2004-01-13 International Rectifier Corporation Semiconductor package including two semiconductor die disposed within a common clip
US6946740B2 (en) 2002-07-15 2005-09-20 International Rectifier Corporation High power MCM package
DE10301091B4 (de) 2003-01-14 2015-01-22 Infineon Technologies Ag Leistungs-Halbleiterbauelement und Verfahren zur Verbindung von einem gemeinsamen Substratträger zugeordneten Halbleitereinrichtungen
JP2005217072A (ja) 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
JP2005302951A (ja) * 2004-04-09 2005-10-27 Toshiba Corp 電力用半導体装置パッケージ
JP4438489B2 (ja) 2004-04-13 2010-03-24 富士電機システムズ株式会社 半導体装置
US7208818B2 (en) 2004-07-20 2007-04-24 Alpha And Omega Semiconductor Ltd. Power semiconductor package
CN101073151B (zh) 2004-12-20 2010-05-12 半导体元件工业有限责任公司 具有增强散热性的半导体封装结构
US20070057368A1 (en) 2005-09-13 2007-03-15 Yueh-Se Ho Semiconductor package having plate interconnections
US7285849B2 (en) 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7804131B2 (en) 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
US7808102B2 (en) 2006-07-28 2010-10-05 Alpha & Omega Semiconductor, Ltd. Multi-die DC-DC boost power converter with efficient packaging
DE102007013186B4 (de) 2007-03-15 2020-07-02 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US7851908B2 (en) 2007-06-27 2010-12-14 Infineon Technologies Ag Semiconductor device
US7800208B2 (en) 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
JP5067267B2 (ja) 2008-06-05 2012-11-07 三菱電機株式会社 樹脂封止型半導体装置とその製造方法
US8193618B2 (en) * 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US8344464B2 (en) 2011-05-19 2013-01-01 International Rectifier Corporation Multi-transistor exposed conductive clip for high power semiconductor packages
US8436429B2 (en) 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174602A (zh) * 2006-10-06 2008-05-07 万国半导体股份有限公司 高电流半导体功率器件小外形集成电路封装
CN101595560A (zh) * 2007-01-24 2009-12-02 费查尔德半导体有限公司 预模制夹头结构
CN102194806A (zh) * 2010-03-18 2011-09-21 万国半导体股份有限公司 堆栈式双晶片封装及其制备方法
CN102468292A (zh) * 2010-10-29 2012-05-23 万国半导体股份有限公司 一种用于直流-直流转换器的封装体结构

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