CN102468292A - 一种用于直流-直流转换器的封装体结构 - Google Patents

一种用于直流-直流转换器的封装体结构 Download PDF

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CN102468292A
CN102468292A CN2010105383276A CN201010538327A CN102468292A CN 102468292 A CN102468292 A CN 102468292A CN 2010105383276 A CN2010105383276 A CN 2010105383276A CN 201010538327 A CN201010538327 A CN 201010538327A CN 102468292 A CN102468292 A CN 102468292A
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mosfet chip
low side
slide holder
body structure
converter
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CN102468292B (zh
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何约瑟
薛彦迅
鲁军
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种用于直流-直流转换器的封装体结构,通过设置厚薄不同的载片台,或是通过设置含不同厚薄联结部的中间联结件,使低端MOSFET芯片能够堆叠在第一载片台的高端MOSFET芯片上,以减少封装时元件的数量;并在控制器与低端MOSFET芯片的空隙中容纳若干连接引线,以进一步减小整个半导体封装的尺寸。在同样大的引线框架上,可以充分扩展各器件的尺寸,来有效提高半导体器件的产品性能。还通过金属连接板的设置实现低端MOSFET芯片的顶部源极与低端源极引脚之间的电性连接,使该金属连接板能够在直流-直流转换器塑封封装后外露,以改善半导体封装的热性能,同时有效降低该半导体封装的厚度。

Description

一种用于直流-直流转换器的封装体结构
技术领域
本发明涉及一种半导体封装体结构,特别涉及一种能将多个芯片等元器件封装在同一个封装体中的应用于直流-直流转换器的封装体结构。
背景技术
在直流-直流转换器中通常设有两个MOSFET(金属氧化物半导体场效应管)作为切换开关。如图1所示,是由2个N型MOSFET连接形成的直流-直流(DC-DC)转换器的电路图。
其中高端MOSFET的栅极G1及低端MOSFET的栅极G2均与一控制器连接;高端MOSFET(HS)的漏极D1连接Vin端,其源极S1连接低端MOSFET(LS)的漏极D2,而低端MOSFET的源极S2连接Gnd端,则形成所述直流-直流转换器。一般在直流-直流转换器的Vin-Gnd两端之间还设置有电容、电感等元器件。
如图2所示,现有一种直流-直流转换器的封装结构,使高端MOSFET芯片和低端MOSFET芯片以及控制器封装在同一个封装体中,以减少外围器件数量,同时提高电源等的利用效率。
然而对于具体的封装体来说,上述高端MOSFET芯片和低端MOSFET芯片以及控制器只能在引线框架的同一个平面上平行布置,那么封装体的安装空间很大程度上限制了高端MOSFET、低端MOSFET以及控制器的尺寸,这对直流-直流转换器的性能提高具有很大的影响。
发明内容
本发明的目的在于提供一种用于直流-直流转换器的封装体结构,能够将多个半导体芯片等元器件封装在同一个半导体封装中,以减少直流-直流转换器组装时元件的数量,也减小整个半导体封装的尺寸;进一步地由于封装空间的节省,能够在同样大小的封装体内增大芯片或控制器的尺寸,来有效提高半导体器件的产品性能。
为了达到上述目的,本发明的技术方案是提供一种用于直流-直流转换器的封装体结构,其特征在于,包含:
分别具有底部漏极、顶部栅极和顶部源极的高端MOSFET芯片和低端MOSFET芯片;
引线框架,其设置有第一载片台和第二载片台;
所述高端MOSFET芯片设置在第一载片台上,使其底部漏极与所述第一载片台形成电性连接;
控制器,也设置在所述第一载片台上,其与所述高端MOSFET芯片的顶部栅极电性连接;
导电的中间联结件,其设置在所述第二载片台及高端MOSFET芯片上,并与所述高端MOSFET芯片的顶部源极电性连接;
所述低端MOSFET芯片设置在所述中间联结件上,其顶部栅极与所述控制器电性连接;其底部漏极与所述中间联结件的顶面电性连接,即与所述高端MOSFET芯片的顶部源极也电性连接;
所述中间联结件不覆盖所述控制器,使在所述控制器上方、与所述低端MOSFET芯片之间存在空隙。
在本发明的一种优选实施例中,所述第二载片台的厚度大于所述第一载片台的厚度。
所述第二载片台的厚度与所述第一载片台上堆叠了高端MOSFET芯片后的厚度一致。
在本发明的另一种优选实施例中,所述导电的中间联结件包含一体设置的第一联结部,以及厚于所述第一联结部的第二联结部;
所述第二联结部设置在第二载片台上;
所述第一联结部设置在所述第一载片台的高端MOSFET芯片上,使在所述高端MOSFET芯片的顶部源极通过该第一联结部,与所述低端MOSFET芯片的底部漏极之间形成电性连接。
所述第一联结部设置在所述第一载片台的高端MOSFET芯片顶面之后的厚度,与所述第二联结部设置在第二载片台顶面之后的厚度一致。
在上述两种优选实施例中,所述引线框架上还设置有与所述第一载片台、第二载片台分隔且无电性连接的若干引脚,包含若干低端源极引脚、低端栅极引脚、高端源极引脚、高端栅极引脚以及控制引脚。
所述高端MOSFET芯片通过若干连接引线键合,分别在其顶部栅极与高端栅极引脚之间、顶部源极与高端源极引脚之间分别形成电性连接。
所述控制器通过若干连接引线键合,分别与所述第一载片台、若干控制引脚、低端栅极引脚,以及高端MOSFET芯片的顶部栅极形成电性连接。
所述低端MOSFET芯片通过若干连接引线键合,使其顶部栅极与所述低端栅极极引脚之间形成电性连接,即与所述控制器之间也形成电性连接。
所述低端MOSFET芯片,覆盖所述中间联结件和控制器顶部的部分或全部区域。
所述控制器上方、与所述低端MOSFET芯片之间的空隙中,容纳所述键合连接控制器与高端MOSFET芯片或控制引脚的若干连接引线。
所述低端MOSFET芯片通过若干连接引线键合,使其顶部源极与所述低端源极引脚之间形成电性连接。
所述用于直流-直流转换器的封装体结构,还包含若干金属连接板,来电性连接所述低端MOSFET芯片的顶部源极与所述低端源极引脚,使所述金属连接板得以暴露在所述封装体结构的表面之外。
本发明所述用于直流-直流转换器的封装体结构,与现有技术相比,其优点在于:
本发明通过设置厚薄不同的第一、第二载片台,或是通过设置含不同厚薄联结部的中间联结件,使低端MOSFET芯片放置到中间联结件顶面后,能够堆叠在第一载片台的高端MOSFET芯片上,并通过中间联结件连接高端MOSFET芯片的顶部源极与低端MOSFET芯片的底部漏极,以减少直流-直流转换器组装时元件的数量。同时在第一载片台的控制器上方、与低端MOSFET芯片之间的空隙中,能够容纳键合连接控制器与高端MOSFET芯片或若干引脚的若干连接引线,以进一步减小整个半导体封装的尺寸。
本发明由于采用低端MOSFET芯片通过中间联结件堆叠至高端MOSFET芯片和控制器上方的封装体结构,与现有技术在引线框架上平铺设置高、低端MOSFET芯片和控制器的结构相比,本实施例在同样大的引线框架上,可以充分扩展各器件的尺寸,如将低端MOSFET芯片面积增大至覆盖整个高端MOSFET芯片和控制器上方,能够有效提高半导体器件的产品性能。
本发明还通过金属连接板、金属连接带等金属连接体,来实现低端MOSFET芯片的顶部源极与低端源极引脚之间的电性连接,使该金属连接板能够在直流-直流转换器塑封封装后外露,以改善半导体封装的热性能,同时有效降低该半导体封装的厚度。
由本发明所述通过设置厚薄不同的载片台,或是设置含不同厚薄联结部的中间联结件来承载并电性连接若干元器件的结构,可以方便地将各种半导体芯片、控制器、电感或电容等元器件堆叠,使其能被封装在同一个半导体封装中,以扩展本发明形成各种其他半导体器件。
附图说明
图1是直流-直流转换器的电路原理框图;
图2是现有直流-直流转换器的封装结构示意图;
图3是本发明用于直流-直流转换器的封装体结构在实施例1中的总体结构示意图;
图4~图15是本发明用于直流-直流转换器的封装体结构在实施例1中的分层结构示意图;
其中,图4、图7、图10、图13是实施例1中封装体结构的俯视图;
图5、图8、图11、图14分别是沿图4、图7、图10、图13中A-A’方向的剖面图;
图6、图9、图12、图15分别是沿图4、图7、图10、图13中B-B’方向的剖面图;
图16是本发明用于直流-直流转换器的封装体结构在实施例2中的结构俯视图;
图17是沿图16中A-A’方向的剖面图;
图18是沿图16中B-B’方向的剖面图。
具体实施方式
以下根据图3~图18,详细说明本发明的一些较佳实施例,以更好的理解本发明的技术方案和有益效果。
如图1所示,本发明中所提供的直流-直流转换器,是由2个相同类型的MOSFET芯片分别作为高端MOSFET芯片和低端MOSFET芯片,与控制器或其他元器件连接后,封装在同一个封装体内,形成独立的半导体器件。
该2个MOSFET芯片可以是2个N型或P型的MOSFET芯片。但是由于N型MOSFET芯片相比于P型MOSFET芯片,体积较小,电阻也较小,故在以下所述的实施例中,均以2个N型MOSFET芯片为例说明。但应当注意的是,这些具体描述及实例并非用来限制本发明的范围。
所述高端MOSFET芯片相比于低端MOSFET芯片尺寸较小。高端和低端MOSFET芯片均具有底部漏极、顶部源极和顶部栅极,其中高端MOSFET的栅极G1及低端MOSFET的栅极G2均与一控制器连接;高端MOSFET(HS)的漏极D1连接Vin端,其源极S 1连接低端MOSFET(LS)的漏极D2,而低端MOSFET的源极S2连接Gnd端,形成所述直流-直流转换器。在直流-直流转换器的Vin-Gnd两端之间还可以设置电容、电感等元器件。
实施例1
如图3所示是本实施例所述用于直流-直流转换器的封装体结构的示意图,其包含一引线框架,该引线框架上在同一平面设置有厚度不同的第一载片台11和第二载片台12,假设第二载片台12的厚度大于第一载片台11厚度。在本实施例中第一载片台11还包括相互分离的第一部分和第二部分。当然,也可选用第一部分和第二部分相互连接的第一载片台。
该引线框架上还设置有与第一、第二载片台分隔且无电性连接的若干引脚,包含低端源极引脚133、低端栅极引脚134、高端源极引脚131、高端栅极引脚132以及控制引脚135。
请参见图3所示,并配合参见图4所示俯视图;图5所示是图4在A-A’向的剖面图,图6所示是图4在B-B’向的剖面图。
将所述尺寸较小的高端MOSFET芯片21粘接帖附至第一载片台11第一部分上,使其底部漏极(图中未示)与第一载片台11第一部分形成电性连接;而其顶部源极211和顶部栅极212通过若干连接引线51键合,分别与上述高端源极引脚131、高端栅极引脚132形成电性连接。
将控制器40粘接贴附至第一载片台11第二部分上,使控制器40通过若干连接引线51键合,分别与第一载片台11、若干控制引脚135、低端栅极引脚134,以及高端MOSFET芯片21的顶部栅极212形成电性连接。
请参见图3所示,并配合参见图7所示俯视图;图8所示是图7在A-A’向的剖面图,图9所示是图7在B-B’向的剖面图。
所述第二载片台12的厚度与第一载片台11上堆叠了高端MOSFET芯片21后的厚度一致。在该第二载片台12及高端MOSFET芯片21上固定设置一导电的中间联结件30,使该中间联结件30底部仅覆盖高端MOSFET芯片21顶部的一部分,且与所述高端MOSFET芯片21的顶部源极211电性连接(图8)。
请参见图3所示,并配合参见图10所示俯视图;图11所示是图10在A-A’向的剖面图,图12所示是图10在B-B’向的剖面图。
在中间联结件30顶面粘接贴附所述面积较大的低端MOSFET芯片22,并与其底部漏极电性连接,因而形成图1中所示高端MOSFET芯片21的源极与低端MOSFET芯片22的漏极的电性连接。
该低端MOSFET芯片22放置在中间联结件30上,并覆盖高端MOSFET芯片21和控制器40上方的部分区域(图10);低端MOSFET芯片22超出中间联结件30的至少一个边沿延伸到控制器40上方的分区域,由于中间联结件30并不覆盖控制器40顶部,也不与其有任何连接(图8),使在控制器40上方与低端MOSFET芯片22之间的空隙中,能够容纳上述键合连接控制器40与高端MOSFET芯片21或控制引脚135的若干连接引线51(图11)。
该低端MOSFET芯片22上分别通过若干连接引线51键合,将顶部栅极222,与所述引线框架上低端栅极引脚134之间形成电性连接。配合参见图4、图7及图10所示,由于所述低端MOSFET芯片22与控制器40分别与低端栅极引脚134电性连接,实现了图1中所示,低端MOSFET芯片22的栅极与控制器40的连接。
请参见图3所示,并配合参见图13所示俯视图;图14所示是图13在A-A’向的剖面图,图15所示是图13在B-B’向的剖面图。
使用金属连接板52(或者也可以是金属连接带之类的金属连接体)实现低端MOSFET芯片22的顶部源极221与低端源极引脚133之间的电性连接(图13),使在塑封封装上述整个堆叠的封装体结构后,不仅可以外露该封装体结构的底部与Vin端连接,还可以外露所述金属连接板52的顶部表面与Gnd端连接,以改善半导体封装的热性能,同时有效降低该半导体封装的厚度。
实施例2
配合参见俯视图(图16)、A-A’向的剖面图(图17)和B-B’向的剖面图(图18)所示,本实施例所述用于直流-直流转换器的封装体结构,具有与实施例1中类似的堆叠结构,在引线框架顶部的第一载片台11的第一部分和第二部分上,分别粘接贴附高端MOSFET芯片21及控制器40。在本实施例中第一载片台11的第一部分和第二部分相互分离。当然,也可选用第一部分和第二部分相互连接的第一载片台。
高端MOSFET芯片21通过若干连接引线51键合,在其顶部栅极与高端栅极引脚132之间、顶部源极与高端源极引脚131之间分别形成电性连接。控制器40通过若干连接引线51键合,分别与第一载片台11、若干控制引脚135、低端栅极引脚134,以及高端MOSFET芯片21的顶部栅极形成电性连接。
在引线框架的第二载片台12及高端MOSFET芯片21的顶部设置导电的中间联结件30,并在中间联结件30上设置低端MOSFET芯片22,通过中间联结件30电性连接高端MOSFET芯片21的顶部源极与低端MOSFET芯片22的底部漏极。
与上述实施例1的不同点在于,本实施例中所述引线框架上第一载片台11与第二载片台12厚度一致。
所述中间联结件30包含一体设置的第一联结部31和第二联结部32,使第一联结部31粘接贴附到第一载片台11的高端MOSFET芯片21顶面之后的厚度,与第二联结部32粘接贴附在第二载片台12顶面之后的厚度一致。具体通过该第一联结部31实现高端MOSFET芯片21的顶部源极与低端MOSFET芯片22的底部漏极的电性连接。
对比图10与图16所示,本实施例中固定设置在中间联结件30上的低端MOSFET芯片22面积增大至覆盖或超出高端MOSFET芯片21及控制器40上方的整个区域,使在同样大的引线框架上,低端MOSFET芯片22的尺寸能够充分扩展,因而有效提高半导体器件的产品性能。
如图17所示,低端MOSFET芯片22超出中间联结件31的至少一个边沿延伸到控制器40上方的分区域,由于所述第一联结部31不覆盖控制器40,使控制器40上方与低端MOSFET芯片22的空隙中,能够容纳上述控制器40与高端MOSFET芯片21或其他若干引脚的连接引线51。
本实施例中,低端MOSFET芯片22通过若干连接引线51键合,分别实现顶部栅极222与低端栅极引脚134之间、顶部源极221与低端源极引脚133之间的电性连接。
在一些优选的实施例中,所述低端MOSFET芯片22的顶部源极221与低端源极引脚133之间的电性连接,也可以通过如图13所述的金属连接板52、金属连接带等金属连接体实现,使其能够在封装后外露,以改善半导体封装的热性能,同时有效降低该半导体封装的厚度。
综上所述,本发明通过设置厚薄不同的第一、第二载片台,或是通过设置含不同厚薄联结部的中间联结件30,使低端MOSFET芯片22放置到中间联结件30顶面后,能够堆叠在第一载片台11的高端MOSFET芯片21上,并通过中间联结件30连接高端MOSFET芯片21的顶部源极211与低端MOSFET芯片22的底部漏极,以减少直流-直流转换器组装时元件的数量。同时在第一载片台11的控制器40上方、与低端MOSFET芯片22之间的空隙中,能够容纳键合连接控制器40与高端MOSFET芯片21或若干引脚的若干连接引线51,以进一步减小整个半导体封装的尺寸。
本发明由于采用低端MOSFET芯片22通过中间联结件30堆叠至高端MOSFET芯片21和控制器40上方的封装体结构,与图2所示现有技术在引线框架上平铺设置高、低端MOSFET芯片22和控制器40的结构相比,本实施例在同样大的引线框架上,可以充分扩展各器件的尺寸,如将低端MOSFET芯片22面积增大至覆盖整个高端MOSFET芯片21和控制器40上方,能够有效提高半导体器件的产品性能。
本发明还通过金属连接板52、金属连接带等金属连接体,来实现低端MOSFET芯片22的顶部源极与低端源极引脚133之间的电性连接,使该金属连接板52能够在直流-直流转换器塑封封装后外露,以改善半导体封装的热性能,同时有效降低该半导体封装的厚度。
由本发明所述通过设置厚薄不同的载片台,或是设置含不同厚第一联结部31的中间联结件来承载并电性连接若干元器件的结构,可以方便地将各种半导体芯片、控制器、电感或电容等元器件堆叠,使其能被封装在同一个半导体封装中,以扩展本发明形成各种其他半导体器件。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。

Claims (13)

1.一种用于直流-直流转换器的封装体结构,其特征在于,包含:
分别具有底部漏极、顶部栅极和顶部源极的高端MOSFET芯片(21)和低端MOSFET芯片(22);
引线框架,其设置有第一载片台(11)和第二载片台(12);
所述高端MOSFET芯片(21)设置在第一载片台(11)上,使其底部漏极与所述第一载片台(11)形成电性连接;
控制器(40),也设置在所述第一载片台(11)上,其与所述高端MOSFET芯片(21)的顶部栅极电性连接;
导电的中间联结件(30),其设置在所述第二载片台(12)及高端MOSFET芯片(21)上,并与所述高端MOSFET芯片(21)的顶部源极(211)电性连接;
所述低端MOSFET芯片(22)设置在所述中间联结件(30)上,其顶部栅极与所述控制器(40)电性连接;其底部漏极与所述中间联结件(30)的顶面电性连接,即与所述高端MOSFET芯片(21)的顶部源极(211)电性连接;
所述中间联结件(30)不覆盖所述控制器(40),使在所述控制器(40)上方、与所述低端MOSFET芯片(22)之间存在空隙。
2.如权利要求1所述用于直流-直流转换器的封装体结构,其特征在于,所述第二载片台(12)的厚度大于所述第一载片台(11)的厚度。
3.如权利要求2所述用于直流-直流转换器的封装体结构,其特征在于,所述第二载片台(12)的厚度与所述第一载片台(11)上堆叠了高端MOSFET芯片(21)后的厚度一致。
4.如权利要求1所述用于直流-直流转换器的封装体结构,其特征在于,所述导电的中间联结件(30)包含一体设置的第一联结部(31),以及厚于所述第一联结部(31)的第二联结部(32);
所述第二联结部(32)设置在第二载片台(12)上;
所述第一联结部(31)设置在所述第一载片台(11)的高端MOSFET芯片(21)上,使在所述高端MOSFET芯片(21)的顶部源极(211)通过该第一联结部(31),与所述低端MOSFET芯片(22)的底部漏极之间形成电性连接。
5.如权利要求4所述用于直流-直流转换器的封装体结构,其特征在于,所述第一联结部(31)设置在所述第一载片台(11)的高端MOSFET芯片(21)顶面之后的厚度,与所述第二联结部(32)设置在第二载片台(12)顶面之后的厚度一致。
6.如权利要求3或5所述用于直流-直流转换器的封装体结构,其特征在于,所述引线框架上还设置有与所述第一载片台(11)、第二载片台(12)分隔且无电性连接的若干引脚,包含若干低端源极引脚(133)、低端栅极引脚(134)、高端源极引脚(131)、高端栅极引脚(132)以及控制引脚(135)。
7.如权利要求6所述用于直流-直流转换器的封装体结构,其特征在于,所述高端MOSFET芯片(21)通过若干连接引线(51)键合,分别在其顶部栅极(212)与高端栅极引脚(132)之间、顶部源极(211)与高端源极引脚(131)之间分别形成电性连接。
8.如权利要求6所述用于直流-直流转换器的封装体结构,其特征在于,所述控制器(40)通过若干连接引线(51)键合,分别与所述第一载片台(11)、若干控制引脚(135)、低端栅极引脚(134),以及高端MOSFET芯片(21)的顶部栅极(212)形成电性连接。
9.如权利要求8所述用于直流-直流转换器的封装体结构,其特征在于,所述低端MOSFET芯片(22)通过若干连接引线(51)键合,使其顶部栅极(222)与所述低端栅极引脚(134)之间形成电性连接,即与所述控制器(40)之间也形成电性连接。
10.如权利要求8所述用于直流-直流转换器的封装体结构,其特征在于,所述低端MOSFET芯片(22),覆盖所述中间联结件(30)和控制器(40)顶部的部分或全部区域。
11.如权利要求10所述用于直流-直流转换器的封装体结构,其特征在于,所述控制器(40)上方、与所述低端MOSFET芯片(22)之间的空隙中,容纳所述键合连接控制器(40)与高端MOSFET芯片(21)或控制引脚(135)的若干连接引线(51)。
12.如权利要求6所述用于直流-直流转换器的封装体结构,其特征在于,所述低端MOSFET芯片(22)通过若干连接引线(51)键合,使其顶部源极(221)与所述低端源极引脚(133)之间形成电性连接。
13.如权利要求6所述用于直流-直流转换器的封装体结构,其特征在于,还包含若干金属连接板(52),来电性连接所述低端MOSFET芯片(22)的顶部源极(221)与所述低端源极引脚(133),使所述金属连接板(52)得以暴露在所述封装体结构的表面之外。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515336A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装、芯片布置、电路板以及用于制造芯片封装的方法
CN104103617A (zh) * 2013-04-02 2014-10-15 英飞凌科技奥地利有限公司 多层半导体封装
CN104347568A (zh) * 2013-08-07 2015-02-11 万国半导体股份有限公司 多芯片混合封装的半导体器件及其制备方法
CN104576558A (zh) * 2013-10-21 2015-04-29 快捷韩国半导体有限公司 电源模块封装体
CN104795385A (zh) * 2014-01-20 2015-07-22 钰创科技股份有限公司 系统级包装模块和系统级包装模块的制造方法
CN104882426A (zh) * 2014-02-27 2015-09-02 西安永电电气有限责任公司 一种塑封式ipm模块堆叠式结构
CN105355606A (zh) * 2015-09-28 2016-02-24 杰群电子科技(东莞)有限公司 一种新型系统级封装
CN107924901A (zh) * 2015-05-04 2018-04-17 创研腾科技有限公司 薄型底脚功率封装
US11469205B2 (en) 2013-03-09 2022-10-11 Adventive International Ltd. Universal surface-mount semiconductor package

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224945A1 (en) * 2004-04-09 2005-10-13 Kabushiki Kaisha Toshiba Power semiconductor device package
US20060169976A1 (en) * 2005-01-07 2006-08-03 Kabushiki Kaisha Toshiba Semiconductor device
US20060186514A1 (en) * 2005-02-22 2006-08-24 Stats Chippac Ltd. Package stacking lead frame system
CN101140926A (zh) * 2006-09-07 2008-03-12 万国半导体股份有限公司 层迭式双金属氧化物半导体场效应晶体管包
CN101419964A (zh) * 2007-10-26 2009-04-29 英飞凌科技股份公司 具有多个半导体芯片的装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224945A1 (en) * 2004-04-09 2005-10-13 Kabushiki Kaisha Toshiba Power semiconductor device package
US20060169976A1 (en) * 2005-01-07 2006-08-03 Kabushiki Kaisha Toshiba Semiconductor device
US20060186514A1 (en) * 2005-02-22 2006-08-24 Stats Chippac Ltd. Package stacking lead frame system
CN101140926A (zh) * 2006-09-07 2008-03-12 万国半导体股份有限公司 层迭式双金属氧化物半导体场效应晶体管包
CN101419964A (zh) * 2007-10-26 2009-04-29 英飞凌科技股份公司 具有多个半导体芯片的装置

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515336A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装、芯片布置、电路板以及用于制造芯片封装的方法
US9859198B2 (en) 2012-06-27 2018-01-02 Infineon Technologies Ag Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages
US11469205B2 (en) 2013-03-09 2022-10-11 Adventive International Ltd. Universal surface-mount semiconductor package
CN104103617A (zh) * 2013-04-02 2014-10-15 英飞凌科技奥地利有限公司 多层半导体封装
CN104103617B (zh) * 2013-04-02 2018-01-26 英飞凌科技奥地利有限公司 多层半导体封装
CN104347568B (zh) * 2013-08-07 2017-03-01 万国半导体股份有限公司 多芯片混合封装的半导体器件及其制备方法
CN104347568A (zh) * 2013-08-07 2015-02-11 万国半导体股份有限公司 多芯片混合封装的半导体器件及其制备方法
CN104576558A (zh) * 2013-10-21 2015-04-29 快捷韩国半导体有限公司 电源模块封装体
CN104795385B (zh) * 2014-01-20 2017-09-08 钰创科技股份有限公司 系统级包装模块和系统级包装模块的制造方法
CN104795385A (zh) * 2014-01-20 2015-07-22 钰创科技股份有限公司 系统级包装模块和系统级包装模块的制造方法
CN104882426A (zh) * 2014-02-27 2015-09-02 西安永电电气有限责任公司 一种塑封式ipm模块堆叠式结构
CN107924901A (zh) * 2015-05-04 2018-04-17 创研腾科技有限公司 薄型底脚功率封装
CN105355606A (zh) * 2015-09-28 2016-02-24 杰群电子科技(东莞)有限公司 一种新型系统级封装
CN105355606B (zh) * 2015-09-28 2019-05-28 杰群电子科技(东莞)有限公司 一种新型系统级封装

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