CN104009013A - 具有单独的管芯间互连的多管芯封装 - Google Patents
具有单独的管芯间互连的多管芯封装 Download PDFInfo
- Publication number
- CN104009013A CN104009013A CN201410068362.4A CN201410068362A CN104009013A CN 104009013 A CN104009013 A CN 104009013A CN 201410068362 A CN201410068362 A CN 201410068362A CN 104009013 A CN104009013 A CN 104009013A
- Authority
- CN
- China
- Prior art keywords
- electrode
- tube core
- metal layer
- core
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/414—Connecting portions
- H01L2224/4141—Connecting portions the connecting portions being stacked
- H01L2224/41421—Connecting portions the connecting portions being stacked on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
- H01L2224/84815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/84986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了具有单独的管芯间互连的多管芯封装。第一半导体管芯的第一侧处的第一电极连接到衬底的第一导电区。第二半导体管芯的第一侧处的第一电极连接到衬底的第二导电区。每个管芯具有在各自管芯的相反的第二侧处的第二电极。第一金属层从衬底的外围区延伸以在第一管芯之上。第一金属层具有总体矩形横截面积,并且将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极。与第一金属层分离的第二金属层在第一和第二管芯上延伸。第二金属层具有总体矩形横截面积,并且将第一和第二管芯的第二电极相连接。
Description
技术领域
本申请涉及多管芯封装,并且更具体地涉及多管芯封装中的管芯间互连。
背景技术
电子部件的集成密度的增加和相关联的对封装的热与电传导性的较大要求需要具有更好热与电传导性的新连接技术,并且还需要用于对应连接元件的新构造技术。近年来,替代丝焊的金属夹已经用于在半导体管芯(芯片)电极与引线框架之间提供电连接。金属夹在引线框架与管芯电极之间提供大面积连接,从而相对于丝焊允许封装的电和热属性的增加。然而,常规金属夹互连在工艺性能方面具有较大限制,尤其是当在单个封装中使用多个管芯时。常规地,单个金属夹用于将两个或更多管芯的电极连接到一个封装中的相同电位。由于所密封的管芯的不同电极拓扑和其他考虑,在多管芯封装中实现此类单夹管芯间连接是有问题的。常规单夹管芯间互连限制半导体管芯在外壳内的设计和布置,并且不允许管芯在组件中旋转,特别是当金属夹较大时。
发明内容
根据多管芯封装的实施例,该多管芯封装包括:衬底,其具有多个导电区;和第一半导体管芯,其具有第一和第二相反的侧、在第一侧处连接到导电区的第一导电区的第一电极以及在第二侧处的第二电极。该多管芯封装还包括第二半导体管芯,其具有第一和第二相反的侧、在第一侧处连接到导电区的第二导电区的第一电极以及在第二侧处的第二电极。第一金属层从衬底的外围区延伸以在第一管芯之上。第一金属层具有总体矩形横截面积,并且将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极。与第一金属层分离的第二金属层在第一和第二管芯上延伸。第二金属层具有总体矩形横截面积,并且将第一管芯的第二电极连接到和第二管芯的第二电极。
根据制造多管芯封装的方法的实施例,该方法包括:提供具有多个导电区的衬底;将第一半导体管芯的第一侧处的第一电极连接到导电区的第一导电区,第一管芯具有在第一管芯的相反的第二侧处的第二电极;将第二半导体管芯的第一侧处的第一电极连接到导电区的第二导电区,第二管芯具有在第二管芯的相反的第二侧处的第二电极;经由第一金属层将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极,第一金属层从衬底的外围区延伸以在第一管芯之上并且具有总体矩形横截面积;以及经由第二金属层将第一管芯的第二电极连接到第二管芯的第二电极,第二金属层与第一金属层分离、在第一和第二管芯上延伸并且具有总体矩形横截面积。
在阅读以下详细描述之后并且在查看附图之后,本领域技术人员将认识到附加的特征和优点。
附图说明
图中的部件不一定是按比例的,代之以将重点放在说明本发明的原理上。此外,在图中,相同的参考数字指明对应部分。在图中:
图1示出了根据实施例的多管芯封装的自顶向下的平面视图;
图2示出了图1的多管芯封装的沿标记为A-A’的线的横截面视图;
图3示出了通过图1的封装中包括的部件来实现的半桥转换器电路的示例性电路图;
图4示出了密封后的图1的多管芯封装的沿标记为A-A’的线的横截面视图;
图5示出了根据另一实施例的多管芯封装的自顶向下的平面视图;以及
图6示出了根据再另一实施例的多管芯封装的自顶向下的平面视图。
具体实施方式
本文描述的实施例使用单独金属夹或具有总体矩形横截面积的其他类型的金属层来将两个半导体管芯的电极连接到一个封装中的相同电位,并且使用附加的金属夹或金属层来将管芯连接到封装中包括的引线框架或其他类型的衬底。如本文所使用的术语“金属层”意图包括金属夹或具有总体矩形横截面积的其他大面积互连,诸如在半导体管芯封装中使用的金属丝带(metal ribbons)。金属夹典型地用导电性胶粘剂焊接或粘合到其他结构,而金属丝带典型地被超声接合。如本文所使用的术语“总体矩形横截面积”意图意指具有与例如圆形或椭圆形横截面形状相对的矩形或准矩形形状的横截面积,圆形或椭圆形横截面形状典型地与丝焊连接相关联。
本文中描述的管芯间连接可以通过以下方式来实现:将金属层的一端连接到管芯的电极,并将该金属层的相反端连接到相同封装中的另一管芯的电极。任一管芯电极也可以连接到封装中包括的引线框架/衬底以完成该特定管芯的电互连。连接到管芯的相同电极的单独金属层可以安排在不同平面中或者在相同平面中相互分离开。在每种情况中,两个金属层的一端以堆叠或分离开的方式连接到相同管芯电极。
本文描述的管芯间连接在封装内的管芯布局和管芯互连布置方面提供了更大的灵活性,因为至少两个单独的金属层用于将管芯连接到一个封装中的相同电位。例如,将两个或更多管芯连接到相同电位的单独金属层可以以不同角度来定向以允许更大的集成灵活性。一般地,本文描述的管芯间连接提供部件电路的高级别的集成和容易的3-D集成,通过提供双侧冷却来改进散热,减小电阻,并且归因于更安全管芯接触的使用而增加了部件可靠性。
图1示出了密封之前的多管芯封装的自顶向下的平面视图,并且图2示出了图1中沿标记为A-A’的线的封装的横截面视图。该封装包括具有导电区102的衬底100。在一个实施例中,衬底100是引线框架,并且导电区102是引线框架的不同区段。在另一实施例中,衬底100是具有导电区102的电路板。在再另一实施例中,衬底100是诸如陶瓷材料的电绝缘体,其具有安置在该体上的导电区102。可以使用具有导电区102的再其他衬底100。
在每种情况中,衬底100的导电区102提供用于包括在封装中的半导体管芯的电连接的点。在图1中示出的纯示例性实施例中,诸如IGBT(绝缘栅双极晶体管)、MOSFET(金属氧化物场效应晶体管)或JFET(结型场效应晶体管)或二极管管芯的两个晶体管半导体管芯104、106与电容器108一起包括在封装中。
仅仅为了解释和说明的方便,图1的封装中包括的部件实现的电路是如图3中所示的半桥转换器电路。该半桥电路包括低侧晶体管(LS)、高侧晶体管(HS)和耦合在半桥电路的正输入(Vin+)与负输入(Vin-)之间的输入电容器(Cin)。在一些配置中,负输入可以是地。低侧晶体管LS对应于图1和2中示出的管芯之一104,高侧晶体管HS对应于另一管芯106,并且输入电容器Cin对应于电容器部件108。在图3中示出的示例性电路图中,晶体管是MOSFET,每个晶体管具有栅极(G)、漏极(D)和源极(S)端子。
低侧晶体管LS的栅极、漏极和源极端子对应于图1中示出的低侧晶体管管芯104的栅极、源极和漏极电极110、112、114。高侧晶体管HS的栅极、漏极和源极端子对应于高侧晶体管管芯106的栅极、源极和漏极电极116、118、120。高侧晶体管HS的漏极端子电连接到半桥电路的正输入(Vin+)。高侧晶体管HS的源极端子电连接到低侧晶体管LS的漏极端子以形成半桥电路的输出(Vout)。低侧晶体管LS的源极端子电连接到负输入(Vin-)。晶体管栅极用作控制信号输入(IN1、IN2)。IGBT可以替代MOSFET被使用,其中IGBT的集电极连接将对应于MOSFET的漏极连接,并且IGBT的发射极连接将对应于MOSFET的源极连接。在任一情况中,半桥电路的正输入端子(Vin+)、负输入端子(Vin-)和输出端子(Vout)对应于图1中示出的衬底100的导电区102中不同的一个。一般地,封装中包括的半导体管芯的类型和数量取决于封装被设计用于的具体应用,并且本文描述的管芯间互连实施例可以用在每一种情况中。
每一个半导体管芯104、106具有在管芯104、106的每一侧的一个或多个电极。例如,低侧晶体管管芯104在管芯104面对衬底100的侧具有栅极电极110和源极电极112,并且在管芯104背对衬底100的侧具有漏极电极114。在相反方式中,高侧晶体管管芯106在管芯106面对衬底100的侧具有漏极电极120,并且在管芯106背对衬底100的侧具有栅极电极116和源极电极118。根据该实施例,低侧晶体管管芯104具有所谓的“倒装芯片”配置。可以使用其他管芯配置。接下来描述的是至在管芯104、106面对衬底100的侧处的电极110、112、120的连接。
低侧晶体管管芯104的源极电极112例如通过焊料122连接到衬底100的电连接到半桥电路的负输入(Vin-)的导电区102。电容器部件108面对衬底100的侧也例如通过焊料124连接到衬底100的也电连接到Vin-的导电区102。低侧晶体管管芯104的栅极电极110例如通过焊料126连接到衬底100的电连接到低侧晶体管104的栅极输入的导电区102。高侧晶体管管芯106的漏极电极120例如通过焊料128连接到衬底100的电连接到半桥电路的正输入(Vin+)的导电区102。电容器部件108背对衬底100的侧例如通过接合线(bond wire)130与高侧晶体管管芯106的漏极电极120连接到衬底100的相同的导电区102。电容器部件108的该侧还例如通过接合线130连接到衬底100的外围区中的另一导电区102。接下来描述的是至管芯104、106背对衬底100的侧处的电极114、116、118的连接。
具有总体矩形横截面积的第一金属层132从衬底100的外围区延伸以在高侧晶体管管芯106之上。第一金属层132将高侧晶体管管芯106的源极电极118连接到衬底100的外围区中被指明为半桥电路的输出(Vout)的导电区102。在图1和2中示出的实施例中,第一金属层132是通过焊料134在一端连接到衬底100的导电区102并且通过焊料136在相反端连接到高侧晶体管管芯106的源极电极118的金属夹。在其他实施例中,第一金属层132是代替金属夹的具有总体矩形横截面积的金属丝带。
与第一金属层132相分离而且也具有总体矩形横截面积的第二金属层138在低侧和高侧晶体管管芯104、106上延伸。第二金属层138将高侧晶体管管芯106的源极电极118连接到低侧晶体管管芯104的漏极电极114。在图1和2中示出的实施例中,第二金属层138是通过焊料140在一端连接到低侧晶体管管芯104的漏极电极114并且通过焊料142在相反端连接到第一金属层132的连接到高侧晶体管管芯106的源极电极118的端的金属夹。在其他实施例中,第二金属层138是代替金属夹的具有总体矩形横截面积的金属丝带。与第一和第二金属层132、138相分离而且也具有总体矩形横截面积的第三金属层144将低侧晶体管管芯104的漏极电极114连接到衬底100的外围区中的导电区102。
根据图1和2中示出的实施例,第一金属层132具有(经由焊料134)在一端连接到衬底100的外围区中的导电区102的较小区段(minor section)131。第一金属层132的较小区段131延伸远离衬底100。第一金属层132还具有从较小区段131的相反端延伸到高侧晶体管管芯106的源极电极118的较大区段(major section)133。第二金属层138类似地具有(经由焊料140)在一端连接到低侧晶体管管芯104的漏极电极114的较小区段137。第二金属层138的较小区段137延伸远离低侧晶体管管芯104。第二金属层138还具有从较小区段137的相反端延伸到第一金属层132背对高侧晶体管管芯106的侧的较大区段139。在一个实施例中,第一和/或第二金属层132、138的较小和较大区段131、133、137、139具有单个连续构造。第一和第二金属层132、138的较大区段133、139的每一个在一些实施例中可以具有至少150μm的厚度,或者在其他实施例中具有至少200μm的厚度。
图4示出了在向封装应用密封材料146后的图1中示出的多管芯封装的沿标记为A-A’的线的横截面视图。衬底100、管芯104、106、电容器108和金属层132、134被密封材料146密封。多管芯封装可以是如图1、2和4中所示的无引线封装或者具有引线。
在每种情况中并且根据图1、2和4中所示出的实施例,第一金属层132具有连接到高侧晶体管管芯106的源极电极118的第一侧和连接到第二金属层138的与第一侧相反的第二侧。根据该实施例,第一金属层132在第一平面中延伸,并且第二金属层138在不同于第一平面的第二平面中与第一金属层132平行地延伸。
图5示出了与图1中示出的实施例类似的另一多管芯封装的自顶向下的平面视图,然而,第二金属层138以介于5°与90°之间的角度(θ)从第一金属层132延伸。在一个实施例中,θ介于30°与45°之间。在另一实施例中,θ约为90°。此外,与图1相比较,电容器部件108与低侧晶体管管芯104的位置在图5中进行了交换,从而示出了使用多于一个金属层132、138将不同管芯104、106连接到相同电位(例如,Vout)的另一优点。如果单个金属层替代地用于将高侧晶体管管芯106的源极电极118和低侧晶体管管芯104的漏极电极114连接到相同电位(例如,Vout),则电容器部件108与低侧晶体管管芯140的位置不能交换。
图6示出了与图1中示出的实施例类似的再另一多管芯封装的自顶向下的平面视图,然而,第一和第二金属层132、138在相同平面中延伸并且在该平面中彼此分离开。根据该实施例,第一金属层132连接到高侧晶体管管芯106的源极电极118的第一部分,并且第二金属层138连接到相同的源极电极118的第二不同部分。此外,根据该实施例,第二金属层138可以是具有均匀平面构造的单个体。
诸如“之下”、“下方”、“下部”、“之上”、“上部”等的空间上的相对术语用于方便描述以解释一个元件相对于第二元件的定位。除了与图中描绘的那些不同的定向之外,这些术语还意图涵盖设备的不同定向。此外,诸如“第一”、“第二”等的术语也用于描述各种元件、区、区段等,并且也不意图是限制性的。相同的术语贯穿说明书指代相同的元素。
如本文所使用的,术语“具有”、“包含”、“包括”(including、comprising)等是开放式术语,其指示存在所声明的元素或特征,但是不排除附加的元素或特征。除非上下文清楚地另有所指,否则冠词“一”、“一个”和“该”意图包括复数以及单数。
对于以上考虑的变型和应用的范围,应当理解,本发明并不受前面的描述的限制,其也不受附图的限制。相反,本发明仅由所附权利要求及其法律等同物来限定。
Claims (21)
1. 一种多管芯封装,包括:
衬底,其具有多个导电区;
第一半导体管芯,其具有第一和第二相反的侧、在第一侧处连接到导电区的第一导电区的第一电极以及在第二侧处的第二电极;
第二半导体管芯,其具有第一和第二相反的侧、在第一侧处连接到导电区的第二导电区的第一电极以及在第二侧处的第二电极;
第一金属层,其从衬底的外围区延伸以在第一管芯之上,第一金属层具有总体矩形横截面积,并且将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极;以及
第二金属层,其与第一金属层分离并且在第一和第二管芯上延伸,第二金属层具有总体矩形横截面积,并且将第一管芯的第二电极连接到第二管芯的第二电极。
2. 根据权利要求1所述的多管芯封装,其中,第一金属层具有连接到第一管芯的第二电极的第一侧和连接到第二金属层的与第一侧相反的第二侧。
3. 根据权利要求1所述的多管芯封装,其中,第一金属层连接到第一管芯的第二电极的第一部分,并且第二金属层连接到第一管芯的第二电极的不同于第一部分的第二部分。
4. 根据权利要求1所述的多管芯封装,其中,第一金属层在平面中延伸,并且第二金属层在相同平面中与第一金属层分离开。
5. 根据权利要求1所述的多管芯封装,其中,第一金属层在第一平面中延伸,并且第二金属层在不同于第一平面的第二平面中与第一金属层平行地延伸。
6. 根据权利要求5所述的多管芯封装,其中第二金属层以介于5°与90°之间的角度从第一金属层延伸。
7. 根据权利要求6所述的多管芯封装,其中第二金属层以介于30°与45°之间的角度从第一金属层延伸。
8. 根据权利要求6所述的多管芯封装,其中第二金属层以约90°的角度从第一金属层延伸。
9. 根据权利要求1所述的多管芯封装,其中,第一金属层包括连接到导电区的在衬底的外围区中的一个导电区并且延伸远离衬底的较小区段,和从较小区段延伸到第一管芯的第二电极的较大区段。
10. 根据权利要求9所述的多管芯封装,其中,第一金属层的较小和较大区段具有单个连续构造。
11. 根据权利要求1所述的多管芯封装,其中,第二金属层包括连接到第二管芯的第二电极并且延伸远离第二管芯的较小区段,和从较小区段延伸到第一金属层背对第一管芯的侧的较大区段。
12. 根据权利要求11所述的多管芯封装,其中,第二金属层的较小和较大区段具有单个连续构造。
13. 根据权利要求1所述的多管芯封装,其中,第二金属层是具有均匀平面构造的单个体。
14. 根据权利要求1所述的多管芯封装,其中,第一金属层是具有焊接到导电区的在衬底的外围区中的一个导电区的第一端和焊接到第一管芯的第二电极的第二端的金属夹,并且其中,第二金属层是具有焊接到第一管芯的第二电极的第一端和焊接到第二管芯的第二电极的第二端的金属夹。
15. 根据权利要求1所述的多管芯封装,还包括密封材料,其密封衬底、第一管芯、第二管芯、第一金属层以及第二金属层。
16. 根据权利要求1所述的多管芯封装,其中:
第一管芯是半桥转换器电路的低侧晶体管,并且第二管芯是半桥转换器电路的高侧晶体管;
第一管芯的第一电极是低侧晶体管的源极电极;
第一管芯的第二电极是低侧晶体管的漏极电极;
第二管芯的第一电极是高侧晶体管的漏极电极;
第二管芯的第二电极是高侧晶体管的源极电极;
第一金属层将衬底的指明为半桥转换器电路的输出的导电区连接到低侧晶体管的漏极电极;以及
第二金属层将低侧晶体管的漏极电极连接到高侧晶体管的源极电极。
17. 一种制造多管芯封装的方法,所述方法包括:
提供具有多个导电区的衬底;
将第一半导体管芯的第一侧处的第一电极连接到导电区的第一导电区,第一管芯具有在第一管芯的相反的第二侧处的第二电极;
将第二半导体管芯的第一侧处的第一电极连接到导电区的第二导电区,第二管芯具有在第二管芯的相反的第二侧处的第二电极;
经由第一金属层将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极,第一金属层从衬底的外围区延伸以在第一管芯之上并且具有总体矩形横截面积;以及
经由第二金属层将第一管芯的第二电极连接到第二管芯的第二电极,第二金属层与第一金属层分离、在第一和第二管芯上延伸并且具有总体矩形横截面积。
18. 根据权利要求17所述的方法,其中,将导电区的在衬底的外围区中的一个导电区连接到第一管芯的第二电极包括:
将第一金属层的较小区段连接到衬底的外围区中的导电区,较小区段延伸远离衬底;以及
将第一金属的较大区段连接到第一管芯的第二电极,第一金属层的较小和较大区段是连续的。
19. 根据权利要求17所述的方法,其中,经由第二金属层将第一管芯的第二电极连接到第二管芯的第二电极包括:
将第一金属层的第一侧连接到第一管芯的第二电极;以及
将第一金属层的相反的第二侧连接到第二金属层。
20. 根据权利要求17所述的方法,其中,经由第二金属层将第一管芯的第二电极连接到第二管芯的第二电极包括:
将第一金属层连接到第一管芯的第二电极的第一部分;以及
将第二金属层连接到第一管芯的第二电极的不同于第一部分的第二部分。
21. 根据权利要求17所述的方法,其中,第一金属层是第一金属夹并且第二金属层是第二金属夹,并且其中,经由第二金属层将第一管芯的第二电极连接到第二管芯的第二电极包括:
将第一金属夹的第一端焊接到导电区的在衬底的外围区中的一个导电区;
将第一金属夹的第二端焊接到第一管芯的第二电极;
将第二金属夹的第一端焊接到第一管芯的第二电极;以及
将第二金属夹的第二端焊接到第二管芯的第二电极。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/778,801 US9054040B2 (en) | 2013-02-27 | 2013-02-27 | Multi-die package with separate inter-die interconnects |
US13/778,801 | 2013-02-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104009013A true CN104009013A (zh) | 2014-08-27 |
Family
ID=51349637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410068362.4A Pending CN104009013A (zh) | 2013-02-27 | 2014-02-27 | 具有单独的管芯间互连的多管芯封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9054040B2 (zh) |
CN (1) | CN104009013A (zh) |
DE (1) | DE102014102364A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106158734A (zh) * | 2014-10-03 | 2016-11-23 | 力祥半导体股份有限公司 | 半导体封装装置 |
CN108933116A (zh) * | 2017-05-24 | 2018-12-04 | 英飞凌科技股份有限公司 | 具有引线框的半导体封装 |
TWI716455B (zh) * | 2016-04-20 | 2021-01-21 | 美商艾馬克科技公司 | 形成具有導電的互連框的半導體封裝之方法及結構 |
CN114678279A (zh) * | 2021-01-27 | 2022-06-28 | 北京新能源汽车股份有限公司 | 半导体器件及其制作方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101977994B1 (ko) | 2013-06-28 | 2019-08-29 | 매그나칩 반도체 유한회사 | 반도체 패키지 |
US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
US9806053B2 (en) | 2013-10-11 | 2017-10-31 | Mediatek Inc. | Semiconductor package |
US9147664B2 (en) * | 2013-10-11 | 2015-09-29 | Mediatek Inc. | Semiconductor package |
US9392696B2 (en) | 2013-10-11 | 2016-07-12 | Mediatek Inc. | Semiconductor package |
DE102018124497B4 (de) * | 2018-10-04 | 2022-06-30 | Infineon Technologies Ag | Halbleitervorrichtung und Verfahren zum Bilden einer Halbleitervorrichtung |
DE102020119611A1 (de) | 2020-07-24 | 2022-01-27 | Infineon Technologies Ag | Schaltungsanordnung und verfahren zum bilden einer schaltungsanordnung |
US11842957B2 (en) * | 2020-12-29 | 2023-12-12 | Nxp Usa, Inc. | Amplifier modules and systems with ground terminals adjacent to power amplifier die |
JP7538097B2 (ja) * | 2021-09-13 | 2024-08-21 | 株式会社東芝 | 半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6255722B1 (en) * | 1998-06-11 | 2001-07-03 | International Rectifier Corp. | High current capacity semiconductor device housing |
US6677669B2 (en) | 2002-01-18 | 2004-01-13 | International Rectifier Corporation | Semiconductor package including two semiconductor die disposed within a common clip |
US6946740B2 (en) | 2002-07-15 | 2005-09-20 | International Rectifier Corporation | High power MCM package |
DE10301091B4 (de) | 2003-01-14 | 2015-01-22 | Infineon Technologies Ag | Leistungs-Halbleiterbauelement und Verfahren zur Verbindung von einem gemeinsamen Substratträger zugeordneten Halbleitereinrichtungen |
US7208818B2 (en) | 2004-07-20 | 2007-04-24 | Alpha And Omega Semiconductor Ltd. | Power semiconductor package |
CN101073151B (zh) * | 2004-12-20 | 2010-05-12 | 半导体元件工业有限责任公司 | 具有增强散热性的半导体封装结构 |
US7285849B2 (en) | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US7804131B2 (en) | 2006-04-28 | 2010-09-28 | International Rectifier Corporation | Multi-chip module |
US7808102B2 (en) * | 2006-07-28 | 2010-10-05 | Alpha & Omega Semiconductor, Ltd. | Multi-die DC-DC boost power converter with efficient packaging |
DE102007013186B4 (de) | 2007-03-15 | 2020-07-02 | Infineon Technologies Ag | Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben |
US7851908B2 (en) | 2007-06-27 | 2010-12-14 | Infineon Technologies Ag | Semiconductor device |
US7800208B2 (en) | 2007-10-26 | 2010-09-21 | Infineon Technologies Ag | Device with a plurality of semiconductor chips |
US8193618B2 (en) | 2008-12-12 | 2012-06-05 | Fairchild Semiconductor Corporation | Semiconductor die package with clip interconnection |
US8344464B2 (en) | 2011-05-19 | 2013-01-01 | International Rectifier Corporation | Multi-transistor exposed conductive clip for high power semiconductor packages |
US8436429B2 (en) | 2011-05-29 | 2013-05-07 | Alpha & Omega Semiconductor, Inc. | Stacked power semiconductor device using dual lead frame and manufacturing method |
-
2013
- 2013-02-27 US US13/778,801 patent/US9054040B2/en active Active
-
2014
- 2014-02-24 DE DE201410102364 patent/DE102014102364A1/de not_active Ceased
- 2014-02-27 CN CN201410068362.4A patent/CN104009013A/zh active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106158734A (zh) * | 2014-10-03 | 2016-11-23 | 力祥半导体股份有限公司 | 半导体封装装置 |
CN106158734B (zh) * | 2014-10-03 | 2019-01-08 | 力祥半导体股份有限公司 | 半导体封装装置 |
TWI716455B (zh) * | 2016-04-20 | 2021-01-21 | 美商艾馬克科技公司 | 形成具有導電的互連框的半導體封裝之方法及結構 |
CN108933116A (zh) * | 2017-05-24 | 2018-12-04 | 英飞凌科技股份有限公司 | 具有引线框的半导体封装 |
CN108933116B (zh) * | 2017-05-24 | 2023-12-05 | 英飞凌科技股份有限公司 | 具有引线框的半导体封装 |
CN114678279A (zh) * | 2021-01-27 | 2022-06-28 | 北京新能源汽车股份有限公司 | 半导体器件及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140240945A1 (en) | 2014-08-28 |
DE102014102364A1 (de) | 2014-08-28 |
US9054040B2 (en) | 2015-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104009013A (zh) | 具有单独的管芯间互连的多管芯封装 | |
JP6765469B2 (ja) | パワーモジュール半導体装置 | |
US10041979B2 (en) | Method of sensing current flowing in a power module | |
US10854589B2 (en) | Semiconductor device | |
US9312211B2 (en) | Semiconductor device and manufacturing method thereof | |
US9240371B2 (en) | Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module | |
US9147648B2 (en) | Multi-die power semiconductor device packaged on a lead frame unit with multiple carrier pins and a metal clip | |
CN101990709A (zh) | 层叠的功率转换器结构和方法 | |
US8476752B2 (en) | Package structure for DC-DC converter | |
JP7183594B2 (ja) | 半導体装置 | |
TW201921613A (zh) | 電子裝置 | |
US7872348B2 (en) | Semiconductor device | |
US9041170B2 (en) | Multi-level semiconductor package | |
US9275944B2 (en) | Semiconductor package with multi-level die block | |
KR101644913B1 (ko) | 초음파 용접을 이용한 반도체 패키지 및 제조 방법 | |
WO2021200138A1 (ja) | 半導体装置 | |
CN103426853A (zh) | 具有引线框架和层压基板的封装电路 | |
JP2020064980A (ja) | 半導体モジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140827 |
|
RJ01 | Rejection of invention patent application after publication |