CN101140926A - 层迭式双金属氧化物半导体场效应晶体管包 - Google Patents

层迭式双金属氧化物半导体场效应晶体管包 Download PDF

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CN101140926A
CN101140926A CNA2007101482374A CN200710148237A CN101140926A CN 101140926 A CN101140926 A CN 101140926A CN A2007101482374 A CNA2007101482374 A CN A2007101482374A CN 200710148237 A CN200710148237 A CN 200710148237A CN 101140926 A CN101140926 A CN 101140926A
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contact pin
tube core
field effect
effect transistor
mos field
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CN100495702C (zh
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圣杰·哈佛纳
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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Abstract

本发明公开了一种层迭式双MOSFET包。该集成电路包包括：第一传导接片；一个高端MOSFET管芯，它跟第一传导接片的耦合使得该高端MOSFET管芯的漏极电耦合到第一传导接片；第二传导接片，它以复层关系电耦合到该高端MOSFET管芯的源极；一个低端MOSFET管芯，它跟第二传导接片的耦合使得该低端MOSFET管芯的漏极电耦合到第二传导接片；第一引线，耦合到该高端MOSFET管芯的门极；至少一个第二引线，耦合到第一传导接片；至少一个第三引线，耦合到低端MOSFET管芯的源极；第四引线，耦合到低端MOSFET管芯的门极；以及密封外壳，用来包装：第一传导接片的各部分、高端MOSFET管芯、第二传导接片的各部分、低端MOSFET管芯、和第一引线、至少一个第二引线、至少一个第三引线、和第四引线的各部分。

Description

层迭式双金属氧化物半导体场效应晶体管包
技术领域
本发明涉及一种功率半导体(集成电路)包，特别是涉及一种层迭式双MOSFET(金属氧化物半导体场效应晶体管)包。
背景技术
在一些开关电路，诸如同步降压变流器、半桥式变流器和逆变器中，两个功率MOSFET可以互补方式切换。图1中所示一般的开关电路110中，包括两个MOSFET 100和150串联接在电压源105上，通常分别称这两个MOSFET 100和150为高端和低端MOSFET。
为了启动一个切换周期，首先关断低端MOSFET 150。这就迫使MOSFET150的体二极管开通并驱动其电流。经延迟后，使高端MOSFET 100开通，并迫使其体二极管关断。然而，该体二极管的关断过程导致其恢复电流陡然截止。该恢复电流流过寄生电感LDHS、LSHS、LDLS、和LSLS，以及流过开关电路110的痕量电感LTRCS、LTRCH和LTRCL。
在这些电感中的电流的陡然截止导致开关电路110内严重振荡，通常称为响铃。在切换途径中这些电感也减慢了切换速度并造成额外的损耗。当切换频率连续增加，这些损耗变得更大，从而限制了开关电路110的性能。
现有技术有各种办法来减小引线电感。例如有些现有技术方案将高端和低端MOSFET两管芯互相并排靠着包装在一起并在包内用导线连接它们。这样一起包装减小了部分外界的痕量电感，但并未完全消除它们。
现有技术已知将两个MOSFET管芯层迭起来并夹入金属接片夹层。例如在属于Estacio的美国专利No.6777786中披露的半导体器件包括安装在铅座上的层迭管芯，在属于Joshi的美国专利No.7029947中披露的翻转式芯片为铅模压包内含二管芯。而在Kuo等人的美国专利申请号No.2001/0052641中披露的功率半导体器件包括了上、下二管芯。虽然这些参考文献披露了层迭MOSFET管芯，这类层迭限于在包中只有单个MOSFET，其目的仅在于减少连接导线的数目和制造成本。即使这些方案包括了层迭两个管芯，顶上的管芯是翻转倒置的以便让管芯最后可连接在一起成为单一的MOSFET器件。现有技术还没有这种努力来层迭一双MOSFET以互补方式运作。
因此需要一种克服现有技术局限性的技术来实现层迭的双MOSFET包。也有需要让层迭的双MOSFET包来实施双MOSFET互补切换方式的电路，例如用于同步降压变流器、半桥式变流器和逆变器中。还有需要使层迭的双MOSFET包的引线和连接电感最小化到现有技术无法实现的水平。也有需要使层迭的双MOSFET包具有较高的效率并且减少在切换运作时的响铃问题。
发明内容
本发明提供的层迭式双MOSFET包克服了现有技术的局限并且实现了所述各项目标，其中将高端MOSFET的源极在一个切换或相位节点处从内部短路连接到低端MOSFET的漏极，而该节点又被线引出该包。该包还包括高端MOSFET的漏极和门极的引出线，和低端MOSFET的门极和源极的引出线。
按照本发明的一方面的一种层迭式双MOSFET包包括：第一传导接片；一个高端MOSFET管芯，它跟第一传导接片的耦合使得该高端MOSFET管芯的漏极电耦合到第一传导接片；第二传导接片，它以复层关系电耦合到该高端MOSFET管芯的源极；一个低端MOSFET管芯，它跟第二传导接片的耦合使得该低端MOSFET管芯的漏极电耦合到第二传导接片；第一引线，用来耦合到该高端MOSFET管芯的门极；至少一个第二引线，用来耦合到该高端MOSFET管芯的漏极；至少一个第三引线，用来耦合到低端MOSFET管芯的源极；第四引线，用来耦合到低端MOSFET管芯的门极；以及密封外壳，用来包装：第一传导接片的各部分、高端MOSFET管芯、第二传导接片的各部分、低端MOSFET管芯、和第一引线、该至少一个第二引线、该至少一个第三引线、和第四引线的各部分。
按照本发明的另一方面，一种制备层迭式双MOSFET包的方法包括以下步骤：形成第一传导接片；层迭高端MOSFET管芯到第一传导接片上，使得该高端MOSFET管芯的漏极接点耦合到第一传导接片；以复层关系层迭第二传导接片到该高端MOSFET管芯上，使得该高端MOSFET管芯的源极接点耦合到第二传导接片；层迭低端MOSFET管芯到第二传导接片上，使得该低端MOSFET管芯的漏极接点耦合到第二传导接片。
以上对本发明的较为重要的特征做了广泛而纲要的叙述，使得后面的详细叙述得到更好理解，并且使本发明对于技术的贡献得到更好欣赏。当然，本发明的各个附加特征将在后面叙述，并且构成后面的权利要求的主题。
为此，在对于至少一个实施方案做详细解释前，首先得理解，本发明并不限于应用于后面叙述的或在附图中显示的功能组件的细节和这些组件的配置。本发明还可能有别的实施方案和各种实现和执行方式。也要理解这里所用的措辞和术语、乃至摘要，只是为了描述的目的，不得视为限制性的。
对此，本领域的技术人员会理解并且运用以这里披露的概念为基础，来设计别的方法和系统，以达到本发明的各个目标。所以，重要的是应该将各权利要求看成包含了这类等价方案，只要它们没有脱离本发明的精神和范围。
附图说明
图1为现有技术的同步降压变流器的电路模型；
图2为本发明的层迭式双MOSFET包的侧视概图；
图3为本发明的层迭式双MOSFET包的顶视概图；
图4为按照本发明的方法的流程图。
具体实施方式
参照图2的本发明的层迭式双MOSFET包(常称为200)的简图，它包括一个金属的或别的导热材料的接片210附着在一个高端MOSFET管芯230的顶面220上。该高端MOSFET管芯230的漏极(图中未示出)电耦合到该传导接片210。另一个金属的或类似的导热材料的相位接片240层迭到该高端MOSFET管芯230的顶上，并且附着在高端MOSFET管芯230的源极(图中未示出)。相位接片240包括一个层迭到该高端MOSFET管芯230的顶上的薄的部分241和一个厚的部分243。
一个低端MOSFET管芯250层迭到传导相位接片240的顶面245，使得低端MOSFET管芯250的漏极(图中未示出)电与热连接到传导接片240。传导接片210的底面215和传导相位接片240的底面247如图示设置成一平面使二接片分别处于层迭式双MOSFET包的底部。传导相位接片240既从高端MOSFET管芯230也从低端MOSFET管芯250载走热量。
参照图3的层迭式双MOSFET包的较佳实施例，图标300，它包括一个金属的或类似的导热材料的相位接片310，其第一段313具有底面(图中未示出)跟包300的底面平齐。第一段313的一部分315伸出了该包的封壳380并可连接到散热器(图中未示出)。相位接片310的较薄的第二段317的底面(图中未示出)的平面设置得高于包300的底面，以容纳高端MOSFET管芯330和其下设的Vin传导接片340。
Vin传导接片340的底面(图中未示出)跟传导相位接片310的底面在同一平面。高端MOSFET管芯330电连接到Vin传导接片340的顶面341，以使得高端MOSFET管芯330的漏极电耦合于Vin传导接片340。传导相位接片310的第二段317设置在高端MOSFET管芯330的顶面跟低端MOSFET管芯350的底面之间，以使得高端MOSFET管芯330的源极电耦合于低端MOSFET管芯350的漏极。如图示高端MOSFET管芯330的位置跟传导相位接片310错开来使得高端MOSFET管芯的门极接点不会被传导相位接片310盖住。
层迭式双MOSFET包300可包括D-PAK或D2-PAK类型的包，至少有4个管脚。高端MOSFET管芯330的漏极可用Vin传导接片340耦合到两个引线361和363。二引线361和363如在本实施例所示可融合到一起成为一个引线。高端MOSFET管芯330的门极可用常规连接线351或导电夹耦合到引线360。低端MOSFET管芯350的源极接点可用常规连接线352或导电夹耦合到引线365和367。低端MOSFET管芯350的门极接点可用常规连接线353或导电夹耦合到引线369。
参照图4，按照本发明的层迭式双MOSFET包的制备方法400包括步骤410来形成Vin传导接片。在步骤420将高端MOSFET管芯层迭到Vin传导接片上以使得高端MOSFET管芯的漏极耦合到Vin传导接片。可用焊胶或导电环氧树脂将高端MOSFET管芯固定在Vin传导接片上。在步骤430将传导相位接片层迭到高端MOSFET管芯上以使得高端MOSFET管芯的源极接点耦合到传导相位接片。可用焊胶或导电环氧树脂将传导相位接片固定在高端MOSFET管芯上。在步骤440将低端MOSFET管芯层迭到传导相位接片上以使得低端MOSFET管芯的漏极耦合到传导相位接片上。可用焊胶或导电环氧树脂将低端MOSFET管芯固定在传导相位接片上。在接下来的步骤450用连接导线连接高端MOSFET管芯的门极和低端MOSFET管芯的门极及源极到包上相应的各引线，最后在步骤460用注塑材料进行封装。这一新颖的方法400使得提供的包中所有功率连接都是零电感，而低端MOSFET管芯的源极连接则是例外。
通过层迭低端MOSFET管芯到高端MOSFET管芯上并采用公共的接片来做它们之间的相位节点连接，就消除了大部分跟组件互联和引线相关的电感。用作低端和高端的两个MOSFET管芯可以都是N型，或都是P型，或彼此互补的极性。这两个MOSFET管芯的参数可以是性能全同的或不对称的并经优化了来执行高、低端的切换。低端MOSFET管芯还可包括一个集成的Schottky整流器以便进一步改进其性能。此二MOSFET管芯可采用各种模塑封装来形成常规的包型，例如D-PAK、D2-PAK、多引线TO-220或任何别的包型设计。
当然，应该理解，以上所述的是本发明的较佳实施例，可以做出各种改变，而并不脱离如在以下的权利要求书所表达的本发明的精神和范围。

Claims (18)

1.一种层迭式双金属氧化物半导体场效应晶体管包，其特征在于，包括以下部分：
第一传导接片；
一个高端金属氧化物半导体场效应晶体管管芯，它跟第一传导接片的耦合使得该高端金属氧化物半导体场效应晶体管管芯的漏极电耦合到第一传导接片；
第二传导接片，它以跟高端金属氧化物半导体场效应晶体管的复层关系电耦合到该高端金属氧化物半导体场效应晶体管管芯的源极；
一个低端金属氧化物半导体场效应晶体管管芯，它跟第二传导接片的耦合使得该低端金属氧化物半导体场效应晶体管管芯的漏极电耦合到第二传导接片；
第一引线，耦合到该高端金属氧化物半导体场效应晶体管管芯的门极；
至少一个第二引线，耦合到第一传导接片；
至少一个第三引线，耦合到低端金属氧化物半导体场效应晶体管管芯的源极；
第四引线，耦合到低端金属氧化物半导体场效应晶体管管芯的门极；密封外壳，用来包装：第一传导接片的各部分、高端金属氧化物半导体场效应晶体管管芯、第二传导接片的各部分、低端金属氧化物半导体场效应晶体管管芯、和第一引线、如上文所述的至少一个第二引线、如上文所述的至少一个第三引线、和第四引线的各部分。
2.如权利要求1所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中第二传导接片覆盖高端金属氧化物半导体场效应晶体管管芯的方式让高端金属氧化物半导体场效应晶体管管芯的门极接点得以暴露出来。
3.如权利要求1所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中第二传导接片包括一个相位接片。
4.如权利要求1所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中第二传导接片伸出了封装外壳。
5.如权利要求1所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中第二传导接片包括一个较薄部分和一个较厚部分。
6.如权利要求5所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中所述较薄部分覆盖了高端金属氧化物半导体场效应晶体管管芯。
7.如权利要求1所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中第二传导接片包括一个较薄部分和一个较厚部分，该较厚部分的底面跟第一传导接片的底面设置在同一个平面。
8.如权利要求7所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中所述较厚部分的底面跟第一传导接片的底面包括两个传导接片。
9.如权利要求8所述的层迭式双金属氧化物半导体场效应晶体管包，其特征在于，其中所述两个传导接片暴露到封装外壳的底面外。
10.一种制备层迭式双金属氧化物半导体场效应晶体管包的方法，其特征在于，包括下列步骤：
形成第一传导接片；
将高端金属氧化物半导体场效应晶体管管芯层迭到第一传导接片上以使得高端金属氧化物半导体场效应晶体管管芯的漏极接点耦合到第一传导接片；
以覆盖关系将第二传导接片层迭到高端金属氧化物半导体场效应晶体管管芯上以使得高端金属氧化物半导体场效应晶体管管芯的源极接点耦合到第二传导接片；
将低端金属氧化物半导体场效应晶体管管芯层迭到第二传导接片上以使得低端金属氧化物半导体场效应晶体管管芯的漏极接点耦合到第二传导接片上。
11.如权利要求10所述的方法，其特征在于，其中第二传导接片覆盖高端金属氧化物半导体场效应晶体管管芯的方式让高端金属氧化物半导体场效应晶体管管芯的门极接点得以暴露出来。
12.如权利要求10所述的方法，其特征在于，其中第二传导接片包括一个相位接片。
13.如权利要求10所述的方法，其特征在于，还包括密封包装第一传导接片、高端金属氧化物半导体场效应晶体管管芯、低端金属氧化物半导体场效应晶体管管芯、和第二传导接片的一部分。
14.如权利要求10所述的方法，其特征在于，其中第二传导接片包括较薄部分和较厚部分。
15.如权利要求14所述的方法，其特征在于，其中较薄部分覆盖高端金属氧化物半导体场效应晶体管管芯。
16.如权利要求10所述的方法，其特征在于，其中第二传导接片包括较薄部分和较厚部分，该较厚部分的底面跟第一传导接片的底面设置在同一个平面。
17.如权利要求16所述的方法，其特征在于，其中较厚部分的底面跟第一传导接片的底面包括两个传导接片。
18.如权利要求17所述的方法，其特征在于，其中所述两个传导接片暴露到封装外壳的底面外。
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