CN204102895U - 半导体封装结构 - Google Patents
半导体封装结构 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000007731 hot pressing Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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Abstract
一种半导体封装结构,包含引线框架、高侧N型晶体管、低侧N型晶体管、第一连接片及第二连接片。引线框架包含电源输入板、接地板及相位板。高侧N型晶体管设置于电源输入板上。低侧N型晶体管设置于接地板上。第一连接片设置于高侧N型晶体管及低侧N型晶体管上,其中高侧N型晶体管透过第一连接片电性连接低侧N型晶体管。第二连接片位于低侧N型晶体管及相位板上,其中低侧N型晶体管透过第二连接片电性连接相位板。由于第一连接片及第二连接片可以是双点连接,故半导体封装结构可具有良好的可靠度。
Description
技术领域
本实用新型是有关于一种半导体封装结构。
背景技术
近年来,随着集成电路技术的进步,相关的电子产品也越来越多样化。其中的功率晶体管由于具有高集成密度、相当低的静态漏电流以及不断提升的功率容量,因此目前被广泛应用在开关电源和变频器等领域。
举例而言,功率晶体管可应用在转换器上。转换器可包含多个功率晶体管,通过控制各个功率晶体管的开启或关闭,可将输入电压转换为不同的输出电压,例如可将输入电压转换为较低的输出电压,达到降压的目的。然而在结构上,功率晶体管彼此之间,或者是功率晶体管本身与其他元件之间会有电性连接的需求。但目前现有的电性连接方式存在有可靠度较差的问题。因此,如何能够提升电性连接的可靠度成为本技术领域有待解决的课题之一。
实用新型内容
本实用新型的目的在于提供一种新颖的半导体封装结构,其包含引线框架、高侧N型晶体管、低侧N型晶体管、第一连接片(clip)以及第二连接片(clip),其中第一连接片及第二连接片可以是双点连接,可靠度佳,而可解决本领域目前所面临的问题。
本实用新型提供的半导体封装结构包含引线框架、高侧N型晶体管、低侧N型晶体管、第一连接片及第二连接片。引线框架包含一电源输入板、一接地板及一相位板。高侧N型晶体管设置于电源输入板上。低侧N型晶体管设置于接地板上。第一连接片设置于高侧N型晶体管及低侧N型晶体管上,其中高侧N型晶体管透过第一连接片电性连接低侧N型晶体管。第二连接片位于低侧N型晶体管及相位板上,其中低侧N型晶体管透过第二连接片电性连接相位板。
根据本实用新型的一实施例,低侧N型晶体管的源极面向并电性连接接地板。
根据本实用新型的一实施例,高侧N型晶体管的漏极面向并电性连接电源输入板。
根据本实用新型的一实施例,高侧N型晶体管的源极电性连接第一连接片。
根据本实用新型的一实施例,低侧N型晶体管的漏极电性连接第一连接片及第二连接片。
根据本实用新型的一实施例,第一连接片与第二连接片彼此分离。
根据本实用新型的一实施例,第一连接片与第二连接片至少部分相互重叠。
根据本实用新型的一实施例,第一连接片的上视形状与第二连接片的上视形状互补。
根据本实用新型的一实施例,半导体封装结构还包含一封装材料层包覆高侧N型晶体管及低侧N型晶体管,并露出第一连接片的一部分、第二连接片的一部分或其组合。
根据本实用新型的一实施例,第一连接片及第二连接片皆为铜片。
根据本实用新型的一实施例,第二连接片的一侧视形状为Z形。
附图说明
图1是依照本实用新型的一实施例的转换器的电路示意图;
图2是依照本实用新型的一实施例的半导体封装结构的剖面示意图;
图3是依照本实用新型的一实施例的半导体封装结构的上视示意图;
图4是依照本实用新型的另一实施例的半导体封装结构的上视示意图;
图5是依照本实用新型的又一实施例的半导体封装结构的上视示意图;
图6是依照本实用新型的另一实施例的半导体封装结构的剖面示意图;
图7是依照本实用新型的又一实施例的半导体封装结构的剖面示意图。
具体实施方式
以下将以附图揭露本实用新型的多个实施例,为明确说明起见,许多实务上的细节将在以下叙述中一并说明。然而,应了解到,这些实务上的细节不应用以限制本实用新型。也就是说,在本实用新型部分实施例中,这些实务上的细节是非必要的。此外,为简化附图起见,一些已知惯用的结构与元件在附图中将以简单示意的方式绘示。
本实用新型提供一种半导体封装结构,其可应用在转换器上。图1是依照本实用新型的一实施例的转换器的电路图。在一实施例中,此转换器为直流-直流转换器(DC-DC converter)。在一实施例中,此转换器通过高侧N型晶体管HS及低侧N型晶体管LS将输入电压转为较低的输出电压。在一实施例中,一驱动芯片(未绘示)可透过驱动电路分别控制高侧N型晶体管HS的栅极及低侧N型晶体管LS的栅极的开启或关闭,以将输入电压转换为较低的输出电压。在一实施例中,驱动芯片可以与脉冲宽度调变(pulse-width modulation,PWM)控制芯片整合为一个控制器。
在一实施例中,如图1所示,高侧N型晶体管HS的漏极电性连接引线框架的电源输入板112,以取得工作电压。低侧N型晶体管LS的源极电性连接引线框架的接地板114。高侧N型晶体管HS的源极与低侧N型晶体管LS的漏极电性连接引线框架的相位板116,以输出电压。在一实施例中,高侧N型晶体管HS及低侧N型晶体管LS与驱动电路整合在一起,而构成整合驱动型金属氧化物半导体场效晶体管(driver MOS,DrMOS)。当然,在其他实施例中,高侧N型晶体管HS及低侧N型晶体管LS亦可不与驱动电路整合在一起。
图2是依照本实用新型的一实施例的半导体封装结构的剖面示意图。图3是依照本实用新型的一实施例的半导体封装结构的上视示意图。以下请参照图2-3,半导体封装结构包含引线框架110、高侧N型晶体管HS、低侧N型晶体管LS、第一连接片(clip)120及第二连接片(clip)130。引线框架110包含电源输入板112、接地板114及相位板116。
高侧N型晶体管HS设置于电源输入板112上,因此高侧N型晶体管HS在运作过程中产生的大量热能可透过电源输入板112散出。在一实施例中,高侧N型晶体管HS透过导电粘着层140粘接电源输入板112。在其他实施例中,高侧N型晶体管透过热压而与电源输入板接着。在一实施例中,高侧N型晶体管HS的漏极面向并电性连接电源输入板112,以取得工作电压。在一实施例中,高侧N型晶体管HS为沟渠式晶体管。
低侧N型晶体管LS设置于接地板114上,因此低侧N型晶体管LS在运作过程中产生的大量热能可透过接地板114散出。在一实施例中,低侧N型晶体管LS透过导电粘着层140粘接接地板114。在其他实施例中,低侧N型晶体管透过热压而与接地板接着。在一实施例中,低侧N型晶体管LS的源极面向并电性连接接地板114。在一实施例中,低侧N型晶体管LS为横向双扩散金属氧化物半导体场效晶体管(lateral double-diffused MOS,LDMOS)。在一实施例中,低侧N型晶体管LS为沟渠式晶体管。
第一连接片120设置于高侧N型晶体管HS及低侧N型晶体管LS上。高侧N型晶体管HS透过第一连接片120电性连接低侧N型晶体管LS。在一实施例中,高侧N型晶体管HS的源极电性连接第一连接片120。在一实施例中,高侧N型晶体管HS的源极透过第一连接片120电性连接低侧N型晶体管LS的漏极。在一实施例中,高侧N型晶体管HS透过导电粘着层140粘接第一连接片120,而低侧N型晶体管LS透过另一导电粘着层140粘接第一连接片120。在其他实施例中,第一连接片通过热压而与高侧N型晶体管及低侧N型晶体管接着。在一实施例中,第一连接片120为铜片(或称铜薄板),例如可为铜箔。
第二连接片130位于低侧N型晶体管LS及相位板116上。低侧N型晶体管LS透过第二连接片130电性连接相位板116。在一实施例中,低侧N型晶体管LS的漏极透过第二连接片130电性连接相位板116。在一实施例中,低侧N型晶体管LS的漏极电性连接第一连接片120及第二连接片130。在一实施例中,低侧N型晶体管LS透过导电粘着层140粘接第一连接片120及第二连接片130。在其他实施例中,第二连接片通过热压而与低侧N型晶体管及相位板接着。在本实施例中,第一连接片120与第二连接片130彼此分离。在一实施例中,第二连接片130为铜片,例如可为铜箔。在一实施例中,第二连接片130的侧视形状为Z形,以便于粘接或连接相位板116。也就是说,第二连接片130具有足够的面积与相位板116粘着,而可避免脱落。
值得注意的是,第一连接片120以及第二连接片130可以是双点连接。因此相较于单一个连接元件连接三点(例如连接高侧N型晶体管、低侧N型晶体管与相位板)而言,第一连接片120及第二连接片130的可靠度更佳。这是因为连接元件在连接这三点时或连接这三点之后,容易发生翘曲、连接不良或甚至脱落等现象,导致可靠度降低,或甚至无法使用。但本实用新型的第一连接片120及第二连接片130因为是双点连接,因此不会有前述问题产生。此外,相较于一般的打线,第一连接片120以及第二连接片130所需的空间较小,而可缩短高侧N型晶体管HS及低侧N型晶体管LS的距离。
在一实施例中,第一连接片120与第二连接片130皆为铜片(或称铜薄板);相较于铝带,铜片的导电能力较佳。在一实施例中,第一连接片120与第二连接片130的厚度为约25微米至75微米,但不限于此。
在一实施例中,半导体封装结构还包含封装材料层150包覆高侧N型晶体管HS及低侧N型晶体管LS,以阻隔水气腐蚀高侧N型晶体管HS及低侧N型晶体管LS。此外,封装材料层150可露出第一连接片120的一部分、第二连接片130的一部分或其组合,以帮助散热。如图2所示,封装材料层150露出第一连接片120的一部分与第二连接片130的一部分,以帮助散热,但本实用新型不限于此。
图4是依照本实用新型的另一实施例的半导体封装结构的上视示意图。特别的是,第一连接片120的上视形状与第二连接片130的上视形状互补。因为第一连接片120与第二连接片130具有相互对应的上视形状,所以在制程对位时十分方便,使第一连接片120及第二连接片130可分别被准确地设置在高侧N型晶体管HS与低侧N型晶体管LS上,以及低侧N型晶体管LS与相位板116上。
图5是依照本实用新型的又一实施例的半导体封装结构的上视示意图。在本实施例中,第一连接片120的上视形状亦与第二连接片130的上视形状互补,所以在制程对位时可使第一连接片120及第二连接片130分别被准确地设置在高侧N型晶体管HS与低侧N型晶体管LS上,以及低侧N型晶体管LS与相位板116上。
图6是依照本实用新型的另一实施例的半导体封装结构的剖面示意图。图6与图2的差异在于,图6的第一连接片120与第二连接片130至少部分相互重叠,且第一连接片120位于第二连接片130的上方。因此在一实施例中,高侧N型晶体管HS的源极是透过堆叠的第一连接片120与第二连接片130电性连接低侧N型晶体管LS的漏极。
图7是依照本实用新型的又一实施例的半导体封装结构的剖面示意图。图7与图2的差异在于,图7的第一连接片120与第二连接片130至少部分相互重叠,且第一连接片120位于第二连接片130的下方。因此在一实施例中,低侧N型晶体管LS的漏极是透过堆叠的第一连接片120与第二连接片130电性连接相位板116。
综合上述,本实用新型提供一种半导体封装结构,可通过第一连接片及第二连接片进行双点连接。相较于单一个连接元件连接三点,第一连接片及第二连接片的双点连接的可靠度较佳。此外,第一连接片及第二连接片可为铜片,故其导电表现较为优异。
虽然本实用新型已以实施例揭露如上,然其并非用以限定本实用新型,任何熟悉此技艺者,在不脱离本实用新型的精神和范围内,当可作各种的更动与润饰,因此本实用新型的保护范围当视所附的权利要求书所界定的范围为准。
Claims (11)
1.一种半导体封装结构,其特征在于,包含:
一引线框架,包含一电源输入板、一接地板及一相位板;
一高侧N型晶体管,设置于该电源输入板上;
一低侧N型晶体管,设置于该接地板上;
一第一连接片,设置于该高侧N型晶体管及该低侧N型晶体管上,其中该高侧N型晶体管透过该第一连接片电性连接该低侧N型晶体管;以及
一第二连接片,位于该低侧N型晶体管及该相位板上,其中该低侧N型晶体管透过该第二连接片电性连接该相位板。
2.根据权利要求1所述的半导体封装结构,其特征在于,该低侧N型晶体管的源极面向并电性连接该接地板。
3.根据权利要求1所述的半导体封装结构,其特征在于,该高侧N型晶体管的漏极面向并电性连接该电源输入板。
4.根据权利要求1所述的半导体封装结构,其特征在于,该高侧N型晶体管的源极电性连接该第一连接片。
5.根据权利要求1所述的半导体封装结构,其特征在于,该低侧N型晶体管的漏极电性连接该第一连接片及该第二连接片。
6.根据权利要求1所述的半导体封装结构,其特征在于,该第一连接片与该第二连接片彼此分离。
7.根据权利要求1所述的半导体封装结构,其特征在于,该第一连接片与该第二连接片至少部分相互重叠。
8.根据权利要求1所述的半导体封装结构,其特征在于,该第一连接片的上视形状与该第二连接片的上视形状互补。
9.根据权利要求1所述的半导体封装结构,其特征在于,还包含一封装材料层包覆该高侧N型晶体管及该低侧N型晶体管,并露出该第一连接片的一部分、该第二连接片的一部分或其组合。
10.根据权利要求1所述的半导体封装结构,其特征在于,该第一连接片及该第二连接片皆为铜片。
11.根据权利要求1所述的半导体封装结构,其特征在于,该第二连接片的一侧视形状为Z形。
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CN106505058A (zh) * | 2016-12-05 | 2017-03-15 | 嘉盛半导体(苏州)有限公司 | 半导体多芯片模块系统 |
TWI619226B (zh) * | 2015-01-15 | 2018-03-21 | 力祥半導體股份有限公司 | 半導體封裝裝置 |
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TWI619226B (zh) * | 2015-01-15 | 2018-03-21 | 力祥半導體股份有限公司 | 半導體封裝裝置 |
CN106505058A (zh) * | 2016-12-05 | 2017-03-15 | 嘉盛半导体(苏州)有限公司 | 半导体多芯片模块系统 |
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