CN102623425B - 包括两个半导体芯片的器件及其制造 - Google Patents

包括两个半导体芯片的器件及其制造 Download PDF

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CN102623425B
CN102623425B CN201210018556.4A CN201210018556A CN102623425B CN 102623425 B CN102623425 B CN 102623425B CN 201210018556 A CN201210018556 A CN 201210018556A CN 102623425 B CN102623425 B CN 102623425B
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semiconductor chip
contact pad
section
metal level
metal
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CN102623425A (zh
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H.埃韦
S.兰多
J.马勒
A.普吕克尔
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L2924/30107—Inductance

Abstract

本发明涉及包括两个半导体芯片的器件及其制造。一种器件包括：第一半导体芯片，在第一面上具有第一接触垫；以及第二半导体芯片，在第一面上具有第一接触垫。所述第二半导体芯片被放置在所述第一半导体芯片之上，其中，所述第一半导体芯片的第一面面向所述第二半导体芯片的第一面。唯一导电材料层被布置在所述第一半导体芯片与所述第二半导体芯片之间。唯一导电材料层将所述第一半导体芯片的第一接触垫电耦合至所述第二半导体芯片的第一接触垫。

Description

包括两个半导体芯片的器件及其制造
技术领域
本发明的实施例涉及一种包括两个半导体芯片的器件。本发明的实施例还涉及一种制造包括两个半导体芯片的器件的方法。
背景技术
对于高度系统集成来说，将集成电路、传感器、微机械设备或其他组件一个堆叠到另一个上是有益的。在器件内将越多组件堆叠在彼此之上，在电路板上就需要越少的面积来布置该器件。
附图说明
附图被包括进来以提供对实施例的进一步理解，并且并入本说明书并构成本说明的一部分。附图示意了实施例并与该描述一起用于解释实施例的原理。其他实施例以及实施例的许多预期优势将随着通过参照以下详细描述变得更好理解而被容易地认识到。附图的元素不必相对于彼此按比例绘制。相似的参考标记表示对应的类似部分。
图1示意性地示出了包括堆叠在彼此上的两个半导体芯片的器件的一个实施例的横截面视图；
图2A-2I示意性地示出了一种制造器件的方法的一个实施例的俯视图和横截面视图，该方法包括将若干半导体芯片堆叠在彼此上以及将介电箔层压在半导体芯片上；
图3示意性地示出了包括电路板和在电路板上安装的器件的系统的一个实施例的横截面视图；
图4示出了半桥电路的基本电路；
图5A-5D示意性地示出了一种制造器件的方法的一个实施例的横截面视图，该方法包括将若干半导体芯片堆叠在彼此上以及通过电沉积（galvanic deposition）来产生外部接触元件；
图6A-6D示意性地示出了一种制造器件的方法的一个实施例的横截面视图，该方法包括将若干半导体芯片堆叠在结构化引线框上；
图7示意性地示出了包括电路板和在电路板上安装的器件的系统的一个实施例的横截面视图；
图8A-8D示意性地示出了一种制造器件的方法的一个实施例的横截面视图，该方法包括将若干半导体芯片堆叠在引线框上以及通过使用接合线将半导体芯片耦合至引线框；以及
图9示意性地示出了包括电路板和在电路板上安装的器件的系统的一个实施例的横截面视图。
具体实施方式
在以下详细描述中，参照了附图，这些附图形成以下详细描述的一部分，并且其中以示意的方式示出了可实施本发明的具体实施例。在这一点上，参照所描述的附图的定向，使用了方向性术语，如“顶”、“底”、“前”、“后”、“首”、“尾”等等。由于实施例的组件可以以多个不同定向而定位，因此方向性术语用于示意的目的而决不进行限制。应当理解，在不脱离本发明的范围的前提下，可以利用其他实施例并且可以进行结构上或逻辑上的改变。因此，以下详细描述不应视为具有限制意义，并且本发明的范围由所附权利要求限定。
应当理解，这里描述的各个示例性实施例的特征可以相互组合，除非另有具体说明。
本说明书中所采用的术语“耦合的”和/或“电耦合的”并不意在表示元件必须直接耦合在一起；可以在“耦合的”或“电耦合的”元件之间提供介于其间的元件。
以下描述包含一个或多个半导体芯片的器件。半导体芯片可以具有不同类型，可以利用不同技术而制造，并可以包括例如集成电路、光电电路或机电电路或者无源电路。例如，集成电路可以被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储电路或集成无源电路。此外，半导体芯片可以被配置为所谓的MEMS（微机电系统）并可以包括微机械结构，如桥、膜、舌结构。半导体芯片可以被配置为传感器或促动器，例如压力传感器、加速度传感器、旋转传感器、磁场传感器、电磁场传感器、麦克风等。半导体芯片不需要由特定半导体材料（如Si、SiC、SiGe、GaAs）制造，并且此外可以包含非半导体的无机和/或有机材料（如绝缘体、塑料或金属）。此外，半导体芯片可以是封装的或未封装的。
特别地，可以涉及具有垂直结构的半导体芯片，即，半导体芯片可以被制造为使得电流可以沿与半导体芯片的主表面垂直的方向流经半导体材料。具有垂直结构的半导体芯片可以具有特别处于其两个主面上（即，处于其顶侧和底侧）的接触垫。换言之，具有垂直结构的半导体芯片具有有源顶侧和有源底侧。特别地，功率半导体芯片可以具有垂直结构。例如，垂直功率半导体芯片可以被配置为功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结型栅场效应晶体管）、功率双极晶体管或功率二极管。作为示例，功率MOSFET的源电极和栅电极可以位于一个主面上，而功率MOSFET的漏电极布置于另一个主面上。此外，以下描述的器件可以包括用于对功率半导体芯片进行控制的集成电路。
半导体芯片可以具有允许与半导体芯片中包括的集成电路进行电接触的接触垫（或者接触元件或电极）。接触垫可以包括施加于半导体芯片的半导体材料的一个或多个金属层。金属层可以利用任何期望的几何形状和任何期望的材料成分而制造。例如，金属层可以具有覆盖一区域的层的形式。任何期望的金属或金属合金（例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒）可以用作材料。金属层不需要是同质的或由仅一种材料制造，即，金属层中可能包含各种成分和浓度的材料。
以下描述的器件可以包含堆叠在彼此之上的两个半导体芯片。唯一（exactly one）导电材料层可以布置在两个半导体芯片之间。导电材料可以由焊接材料、导电粘合剂和金属纳米粒子之一构成。在一个实施例中，导电材料包含不同组分，例如在粘合剂的情况下的树脂和金属粒子，但是，这些组分均匀地分布在所述唯一层之上。
半导体芯片或半导体芯片的至少部分可以利用介电材料或层压材料而覆盖。该材料可以覆盖器件的组件的任何数目的表面的任意一小部分。介电材料可以是任何适当的层压料（预浸料（prepreg））、硬质塑料、热塑性或热固性材料，并可以包含填充材料。可以采用各种技术，利用介电材料（例如，层压、压缩成型、注射成型、粉末成型或液体成型）来覆盖半导体芯片。可以使用热量和/或压力来施加介电材料。
介电材料可以提供各种功能。例如，其可以用于将器件的组件彼此电绝缘和/或与外部组件电绝缘，而介电材料还可以用作用于安装其他组件（如布线层）的平台。介电材料可以用于产生扇出类型的封装。在扇出类型的封装中，外部接触元件和/或将半导体芯片连接至外部接触元件的导体迹线中的至少一些横向地（laterally）位于半导体芯片的轮廓外，或者至少与半导体芯片的轮廓交叉。因此，在扇出类型的封装中，典型地（附加地），半导体芯片的封装的外围部分用于将该封装电接合至外部应用，如应用板等。相对于半导体芯片的覆盖区，包围半导体芯片的封装的该外部部分有效地扩大了封装的接触面积，从而导致针对后续加工（例如第二级组装）在封装垫大小和间距方面的约束放宽。
以下描述的器件包括外部接触元件，其可以具有任何形状、大小和材料。外部接触元件是可从器件外接近的，从而允许从器件外与半导体芯片进行电接触。此外，外部接触元件可以进行热传导，并可以用作用于耗散由半导体芯片生成的热量的散热器。外部接触元件可以由任何期望的导电材料构成。外部接触元件可以包括外部接触垫。焊接材料可以沉积在外部接触垫上。焊接材料可以具有焊球的形状，并可以例如由SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu和/或SnBi构成。
图1示意性地示出了器件100的横截面视图。器件100包括第一半导体芯片10，第一半导体芯片10具有第一面11和在第一面11上布置的第一接触垫12。此外，器件100包括第二半导体芯片14，第二半导体芯片14具有第一面13和在第一面13上布置的第一接触垫15。第二半导体芯片14被放置在第一半导体芯片10之上，使得第一半导体芯片10的第一面11面向第二半导体芯片14的第一面13。唯一导电材料层16布置在第一半导体芯片10与第二半导体芯片14之间。层16将第一半导体芯片10的第一接触垫12电耦合至第二半导体芯片14的第一接触垫15。
图2A-2I示意性地示出了制造器件200的方法的一个实施例的俯视图和横截面视图，器件20在图2I中示出。器件200是图1所示的器件100的实现。因此，器件200的下述细节同样可以适用于器件100。器件100和200的相似或相同组件由相同的参考标记表示。
图2A示出了沿俯视图中所示的线A-A’的俯视图（顶）和横截面视图（底）中的载体20。载体20可以是引线框并且可以具有任何几何形状。载体20不限于任何大小，例如，载体20可以具有从100 μm至1 mm的范围内的厚度或者甚至可以更厚。载体20可以是导电的并且可以完全由金属（例如，铜）或金属合金（例如，铁镍）制造。载体20可以利用导电材料（例如，铜、银、铁镍或镍磷）而电镀。
图2B示出了在载体20上安装的功率半导体芯片10。在载体20上还可以安装图2B未示出的其他半导体芯片。功率半导体芯片10具有第一面11和与第一面11相对的第二面21。第一接触垫12和第二接触垫22分别布置在第一面11和第二面21上。此外，第三接触垫23布置在第一面11上。接触垫12、22和23中的每一个可以包括对功率半导体芯片10的半导体材料施加的一个或多个金属层。金属层可以利用任何期望的几何形状和任何期望的材料成分而制造。例如，金属层可以具有覆盖一区域的层的形式。任何期望的金属或金属合金（例如，铝、钛、金、银、铜、钯、铂、镍、铬或镍钒）可以用作材料。在一个实施例中，第二接触垫22覆盖功率半导体芯片10的整个第二面21。未形成第一和第三接触垫12、23的一部分的功率半导体芯片10的第一面11的一部分被钝化层24覆盖，钝化层24可以由任何适当的介电金属（例如，聚酰亚胺或氮化硅）制成。
例如，功率半导体芯片10可以是功率二极管或功率晶体管，如功率MOSFET、IGBT、JFET或功率双极晶体管。在图2B示例性示出的功率MOSFET的情况下，第一和第二接触垫12和22可以分别是源和漏电极（负载电极）。在这种情况下，第三电极23充当栅电极（控制电极）。在操作期间，可以在源和漏电极12和22之间施加高至5、50、100、500或1000V或甚至更高的电压。对栅电极23施加的开关频率可以处于从1 kHz至100 MHz的范围内，但也可以处于该范围外。
在载体20上安装了功率半导体芯片10，其第二面21面向载体20。可以规定，唯一导电材料层25布置在载体20与功率半导体芯片10之间。层25具有第一面17和与第一面17相对的第二面18。在第一面17处，层25的导电材料与载体20直接接触。在第二面18处，层25的导电材料与功率半导体芯片10的接触元件22直接接触。层25将功率半导体芯片10的接触垫22电耦合至载体20。此外，层25将功率半导体芯片10稳固地附着至载体20。在将功率半导体芯片10附着至载体20之前，层25可以沉积在接触垫22上、或沉积在载体20上、或者沉积在接触垫22和在载体20这二者上。
在一个实施例中，层25的导电材料仅由软焊接材料、扩散焊接材料、导电粘合剂以及包括金属纳米粒子的膏剂（paste）中的一个或多个构成。在一个实施例中，层25的导电材料包含不同组分，例如，在粘合剂的情况下的树脂和金属粒子，但是，这些组分均匀地分布在层25之上。在层25由焊接材料制成的情况下，可能使用Sn、AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi或Au焊料或其他适当焊接材料。在扩散焊接的情况下，特别地，可以使用AuSn或AgSn。在软焊接的情况下，特别地，可以使用SnPb、SnCuAg或SnAgSb。在功率半导体芯片10已经被放置在载体20之上后，进行加热以熔化焊接材料。可以使用回流焊接、真空焊接、软焊接、扩散焊接或其他焊接技术。如果使用导电粘合剂将功率半导体芯片10安装在载体20上，则粘合剂可以基于环氧树脂并富含金、银、镍或铜以产生导电性。可以将粘合剂加热至特定温度以硬化该粘合剂。在一个实施例中，包含金属纳米粒子和其中分散有金属粒子的液体的膏剂用于将功率半导体芯片10附着至载体20。例如，金属粒子可以由银、金、铜、锡或镍制成。金属粒子的至少一部分（例如，金属粒子的多于20%或30%或40%或50%或60%或70%或80%）可以具有小于100 nm或50 nm或10 nm的直径。可以将金属纳米粒子加热至比制成这些金属纳米粒子的金属的熔化温度低的温度。该温度可以足够高以发起烧结过程，从而在接触垫22与载体20之间形成金属纳米粒子的烧结层。此外，其中分散有金属纳米粒子的液体在温度步骤期间蒸发。在一个实施例中，将金属纳米粒子加热至比制成这些金属纳米粒子的金属的熔化温度高的温度。
第一接触垫12的外形（或轮廓）限定了功率半导体芯片10的第一面11的第一区段26。在功率半导体芯片10的俯视图中，第一区段26由阴影区指示。
图2C示出了在功率半导体芯片10上安装的功率半导体芯片14。功率半导体芯片14具有第一面13和与第一面13相对的第二面32。功率半导体芯片14包括在第一面13上布置的第一接触垫15以及在第二面32上布置的第二和第三接触垫33、34。接触垫15、33和34中的每一个可以包括对功率半导体芯片14的半导体材料施加的一个或多个金属层。在一个实施例中，第一接触垫15覆盖功率半导体芯片14的整个第一面13。例如，功率半导体芯片14可以是功率二极管或功率晶体管，如功率MOSFET、IGBT、JFET或功率双极晶体管。在图2C示例性示出的功率MOSFET的情况下，第一和第二接触垫15和33可以分别是漏和源电极（负载电极）。在这种情况下，第三接触垫34充当栅电极（控制电极）。在操作期间，可以在漏和源电极15和33之间施加高至5、50、100、500或1000V或甚至更高的电压。对栅电极34施加的开关频率可以处于从1 kHz至100 MHz的范围内，但还可以处于该范围外。
在功率半导体芯片10上安装了功率半导体芯片14，其第二面13面向功率半导体芯片10的接触垫12。唯一导电材料层16布置在功率半导体芯片10与功率半导体芯片14之间。层16具有第一面35和与第一面35相对的第二面36。在第一面35处，层16的导电材料与功率半导体芯片10的接触元件12直接接触。在第二面36处，层16的导电材料与功率半导体芯片14的接触元件15直接接触。层16将功率半导体芯片10的接触垫12电耦合至功率半导体芯片14的接触垫15。此外，层16将功率半导体芯片14稳固地附着至功率半导体芯片10。在将功率半导体芯片14附着至功率半导体芯片10之前，层16可以沉积在接触垫12上、或沉积在接触垫15上、或者沉积在接触垫12和15这二者上。
在一个实施例中，层16的导电材料仅由软焊接材料、扩散焊接材料、导电粘合剂以及包括金属纳米粒子的膏剂中的一个或多个构成。在一个实施例中，层16的导电材料包含不同组分，例如，在粘合剂的情况下的树脂和金属粒子，但是，这些组分均匀地分布在层16之上。在层16由焊接材料制成的情况下，可能使用Sn、AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi或Au焊料或其他适当焊接材料。在扩散焊接的情况下，特别地，可以使用AuSn或AgSn。在软焊接的情况下，特别地，可以使用SnPb、SnCuAg或SnAgSb。在功率半导体芯片14已经被放置在功率半导体芯片10之上后，进行加热以熔化焊接材料。可以使用回流焊接、真空焊接、软焊接、扩散焊接或其他焊接技术。如果使用导电粘合剂将功率半导体芯片14安装在功率半导体芯片10上，则粘合剂可以基于环氧树脂并富含金、银、镍或铜以产生导电性。可以将粘合剂加热至特定温度以硬化该粘合剂。在一个实施例中，包含金属纳米粒子和其中分散有金属粒子的液体的膏剂用于将功率半导体芯片14附着至功率半导体芯片10。例如，金属粒子可以由银、金、铜、锡或镍制成。金属粒子的至少一部分（例如，金属粒子的多于20%或30%或40%或50%或60%或70%或80%）可以具有小于100 nm或50 nm或10 nm的直径。可以将金属纳米粒子加热至比制成这些金属纳米粒子的金属的熔化温度低的温度。该温度可以足够高以发起烧结过程，从而在接触垫12和15之间形成金属纳米粒子的烧结层。此外，其中分散有金属纳米粒子的液体在温度步骤期间蒸发。在一个实施例中，将金属纳米粒子加热至比制成这些金属纳米粒子的金属的熔化温度高的温度。在一个实施例中，同时加热层25（以将功率半导体芯片粘合至载体20）和层16（以将功率半导体芯片14粘合至功率半导体芯片10）。
在一个实施例中，将功率半导体芯片14放置在功率半导体芯片10的第一接触垫12上，使得功率半导体芯片14完全布置在第一区段26内。因此，功率半导体芯片14不横向位于第一区段26的轮廓外，并且不与第一区段26的轮廓交叉。在这种情况下，功率半导体芯片14的大小小于功率半导体芯片10的大小。在另一实施例中，功率半导体芯片14至少部分地置于第一区段26外。
图2D示出了在功率半导体芯片10的钝化层24上安装的半导体芯片40。半导体芯片40包括逻辑集成电路，并具有有源面，该有源面包括背向功率半导体芯片10的接触垫41。使用粘合剂42将半导体芯片40附着至钝化层24。
图2E示出了被放置在载体20和半导体芯片10、14和40之上的介电箔45。介电箔45由层压材料制成。介电箔45的顶表面涂覆有金属层46（例如，铜层）。金属层46背向载体20。
图2F示出了将介电箔45层压在载体20和半导体芯片10、14和40之上。介电箔45对半导体芯片10、14和40的顶表面和侧表面进行包封。介电箔45可以由电绝缘聚合物材料制成，该电绝缘聚合物材料可以具有箔或薄片的形状。可以在适于将介电箔45附着至底层结构的时间内施加热量和/或压力。在载体20上布置的组件之间的间隙也填充有介电箔45。例如，介电箔45的聚合物材料可以是作为纤维毡（例如，玻璃或碳纤维）和树脂（例如，硬质塑料）的组合的预浸料。预浸材料通常用于制造PCB。在PCB工业中使用且这里可以用作聚合物材料的公知预浸材料是：FR-2、FR-3、FR-4、FR-5、FR-6、G-10、CEM-1、CEM-2、CEM-3、CEM-4和CEM-5。预浸材料是双级（bi-stage）材料，其在半导体芯片10、14和40上施加并在热处理期间硬化时是灵活的。对于预浸料的层压，相同或相似的过程步骤可以用在PCB制造中。此外，介电箔45与金属层46一起可以是RCC（涂树脂铜）。
图2G示出了介电层45与金属层46一起被结构化为以在介电层45和金属层46中创建多个切掉部（cutout）或透孔47。透孔47暴露了载体20和接触垫12、23、33、34和41的至少部分，使得可以与这些被暴露的区域进行电连接。介电层45和金属层46可以通过蚀刻或使用激光烧蚀而结构化。
图2H示出了填充在介电层45和金属层46中创建的透孔47的金属材料48。金属材料48可以通过化学沉积和/或无电镀和/或电镀工艺而沉积。金属材料48可以是任何适当的金属或金属合金（例如，铜或铝）。金属材料48在介电层45中形成通孔，并将载体20和接触垫12、23、33、34和41电耦合至金属层46。
图2I示出了在结构化步骤之后为了产生器件200的覆盖区的金属层46。为此，将干膜抗蚀剂层压在可光结构化的金属层46（图2I未示出）之上。可以通过暴露于具有合适波长的光，在抗蚀膜中形成凹陷。为此，可以采用经过掩膜的激光束或光暴露。随后，对抗蚀膜进行显影，并蚀刻金属层46的由此暴露的部分。此后，剥去抗蚀膜，仅结构化的金属层46保持在介电层45上，如图2I所示。
金属层46被结构化为使得半导体芯片40的接触垫41耦合至功率半导体芯片10的接触垫23和功率半导体芯片14的接触垫34。这允许半导体芯片40控制功率半导体芯片10和14。
金属层46的其余部分以及金属材料48的顶表面形成外部接触垫50，外部接触垫50允许从器件200的外部电气接近半导体芯片10、14和40。此外，金属层46和金属层48的顶表面形成安装表面51。安装表面51可以用于将器件200安装到另一组件（如电路板）上。
如图2I所示的器件200是扇出类型的封装。介电箔45允许外部接触垫50扩展到半导体芯片10的轮廓外。因此，外部接触垫50不需要布置在半导体芯片10的轮廓内，而是可以分布在更大的区域上。由于介电层45而可用于布置外部接触垫50的增大的区域意味着：外部接触垫50不仅能布置为彼此相距较大距离，而且可布置在此处的外部接触垫50的最大数目与所有外部接触垫50布置在半导体芯片10的轮廓内的情形相比同样增大。
由于半导体芯片10、14和40在器件200内的堆叠，器件200具有相对小的尺寸。此外，半导体芯片10、14和40之间的电连接路径较短，这导致了快速的开关时间。器件200的电阻、电容和电感也减小。此外，可以经由器件200的顶和底表面来耗散半导体芯片10、14和40在使用期间所生成的热量。由于布置在两个功率半导体芯片10和14之间的唯一导电材料层16，功率半导体芯片10和14之间的电阻和热阻减小。此外，层16减小了在制造过程的温度步骤期间在功率半导体芯片10和14中引起的机械应力。
图3示意性地示出了系统300的横截面视图。系统300包括器件200和电路板55。器件200安装在电路板55上，其安装表面51面向电路板55。还可以在电路板55上安装图3未示出的其他器件。电路板55可以时PCB（印刷电路板），并在器件200的外部接触垫50通过使用焊接沉积物57而附着至的其上表面上包括接触垫56。
图4示出了布置在两个节点N1和N2之间的半桥电路的基本电路400。半桥由串联连接的两个开关S1和S2构成。器件200的功率半导体芯片14和10分别可以被实现为开关S1和S2。可以对节点N1和N2施加恒定电位。例如，可以对节点N1施加高电位（如10、50、100、200、500或1000V或任何其他电位），并且可以对节点N2施加低电位（如0V）。因此，功率半导体芯片14是高侧开关S1，而功率半导体10时低侧开关S2。可以在从1 kHz至100 MHz的范围内的频率处切换开关S1和S2，但是开关频率也可以在该范围外。这意味着在半桥的操作期间对布置在开关S1和S2之间的节点N3施加变化的电位。节点N3的电位在低和高电位之间的范围内变化。
例如，半桥可以在用于转换DC电压的电子电路（所谓的DC-DC转换器）中实现。DC-DC转换器可以用于将由电池或可再充电电池提供的DC输入电压转换为与下游连接的电子电路的需求相匹配的DC输出电压。DC-DC转换器可以体现为：降压转换器，其中，输出电压小于输入电压；或者升压转换器，其中，输出电压大于输入电压。可以对DC-DC转换器应用若干MHz或更高的频率。此外，高至50 A或甚至更高的电流可以流经DC-DC转换器。
对于本领域技术人员来说显而易见，图2I所示的器件200及其如上所述的制造仅意在为示例实施例，并且许多变型是可能的。例如，其他半导体芯片或不同类型的无源元件可以包括在相同器件200中。半导体芯片和无源元件可以在功能、大小、制造技术等上有所不同。
图2A-2I所示的制造过程的变型在图5A-5D中示意性地示出。从如以下详述的制造过程获得的器件500在图5D中示出。
图5A示出了从图2A-2F所示的过程步骤获得的器件，其中，将介电箔45层压在载体20和半导体芯片10、14和40之上。然而，在图5A所示的实施例中，介电箔45的顶表面被暴露并且不涂覆金属层。
图5B示出了介电层45被结构化以便在介电层45中创建多个透孔60。透孔60暴露载体20和接触垫12、23、33、34和41的至少部分，使得可以与那些暴露的区域进行电连接。介电层45可以通过蚀刻或通过使用激光烧蚀而结构化。
图5C示出了化学或无电镀地沉积到透孔60的表面和介电层45的顶表面上的种子层61。可以针对通常具有小于1 μm的厚度的种子层61使用诸如合适聚合物或者钯或钛之类的材料。可以通过将另一导电材料层沉积到种子层61上来增大种子层61的厚度。例如，铜层可以被无电沉积到种子层61（图5C未示出）上。该铜层可以具有小于1 μm的厚度。随后如图5C所示结构化种子层61。
图5D示出了在结构化的种子层61上电沉积的铜或任何其他合适金属或金属合金的层62。层62可以具有多于5 μm的厚度。层62可以仅覆盖透孔60的壁，然而，透孔60还可以完全填充以金属材料。
由于种子层61的结构化，金属层62在介电层45的顶表面上沉积的部分形成外部接触垫，外部接触垫允许从器件500的外部电气接近半导体芯片10、14和40。金属层62的顶表面形成安装表面63。安装表面63可以用于将器件500安装在另一组件（如电路板）上。
图2A-2I所示的制造过程的另一变型在图6A-6D中示意性地示出。从如以下详述的制造过程获得的器件600在图6D中示出。
图6A示出了包括冲模垫71和外部接触元件72和73的引线框70。
引线框70可以具有任何几何形状，并且外部接触元件72和73可以以任何方式布置。引线框70不限于任何大小，例如，引线框70可以具有从100 μm至1 mm的范围内的厚度，或者甚至可以更厚。引线框70可以由金属（如铜）或金属合金（如铁镍）制造。引线框70可以利用导电材料（如铜、银、铁镍或镍磷）而电镀。可能压印或碾磨引线框70，以便生成如图6A所示的引线框70的外部形状。引线框70可以包括图6A未示出的其他冲模垫和/或外部接触元件。
图6B示出了如以上结合图2B-2D所述在冲模垫71上安装半导体芯片10、14和40。
图6C示出了如以上结合图2E-2F所述层压在冲模垫71、外部接触元件72和73以及半导体芯片10、14和40之上的具有金属层46的介电箔45。
图6D示出了贯穿（extend through）介电层45以便将接触垫12、23、33、34和41电耦合至引线框70的外部接触垫的通孔。例如，可以如以上结合图2G-2I所述制造通孔。引线框70的底表面是安装表面75。
图7示意性地示出了系统700的横截面视图。系统700包括器件600和电路板80。器件600安装在电路板80上，其安装表面75面向电路板80。还可以在电路板80上安装图7未示出的其他器件。电路板80可以是PCB（印刷电路板），并可以在器件600的冲模垫71以及外部接触垫72和73通过使用焊接沉积物82而附着至的其上表面上包括接触垫81。
图2A-2I所示的制造过程的另一变型在图8A-8D中示意性地示出。从如以下详述的制造过程获得的器件800在图8D中示出。
图8A示出了包括如以上结合图6A所述的冲模垫71以及外部接触元件72和73的引线框70。
图8B示出了以上结合图2B-2D所述在冲模垫71上安装半导体芯片10、14和40。
图8C示出了接合线90，其将半导体芯片10、14和40的接触垫12、23、33、34和41电耦合至引线框70的外部接触元件。在一个实施例中，使用金属夹来代替接合线90，将接触垫12、23、33、34和41电耦合至引线框70。
图8D示出了模塑料（mold compound）91，其对引线框70以及半导体芯片10、14和40进行包封。模塑料91可以是热塑性或热固性材料，并可以包含填充材料。可以采用各种技术以应用模塑料91，例如压缩成型、注射成型、粉末成型或液体成型。如图8D所示的器件800的安装表面是冲模垫71以及外部接触元件72和73的底表面75，所述底表面75从模塑料91暴露。
图9示意性地示出了系统900的横截面视图。系统900包括器件800和电路板80。器件800安装在电路板80上，其安装表面75面向电路板80。还可以在电路板80上安装图9未示出的其他器件。器件800的冲模垫71以及外部接触元件72和73附着至电路板80的接触垫81。
此外，尽管可能已经参照若干实施方式中的仅一个实施方式公开了本发明实施例的特定特征或方面，但是如对于任何给定的或特定的应用来说可能期望且有利的，可以将这种特征或方面与其他实施方式的一个或多个其他特征或方面进行组合。此外，在详细描述或权利要求中使用术语“包含”、“具有”、“具备”或其变型这方面来说，这样的术语意在以与术语“包括”类似的方式被包括进来。此外，应当理解，可以在分立的电路、部分集成的电路或完全集成的电路或者编程装置中实现本发明的实施例。此外，术语“示例性”仅表示作为示例，而不是最佳或最优。还应当认识到，为了简明和易于理解，利用相对于彼此而言特定的尺寸示出了这里所示的特征和/或元素，并且，实际尺寸可以与这里示出的尺寸大大不同。
尽管这里示出并描述了具体实施例，但是本领域技术人员应当认识到，在不脱离本发明的范围的前提下，可以利用多种备选和/或等同替换实施方式代替所示出和描述的具体实施例。本申请意在涵盖这里讨论的具体实施例的任何变化或变型。因此，本发明意在仅由权利要求及其等同替换方式来限定。

Claims (23)

1.一种半导体器件，包括：
第一半导体芯片，在第一面上包括第一接触垫；
第二半导体芯片，在第一面上包括第一接触垫，其中，所述第二半导体芯片被放置在所述第一半导体芯片之上，并且，所述第一半导体芯片的第一面面向所述第二半导体芯片的第一面；
唯一导电材料层，布置在所述第一半导体芯片与所述第二半导体芯片之间，其中，所述唯一导电材料层将所述第一半导体芯片的第一接触垫电耦合至所述第二半导体芯片的第一接触垫；以及
安装在所述第一半导体芯片上的第三半导体芯片，
其中，所述第一半导体芯片的第一接触垫的外形限定了所述第一半导体芯片的第一面的第一区段，并且所述第二半导体芯片置于所述第一区段内，并且所述第三半导体芯片在所述第一区段之外。
2.根据权利要求1所述的器件，其中，所述唯一导电材料层包括第一面和与所述第一面相对的第二面，其中，所述唯一导电材料层的第一面与所述第一半导体芯片的第一接触垫直接接触，并且所述唯一导电材料层的第二面与所述第二半导体芯片的第一接触垫直接接触。
3.根据权利要求1所述的器件，其中，所述第一半导体芯片在与所述第一面相对的第二面上包括第二接触垫。
4.根据权利要求3所述的器件，还包括导电载体，其中，所述第一半导体芯片置于载体上，其第二面面向载体。
5.根据权利要求4所述的器件，其中，所述载体的表面形成所述器件的安装表面。
6.根据权利要求1所述的器件，其中，所述第二半导体芯片在与所述第一面相对的第二面上包括第二接触垫。
7.根据权利要求1所述的器件，其中，所述第一半导体芯片和所述第二半导体芯片均为功率半导体芯片。
8.根据权利要求1所述的器件，还包括对所述第一半导体芯片和所述第二半导体芯片进行包封的层压材料。
9.根据权利要求8所述的器件，还包括置于所述层压材料上的金属层。
10.根据权利要求9所述的器件，还包括贯穿所述层压材料且将所述第一半导体芯片和所述第二半导体芯片电耦合至所述金属层的通孔。
11.根据权利要求10所述的器件，其中，所述金属层的表面形成所述器件的安装表面。
12.根据权利要求1所述的器件，其中，所述第三半导体芯片被配置为控制所述第一半导体芯片和所述第二半导体芯片。
13.根据权利要求1所述的器件，其中，所述导电材料包括从由以下各项构成的组选择的材料：软焊接材料、扩散焊接材料、导电粘合剂、以及由金属纳米粒子制成的材料。
14.一种半导体器件，包括：
第一半导体芯片，在第一面上包括第一接触垫并在与所述第一面相对的第二面上包括第二接触垫；
第二半导体芯片，在第一面上包括第一接触垫并在与所述第一面相对的第二面上包括第二接触垫，其中，所述第二半导体芯片置于所述第一半导体芯片之上；
安装在所述第一半导体芯片上的第三半导体芯片；以及
层压材料，对所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片进行包封；
其中，所述第一半导体芯片的第一接触垫的外形限定了所述第一半导体芯片的第一面的第一区段，并且所述第二半导体芯片置于所述第一区段内，并且所述第三半导体芯片在所述第一区段之外。
15.根据权利要求14所述的器件，所述第一半导体芯片的第一面面向所述第二半导体芯片的第一面，并且所述第一半导体芯片的第一接触垫电耦合至所述第二半导体芯片的第一接触垫。
16.根据权利要求14所述的器件，还包括置于所述层压材料上的金属层，其中，所述金属层的表面形成所述器件的安装表面。
17.根据权利要求16所述的器件，还包括贯穿所述层压材料且将所述第一半导体芯片和所述第二半导体芯片电耦合至所述金属层的通孔。
18.一种用于形成半导体器件的方法，所述方法包括：
将唯一导电材料层沉积在第一半导体芯片上，其中，所述第一半导体芯片的第一接触垫与所述导电材料直接接触；
将包括第一接触垫的第二半导体芯片置于所述第一半导体芯片之上，其中，所述第二半导体芯片的第一接触垫与所述导电材料直接接触；以及
在所述第一半导体芯片上安装第三半导体芯片；
其中，所述第一半导体芯片的第一接触垫的外形限定了所述第一半导体芯片的第一面的第一区段，并且所述第二半导体芯片置于所述第一区段内，并且所述第三半导体芯片在所述第一区段之外。
19.根据权利要求18所述的方法，其中，所述导电材料包括从由以下各项构成的组选择的材料：软焊接材料、扩散焊接材料、导电粘合剂、以及包括金属纳米粒子的膏剂。
20.根据权利要求18所述的方法，还包括：将介电层层压在所述第一半导体芯片和所述第二半导体芯片上。
21.根据权利要求20所述的方法，还包括：移除所述介电层的部分，直到所述第一半导体芯片和所述第二半导体芯片的部分被暴露为止。
22.根据权利要求21所述的方法，还包括：将金属材料沉积在所述第一半导体芯片和所述第二半导体芯片的暴露部分上。
23.根据权利要求18所述的方法，其中，所述第一半导体芯片和所述第二半导体芯片均为功率半导体芯片。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916968B2 (en) * 2012-03-27 2014-12-23 Infineon Technologies Ag Multichip power semiconductor device
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9041226B2 (en) * 2013-03-13 2015-05-26 Infineon Technologies Ag Chip arrangement and a method of manufacturing a chip arrangement
US8912663B1 (en) * 2013-06-28 2014-12-16 Delta Electronics, Inc. Embedded package structure and method for manufacturing thereof
US9941229B2 (en) * 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
CN103715184A (zh) * 2013-12-24 2014-04-09 华进半导体封装先导技术研发中心有限公司 基于柔性基板的三维多芯片存储系统封装结构及制作方法
JP6430883B2 (ja) * 2015-04-10 2018-11-28 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
JP6862087B2 (ja) * 2015-12-11 2021-04-21 株式会社アムコー・テクノロジー・ジャパン 配線基板、配線基板を有する半導体パッケージ、およびその製造方法
DE102016205793A1 (de) * 2016-04-07 2017-03-02 Robert Bosch Gmbh Mikromechanisches System
DE102017101185B4 (de) 2017-01-23 2020-07-16 Infineon Technologies Ag Ein Halbleitermodul umfassend Transistorchips, Diodenchips und Treiberchips, angeordnet in einer gemeinsamen Ebene, Verfahren zu dessen Herstellung und integriertes Leistungsmodul
US11476200B2 (en) * 2018-12-20 2022-10-18 Nanya Technology Corporation Semiconductor package structure having stacked die structure
EP4040472A1 (en) * 2021-02-03 2022-08-10 Nexperia B.V. A semiconductor device and a method of manufacturing a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1964036A (zh) * 2005-11-11 2007-05-16 南茂科技股份有限公司 堆叠型晶片封装结构

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617055C1 (de) 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
US5905639A (en) * 1997-09-29 1999-05-18 Raytheon Company Three-dimensional component stacking using high density multichip interconnect decals and three-bond daisy-chained wedge bonds
DE19954941C2 (de) 1999-11-16 2003-11-06 Fraunhofer Ges Forschung Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte
US6611434B1 (en) * 2000-10-30 2003-08-26 Siliconware Precision Industries Co., Ltd. Stacked multi-chip package structure with on-chip integration of passive component
TW488045B (en) * 2001-04-12 2002-05-21 Siliconware Precision Industries Co Ltd Semiconductor package with dislocated multi-chips
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2006216940A (ja) * 2005-01-07 2006-08-17 Toshiba Corp 半導体装置
JP2007019215A (ja) 2005-07-07 2007-01-25 Sanken Electric Co Ltd 半導体装置及びその製法
DE102005055761B4 (de) 2005-11-21 2008-02-07 Infineon Technologies Ag Leistungshalbleiterbauelement mit Halbleiterchipstapel in Brückenschaltung und Verfahren zur Herstellung desselben
US7705613B2 (en) * 2007-01-03 2010-04-27 Abhay Misra Sensitivity capacitive sensor
US7598123B2 (en) * 2007-03-02 2009-10-06 Semiconductor Components Industries, L.L.C. Semiconductor component and method of manufacture
DE102007017831B8 (de) 2007-04-16 2016-02-18 Infineon Technologies Ag Halbleitermodul und ein Verfahren zur Herstellung eines Halbleitermoduls
CN101465345B (zh) * 2007-12-19 2013-01-09 富士迈半导体精密工业（上海）有限公司 光源装置的制造方法
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
KR20090105570A (ko) 2008-04-03 2009-10-07 주식회사 하이닉스반도체 적층 반도체 패키지
US8686569B2 (en) 2010-12-14 2014-04-01 Infineon Technologies Ag Die arrangement and method of forming a die arrangement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1964036A (zh) * 2005-11-11 2007-05-16 南茂科技股份有限公司 堆叠型晶片封装结构

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