CN103681584A - 具有夹接触部的半导体器件 - Google Patents

具有夹接触部的半导体器件 Download PDF

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Publication number
CN103681584A
CN103681584A CN201310692504.XA CN201310692504A CN103681584A CN 103681584 A CN103681584 A CN 103681584A CN 201310692504 A CN201310692504 A CN 201310692504A CN 103681584 A CN103681584 A CN 103681584A
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Prior art keywords
semiconductor chip
contact
semiconductor device
contact clip
carrier
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CN201310692504.XA
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English (en)
Inventor
J·赫格劳尔
K·侯赛尼
R·奥特伦巴
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN103681584A publication Critical patent/CN103681584A/zh
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Abstract

本发明涉及具有夹接触部的半导体器件。一种半导体器件包括载体。此外，所述半导体器件包括半导体芯片，该半导体芯片包括第一主表面以及与所述第一主表面相对的第二主表面，其中在所述第一主表面上布置第一电极，以及所述半导体芯片以所述第二主表面面向所述载体的方式安装于所述载体上。此外，提供了一种嵌入有所述半导体芯片的密封体。所述半导体器件进一步包括接触夹，其中所述接触夹是具有接合到所述第一电极的接合部分且具有形成所述半导体器件的外部端子的端子部分的整体部件。

Description

具有夹接触部的半导体器件
技术领域
本发明涉及封装技术，且特别涉及使用夹接触部对半导体芯片进行封装的技术。
背景技术
半导体器件制造商一直努力提高其产品的性能，同时降低其制造成本。半导体器件制造中的成本密集区域对半导体芯片进行封装。如本领域技术人员所知，集成电路被制造于晶片上，然后，晶片被切割以产生半导体芯片。随后，半导体芯片可以安装于导电载体(诸如引线框)上。期望以低费用提供小部件尺寸的封装方法。
出于这些以及其他原因，存在对本发明的需要。
发明内容
根据本发明的第一方面，提供了一种半导体器件，包括：载体；半导体芯片，包括第一主表面以及与所述第一主表面相对的第二主表面，其中在所述第一主表面上布置第一电极，以及所述半导体芯片以所述第二主表面面向所述载体的方式安装于所述载体上；密封体，嵌入有所述半导体芯片；以及接触夹，其中所述接触夹是具有接合到所述第一电极的接合部分且具有形成所述半导体器件的外部端子的端子部分的整体部件。
根据本发明的第二方面，提供了一种接触夹，被配置为电接触封装内的半导体芯片的电极，所述接触夹包括：接合部分，被配置为接合到所述半导体芯片的所述电极；第一端子部分，包括所述接触夹的第一侧向边缘以及被配置为形成所述封装的第一外部接触部；以及第二端子部分，包括所述接触夹的第二侧向边缘以及被配置为形成所述封装的第二外部接触部。
根据本发明的第三方面，提供了一种接触夹，被配置为电接触封装内的半导体芯片的电极，所述接触夹包括：接合部分，被配置为接合到所述半导体芯片的所述电极；以及第一部分，包括所述接触夹的第一侧向边缘以及被配置为形成所述封装的外部端子。
根据本发明的第四方面，提供了一种制造半导体器件的方法，所述方法包括：提供包括第一主表面以及与所述第一主表面相对的第二主表面的半导体芯片，其中在所述第一主表面上布置第一电极；在载体上安装所述半导体芯片，其中所述半导体芯片以所述第二主表面面向所述载体的方式安装于所述载体上；将接触夹接合至所述半导体芯片，其中所述接触夹是具有接合到所述第一电极的接合部分以及端子部分的整体部件；以及形成嵌入有所述半导体芯片的密封体，其中所述接触夹的所述端子部分形成在所述密封体处暴露的外部端子。
根据本发明的第五方面，提供了一种半导体器件，包括：安装于载体的第一管芯焊盘上的第一功率半导体芯片；安装于载体的第二管芯焊盘上的第二功率半导体芯片；第一接触夹，将所述第一功率半导体芯片的顶表面上的电极与所述第二管芯焊盘互连；以及第二接触夹，其是具有接合至所述第二功率半导体芯片的顶表面上的电极的接合部分且具有形成所述半导体器件的外部端子的端子部分的整体部件。
附图说明
附图被包括以提供对实施例的进一步理解且被结合在本说明书中或构成本说明书的一部分。附图图示了实施例且与该描述一起用于解释实施例的原理。因为通过参考下面的详细描述，其他实施例和实施例的许多预期优点变得更好理解，所以它们将被容易地意识到。附图的元件不必相对于彼此按比例绘制。相似的附图标记表示对应的类似部分：
图1示意性地图示了具有为了示意目的而被假定为透明的密封体的半导体封装的实施例的顶视图；
图2示意性地图示了图1中所示的半导体封装沿线A-A的横截面视图；
图3A-3E示意性地图示了封装半导体芯片的方法的示例性工艺的横截面视图；
图4示意性地图示了根据多个实施例的具有多个边缘接触部分的接触夹的透视图；
图5图示了图1中所示的接触夹沿线A-A线的横截面视图；
图6A-6B图示了根据多个实施例的图1中所示的按照多个实施例的接触夹沿线B-B线的横截面视图；
图7示意性地图示了使用具有多个边缘接触部分的接触夹的半导体封装的实施例的顶视图；
图8A-8B图示了根据多个实施例的图7中所示的按照多个实施例的接触夹沿线B-B线的横截面视图；以及
图9图示了图7中所示的接触夹沿线A-A的横截面视图；
具体实施方式
在下面的详细描述中，对附图进行了参照，这些附图形成该详细描述的一部分，并且在这些附图中通过示意的方式示出了可实施本发明的具体示例。在这一点上，参照所描述的(一个或多个)图的定向来使用方向性术语，诸如“顶”、“底”、“前”、“后”、“首”、“尾”等等。由于可以以多个不同定向来定位实施例的部件，因此方向性术语被用于示意的目的并且决不进行限制。应当理解，在不脱离本发明的范围的情况下，可以利用其他实施例并且可以做出结构或逻辑的改变。因此，下面的详细描述不应在限制的意义上采用，并且本发明的范围由所附权利要求来限定。
应当理解，可以将本文描述的各种示例性实施例的特征与彼此组合，除非以其他方式具体指出。
如在本说明书中采用的那样，术语“耦合”和/或“电耦合”不意在意指元件必须直接耦合在一起；可以在“耦合”或“电耦合”的元件之间提供居间的元件。
本文描述了包含半导体芯片的器件。特别地，可以涉及具有垂直结构的一个或多个半导体芯片，也就是说，可以以电流可沿垂直于半导体芯片的主表面的方向流动的这种方式制造半导体芯片。具有垂直结构的半导体芯片在其两个主表面(即，其顶侧和底侧)上具有电极。
特别地，可以涉及功率半导体芯片。功率半导体芯片可以具有垂直结构。垂直功率半导体芯片可以例如被配置为功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、JFET(结型栅极场效应晶体管)、功率双极晶体管或功率二极管。作为示例，功率MOSFET的源电极和栅电极可以位于一个主表面上，而功率MOSFET的漏电极布置于另一主表面上。半导体芯片不必由特定半导体材料(例如Si、SiC、SiGe、GaAs)制造，且另外可以包含不作为半导体的无机和/或有机材料。半导体芯片可以是不同类型的且可以由不同技术制造。
半导体芯片可以具有允许与半导体芯片中所包括的集成电路进行电接触的电极。该电极可包括施加于半导体芯片的半导体材料的一个或多个金属层。该金属层可由任意期望几何形状以及任何期望材料组分制造。该金属层例如可具有覆盖区域的焊盘或层的形式。作为示例，任何能够形成焊料接合或扩散焊料接合的期望金属(例如Cu、Ni、NiSn、Au、Ag、Pt、Pd)以及这些金属中的一种或多种的合金可以用作该材料。该金属层不必是均质的或由仅一种材料制造，即，材料层中包含的材料的各种组分和浓度是可能的。
在载体上安装了一个或多个半导体芯片。在一个实施例中，该载体可以是金属板或薄片，诸如例如引线框的管芯焊盘。该金属板或薄片可由任何金属或金属合金(例如铜或铜合金)制成。在其他实施例中，该芯片载体可由塑料或陶瓷制成。例如，该芯片载体可以包括涂覆有金属层的塑料层。作为示例，这种芯片载体可以是单层PCB或多层PCB。该PCB可以具有至少一个绝缘层以及附着到该绝缘层的结构化金属箔层。该绝缘层典型地基于环氧树脂、聚四氟乙烯、芳纶纤维或碳纤维而制成且可包括加强装置，诸如纤维毡，例如玻璃或碳纤维。在其他实施例中，该芯片载体可以包括涂覆有金属层的陶瓷板。作为示例，这种芯片载体可以是DCB(直接铜接合)陶瓷衬底。
一个或多个功率半导体芯片被至少部分地包围或嵌入在至少一种电绝缘材料中。该电绝缘材料形成密封体。该密封体可包括模制材料或由模制材料制成。可以采用各种技术来形成模制材料的密封体，例如压缩模制、注射模制、粉末模制或液态模制。此外，该密封体可以具有一片层的形状，例如在(一个或多个)功率半导体芯片和(一个或多个)载体之上层压的一片薄片或箔。该密封体可以形成封装的外围的一部分，即，可以至少部分地限定半导体器件的形状。
电绝缘材料可以包括或由热固性材料或热塑性材料或者由热固性材料或热塑性材料制成。热固性材料可以例如基于环氧树脂而制成。热塑性材料可以例如包括聚醚酰亚胺(PEI)、聚醚砜(PES)聚苯硫醚(PPS)或聚酰胺酰亚胺(PAI)的组中的一种或多种材料。热塑性材料通过在模制或层压期间施加压力和热量而熔化，并在冷却和压力释放时(可逆地)硬化。
形成密封体的电绝缘材料可以包括聚合物材料或由聚合物材料制成。该电绝缘材料可以包括填充或未填充模制材料、填充或未填充热塑性材料、填充或未填充热固性材料、填充或未填充层压件、纤维加强层压件、纤维加强聚合物层压件以及具有填充颗粒的纤维加强聚合物层压件中的至少一个。
在一些实施例中，电绝缘材料可以是层压件，例如聚合物箔或薄片。可以在适合于将聚合物箔或薄片附着至下层结构的时间内施加热量和压力。在层压期间，电绝缘箔或薄片能够流动(即，处于塑性状态中)，使得功率半导体芯片和/或芯片载体上的其他拓扑结构之间的间隙被填充有电绝缘箔或薄片的聚合物材料。电绝缘箔或薄片可以包括任何适当的热塑性或热固性材料或者由任何适当的热塑性或热固性材料制成。在一个实施例中，该绝缘箔或薄片可以包括预浸料(预浸渍纤维的简称)或者由该预浸料制成，即，例如由纤维毡(例如玻璃或碳纤维)以及树脂(例如热固性或热塑性材料)的组合制成。预浸料材料是本领域中公知的且典型地用于制造PCB(印刷电路板)。
提供了将半导体芯片的电极电连接到半导体器件的外部端子的接触夹。该接触夹可以是具有接合到第一电极的接合部分且具有形成半导体器件的外部端子的端子部分的整体部件。作为示例，半导体器件的外部端子可以包括在无引线封装的密封体处暴露的外部接触区域。半导体器件的该外部端子还可以是引线封装的引线。
各种不同类型的电子器件可以被设计为使用如本文所述的接触夹，或可以由本文所述的技术制造。作为示例，依照本公开的电子器件可构成包含两个或更多功率MOSFET以及可选地包含一个或多个逻辑集成电路的电源。例如，本文公开的电子器件可以包括半桥电路，该半桥电路包括高侧晶体管、低侧晶体管以及可选地包括作为驱动器的逻辑集成电路芯片。半桥电路可例如被实现在电子电路中以转换DC电压，所谓的DC-DC转换器。DC-DC转换器可以用于将由电池或可再充电电池提供的DC输入电压转换为与下游连接的电子电路的需要相匹配的DC输出电压。作为示例，本文描述的DC-DC转换器可以是降压转换器或下转换器。
图1图示了根据一个实施例的示例性半导体器件100的顶视图。该半导体器件100可以是包括载体101、半导体芯片102、接触夹103以及密封体104的封装。图2示意性地图示了图1中所示的半导体器件100沿截面线A-A的横截面视图。
载体101可以包括平坦金属板(例如，引线框的管芯焊盘)或由该平坦金属板制成。在其他实施例中，载体101可包括其上表面(即，面向半导体芯片102的表面)上涂覆有金属层的陶瓷衬底或塑料板或者由该陶瓷衬底或金属板制成。
半导体芯片102可以安装于载体101上，其底表面面向载体101(例如，引线框的管芯焊盘)且其顶表面面向远离载体101的方向。该半导体芯片102可以具有顶表面上的第一电极(或接触焊盘)110以及底表面上的第二电极(或接触焊盘)111。该第一和第二电极110、111可以是功率半导体芯片102的负载电极。此外，该半导体芯片102可以具有其顶表面上的第三电极(或接触焊盘)112。该第三电极112可以例如是功率半导体芯片102的控制电极。
该半导体芯片102可以被配置为功率晶体管，例如，功率MOSFET、IGBT、JFET或功率双极晶体管或者功率二极管。在功率MOSFET或JFET的情况下，第一电极110为源电极，第二电极111为漏电极，以及第三电极112为栅电极。在IGBT的情况下，第一电极110为发射极电极，第二电极111为集电极电极，以及第三电极112为栅电极。在功率双极晶体管的情况下，第一电极110为发射极电极，第二电极111为集电极电极，以及第三电极112为基电极。在功率双极二极管的情况下，第一电极和第二电极110、111分别为阴极和阳极，并且没有第三电极。在操作期间，可以在第一和第二电极110、111之间施加高于5、50、100、500或1000V的电压。施加至第三电极112的开关频率的范围可以从1kHz到100MHz，但也可以在该范围外。
第二电极111可以通过接合层121电耦合以及机械耦合至载体101的上表面。该接合层121可以例如包括焊料、软焊料、扩散焊料、浆料、纳米浆料或导电粘合剂或者由其构成。
更具体地，该接合层121可以例如由扩散焊接材料(诸如例如AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi、Sn或Au)制成或者由包含分布在聚合物材料或树脂(诸如例如α-松油醇)中的金属颗粒的浆料制成。包含金属颗粒的浆料可以例如购买自下述公司：Coocson Electronic(产品名称：N1000)、AdvancedNano-Particles(ANP)、Harima Chemicals(产品名称：NPS-H和NHD-1)或NBETechnologies(产品名称：NBE Tech)。金属颗粒可以例如由银、金、铜、锡或镍制成。金属颗粒的尺寸(平均直径)可以例如小于100nm且特别地小于50nm或10nm。在本领域中，这些浆料也被称为纳米浆料。
第一电极110可以通过接合层120电耦合以及机械耦合至接触夹103的接合部分103_1。对于接合层120，可以使用与本文参考接合层121所公开相同的材料、物质以及接合技术。
接触夹103进一步包括端子部分103_3以及在接合部分103_1与端子部分103_3之间延伸的中间部分103_2。接合夹103是整体的，即，接合部分103_1、中间部分103_2和端子部分103_3可以由一个单个部件制成和/或不具有任何组件连接，诸如例如用于将接合部分103_1、中间部分103_2和端子部分103_3互连的焊接接合。
接合部分103_1可以包括被配置为提供接合接触区域103b的凹陷125。该接合接触区域103b可以相对于接合部分103_1的剩余延伸部稍微降低。该接合接触区域103b可以与接合层120接合。
接合部分103_1以及端子部分103_3可以沿基本上平行的方向伸展。中间部分103_2可以相对于接合部分103_1和/或端子部分103_3基本上倾斜或者甚至垂直地伸展。
半导体器件100的密封体104可以在侧面和顶面处嵌入载体101和半导体芯片102。接触夹103的端子部分103_3形成半导体器件100的外部端子且因此从密封体104向外突出。作为示例，如图1和2中所示，半导体器件可以具有无引线封装。在这种及其他情况下，接触夹103的端子部分103_3可以具有在密封体104处(例如在封装的底部处)暴露的外部接触区域103a。外部接触区域103a可以与由载体101的底表面101a限定的参考平面共面。载体101的底表面101a也可以在封装的底部处暴露。此外，密封体104的底表面部分104b可以与由载体101的底表面101a限定的参考平面共面。在该情况下，载体的底表面101a、密封体104的底表面部分104b以及端子部分103的外部接触区域103a均可以与彼此基本上齐平地布置。它们可以形成封装的底部。
载体101的顶表面101b可以限定封装的参考平面。该参考平面被称为内部(封装)参考平面。该内部参考平面可以例如与封装内的其他支撑结构的顶表面(诸如例如，引线柱130的顶表面130b和/或容纳于半导体器件100的封装中的另一载体(未示出)的顶表面)共面。该接触夹103可以在中间部分103_2处与内部参考平面相交。接触夹103与内部参考平面的交点可以位于密封体104内，即，位于由外围线104a限定的区域内。
引线柱130可以形成半导体器件100的另一外部端子。引线柱130的底表面130a可以在半导体器件100的封装的底表面处暴露，以便例如提供该封装的另一SMT外部接触区域。
通过诸如例如接合线140、另一接触夹(未示出)等的互连，第三电极112可与引线柱130耦合。如从图2可看到的那样，在不使任何外部接触区域在该封装处暴露于外部的情况下，互连140可以完全容纳于该封装中。互连140可以与引线柱130的顶表面130b连接。在引线柱130的顶表面130b与内部参考平面齐平或高于内部参考平面的情况下，该互连140可能不与半导体器件100的内部参考平面相交。
半导体器件100可以是SMT(表面安装技术)封装和/或THT(通孔技术)封装。在所有情况下，接触夹103在封装的密封体104处部分地暴露。接触夹103的端子部分103_3的接触区域103a可以被配置为与应用板(诸如例如，客户的器件的PCB(印刷电路板))接合。
附图标记104a指示密封体104的下边缘处的密封体104的外围轮廓线。在图1中，为了图示半导体器件100的封装的内部结构，假定密封体104为透明的。如从图1和2可看到的那样，端子部分103_3的侧向端面103c可以在半导体器件100的封装的外围处暴露。作为示例，端子部分103_3的端面103c可以在密封体104的外围线104a上突出较小距离(例如小于1mm)。在其他示例中，端面103c可以被密封体104覆盖，从而密封体104完全覆盖封装的侧向表面。
密封体104可以完全覆盖封装的顶表面。在其他示例中，密封体104可以具有布置于接触夹103上的开口(未示出)。该开口可以用于将接触夹103的接合部分103_1与设置于半导体器件100的封装之上的散热片(未示出)耦合。
半导体器件100的封装还可以是引线封装。在该情况下，接触夹103的端子部分103_3是从半导体器件100的封装突出的引线。在该情况下，可能未提供位于封装的底侧处的未暴露接触区域103a。更确切地，封装的底侧可以专门由载体101的底表面101a以及密封体104的底表面104b限定。形成封装的端子引线的端子部分103_3可以从封装突出大于1mm、3mm、5mm等的距离。
半导体器件100的封装可以例如具有从大约0.5-2mm(特别地，大约1mm)的范围内的厚度(高度)B。半导体芯片102可以具有从大约20、50、100μm到大约200、300、500μm的范围内的厚度(高度)。载体101可以具有从大约100-200μm或甚至多达例如500μm的范围内的厚度(高度)。互连140(例如接合线)可以具有从例如大约20-200μm(特别地，大约50μm)的范围内的直径。半导体芯片102可以具有大约1-10mm乘以1-10mm的芯片面积。作为示例，半导体芯片102的长度L可以是大约5mm或更小，以及半导体芯片102的宽度W可以是大约6mm或更小。
接触夹103的厚度(高度)T可以例如大于100μm、150μm、200μm、250μm、300μm且可以例如小于200μm、300μm或500μm。由接触夹103(即，由中间部分103_2)克服的高度差ΔH的范围可以从大约150μm到1000μm且可以例如大于200μm、250μm、300μm、350μm或400μm。应当注意，在封装的任何其他部件都没有贡献于克服该水平差ΔH的情况下，接触夹103的端子部分103_3处的接触区域103a与接触夹103的接合部分103_1的下表面之间的高度差ΔH专门被整体接触夹103桥接。
图3A-3E作为示例图示了对半导体芯片102进行封装以提供半导体器件(诸如例如，如图1和2中所示的半导体器件100)的方法的实施例的工艺阶段。应当注意，图3A-3E中所图示的生产阶段可以被理解为简化，这是由于可以使用未在这些图中图示的进一步工艺。例如，可以在半导体器件100的组装期间施加另外的介电层或构造化金属层。
根据图3A，提供了针对半导体芯片102的载体101以及例如另外的支撑结构(诸如例如，引线柱130)。该引线柱130以及载体101可形成相同引线框的一部分。
载体101可以例如是引线框的管芯焊盘、PCB(印刷电路板)、DCB(直接铜接合)(其是在其顶表面和底表面上具有铜层的陶瓷衬底)等。载体101由任意期望金属制成或者具有由任意期望金属制成的顶表面101b。特别地，可以使用能够形成扩散焊料接合的金属，例如Cu、Ni、NiSn、Au、Ag、Pt、Pd或者这些金属中的一种或多种的合金。
然后，可以将焊料材料或任何其他电或机械接合的物质(诸如例如，导电粘合剂)的接合层121施加到载体101的顶表面101b。作为示例，可以通过使用溅射工艺、电化学沉积工艺、印刷或点涂(dispensing)工艺来沉积接合层121。作为示例，可以在载体101的顶表面101b上印刷或点涂焊接材料浆料。该焊接材料浆料可以包含金属颗粒，例如助焊剂(flux)材料以及例如本领域中公知的用于分离金属颗粒的有机溶剂。
特别地，可以使用能够形成扩散焊料接合的任何焊接材料，例如包括Sn、SnAg、SnAu、In、InAg和InAu中的一种或多种的焊接材料。该焊接材料可以没有Pb。如果该焊接材料是扩散焊接材料浆料，则其可以包括例如由上面所引用的材料中的一种或多种制成的金属颗粒。
图3B示意性地图示了以第二主表面面向载体101的方式将半导体芯片102放置于载体101上的工艺。接合层121布置在半导体芯片102的第二主表面与载体101的顶表面101b之间。第二芯片电极111可以与接合层121相对且与接合层121邻接地布置。
然后，可以将半导体芯片102与载体101接合。作为示例，如果接合层121包括焊接材料，则可以加热图3B在所示的布置至一定温度以将半导体芯片102牢固地附着至载体101。例如可以在熔炉中完成加热。在其他实施例中，半导体芯片102可以仅放置于接合层121上，并且稍后在图3E中所示的工艺阶段处执行半导体芯片102与载体101的附着。
然后，参考图3C，接合层120可以沉积于半导体芯片102的第一主表面处的第一电极110上。接合层120的材料可以与如上所述的接合层121的材料相同。此外，可以使用与参考接合层121所描述相同的施加工艺在半导体芯片102上沉积接合层120。
参考图3D，可以将互连140接合到第三电极112以及引线柱130的顶表面130b，以将半导体芯片101与表示半导体器件100的外部端子的引线柱130的底表面130a电连接。互连140的接合还可以在制造工艺的另一阶段处完成，例如，在施加接合层120的工艺之前或在如图3E中所示施加接触夹103的工艺之后。
在图3E中，将接触夹103放置于半导体芯片102上。接触夹103可以由任意期望的金属(例如，能够形成扩散焊料接合的金属，例如Cu、Ni、NiSn、Au、Ag、Pt、Pd或者这些金属中的一种或多种的任何合金)制成。
接触夹103形成半导体器件100的外部端子。作为示例，接触夹103可以是被称为接触夹引线框的引线框的一部分。接触夹引线框可以是第二引线框，即，与包括载体(或管芯焊盘)101和引线柱130的第一引线框不同的引线框。在图3C或3D中所示的布置上放置接触夹103的一种可能性是使第二引线框(“接触夹引线框”)与第一引线框(“芯片载体引线框”)对齐。在该情况下，这两个引线框的框(未示出)可以被定位在相同水平处，例如，在由载体101的底表面101a限定的外围或底部参考平面所给出的水平处。
使用两个引线框以获得图3E中所示的结构的工艺是用于放置(一个或多个)接触夹103的并行工艺的示例。也可以以顺序的工艺(即，针对每个半导体器件100逐个夹)在图3C或3D中所示的布置上放置(一个或多个)接触夹103。
然后，可以将接触夹103与载体101接合。作为示例，如果接合层121包括焊接材料，则可以加热图3E中所示的布置至一定温度以将接触夹103牢固地附着至半导体芯片102。例如可以在熔炉中完成加热。在如上所述的一些示例中，将半导体芯片102接合至载体101的工艺以及将接触夹103接合至半导体芯片101的工艺可以被同时执行。
然后，可以施加电绝缘材料以形成密封体104，参见图2。例如，可以通过使用如前所述的模制技术来施加该电绝缘材料。
例如，可以通过使用如前所述的层压技术来施加该电绝缘材料。
图4图示了示例性接触夹203的透视图。接触夹203可以与依照上述公开的接触夹103相同。特别地，接触夹203可以包括与上述相同的材料或由与上述相同的材料制成。因此，为了避免重述，参考对接触夹103的上述公开。
接触夹203包括与上述的接触夹103的接合部分103_1相对应的可配备有凹陷225的接合部分203_1。接触夹203可以进一步包括与上述的接触夹103的中间部分103_2和端子部分103_3相对应的中间部分203_2和端子部分203_3。本文参考接触夹101描述的全部公开也可以适用于接触夹203。
端子部分203_3形成接触夹203的第一侧向边缘。该第一侧向边缘被配置为形成容纳接触夹203的封装(诸如，在图1和2中所示的封装或下面在图7-9中进一步示出的封装)的外部端子。
在图5中作为示例示出了接触夹203沿线A-A的横截面视图。接触夹203的横截面形状可以与如图2中所示的接触夹103的横截面形状相似或相同。特别地，可以通过接触夹203的中间部分203_2桥接相同的水平差ΔH。
接触夹203可以具有包括接触夹的第二侧向边缘的第二部分233_3。该第二侧向边缘可以被定向为基本上与第一侧向边缘垂直。
根据一个示例，第二部分233_3可以被设计为与第一部分203_3相似或相同。因此，可以通过将第二部分233_3与接合部分203_1互连的中间部分233_2桥接相同的水平差ΔH。在该情况下，第二部分233_3可以形成封装的外部端子，例如，如上所解释的SMT封装。作为示例，图6A图示了根据该接触夹设计的接触夹203沿线B-B的横截面视图。
可替换地，接触夹203可以被设计为示出根据图6B的沿线B-B的横截面形状。在该情况下，包括接触夹203的第二侧向边缘的第二部分233_3未形成接触夹203的外部端子。更确切地，接触夹203的第二部分233_3可以在与接合部分203_1相同的水平处延伸和/或可以具有包括接触区域233a的向下突出部。接触区域233a是用于形成与在其中(意图要)使用接触夹203的封装的内部结构的接触的接触区域。接触区域233a与接触夹203的接合部分203_1的底表面之间的高度差Δh显著小于ΔH。也就是说，在该示例中，接触夹203的第二侧向边缘233_3和第一侧向边缘203_3布置在相对于接触夹203的接合部分203_1的不同水平上。当在封装中实现时(参见例如图7)，第二侧向边缘233_3和第一侧向边缘203_3布置在相对于封装的底平面(其可由如图1-3E在所图示的载体101的底表面101a限定)的不同水平上。
换句话说，根据一个示例，接触夹203可以具有用作在其中使用接触夹203的封装的外部端子的两个或更多个侧向边缘。此外，根据一个示例，接触夹203可以具有用作在其中使用接触夹203的封装的外部端子的至少一个侧向边缘，并可以具有用作在其中使用接触夹203的封装内的内部接触部的至少一个(其他)侧向边缘。
图7示意性地图示了采用如上所述的具有两个边缘接触部分的接触夹203的半导体器件400的顶视图。该半导体器件400可以包括第一载体401_1、第二载体401_2以及第三载体401_3。所有载体401_1、401_2和401_3可以与彼此齐平。所有载体401_1、401_2和401_3可以是一个引线框的管芯焊盘。
半导体器件400可以是多芯片器件。作为示例，该半导体器件400可以是DC-DC转换器。该半导体器件可以包括第一半导体芯片402_1、第二半导体芯片402_2以及第三半导体芯片402_3。第一和第二半导体芯片402_1、402_2可以是功率半导体芯片，诸如例如功率MOSFET。第三半导体芯片402_3可以例如是被配置为控制功率半导体芯片402_1、402_2的逻辑集成电路(IC)。DC-DC转换器可以用于将由电池或可再充电电池提供的DC输入电压转换为与下游连接的电子电路的需要相匹配的DC输出电压。
在图7中，描绘了所谓的半桥电路。第一半导体芯片402_1可以形成半桥的低侧功率开关，且第二半导体芯片402_2可以形成半桥的高侧功率开关。逻辑集成电路403_1分别控制低侧和高侧功率半导体芯片402_1和402_2的栅电极。高侧功率半导体芯片402_2的源电极通过接触夹405连接至第一载体401_1。接触夹405可以是如在图6B中作为示例而例证的桥接水平差Δh的传统接触夹。也就是说，接触夹450可以向下达到由第一载体401_1的顶表面401b(与图1-3中图示的载体101的顶表面101b相对应)限定的封装的内部参考平面。这样，高侧功率半导体芯片402_2的源电极与低侧功率半导体芯片402_1的漏电极电连接。
在半导体器件400中采用如在图4、5以及图6A或图6B中作为示例而图示的接触夹203。接触夹203可以接触低侧功率半导体芯片402_1的源电极并提供封装的(一个或多个)外部端子。
在一个示例中，可以根据图4、5和6A的公开来设计接触夹203。在图7、8A和9中图示了这种实施方式。在该情况下，接触夹203的第一侧向边缘203_3和第二侧向边缘233_3二者被配置为形成封装的外部端子。
在另一示例中，可以如图4、5和6B中图示的那样设计接触夹203。在该情况下，接触夹203的第二侧向边缘233_3未形成封装的外部端子。更确切地，如在图8B中可看到的那样，接触夹203的侧向边缘233_3可以接触端子460。端子460形成与接触夹103的端子部分103_3类似的封装的外部端子。然而，端子460通过接合层461与接触夹203连接(即，不是接触夹203的组成部分)。此外，接触夹203的第二侧向边缘部分233_3可以仅向下达到高于由第一载体401_1的顶表面401b(与如上进一步描述的载体101的顶表面101b相对应)限定的封装的内部参考平面的水平。
将图8A与图8B相比较，显而易见，图8A的整体接触夹和外部端子设计比图8B中所示的两部分接触夹和外部端子设计在横向上更不消耗空间。作为示例，假定封装的给定尺寸，那么当使用图8A的整体接触夹和外部端子设计时，可以在横向上将芯片面积增加ΔL。或者，假定给定的芯片面积，那么当使用图8A的整体接触夹和外部端子设计时，可以以相同量减小封装的横向尺寸。因而，如本文所描述的整体接触夹和外部端子设计可以促进封装小型化和/或芯片面积的增加。此外，当使用如本文所公开的整体接触夹和外部端子设计时，可能不再需要如图8B中的接合层461所例证的接合层。
图9图示了沿图7中的线A-A的截面图。如前面关于图1-5描述的那样，接触夹203的第一侧向边缘203_3用作半导体器件400的封装的外部端子。如可例如在图8A、8B和9中看到的那样，半导体器件400的封装可以包括密封体404，密封体404具有与本文参考密封体104所描述相同的特征。
尽管本文图示并描述了特定实施例，但是本领域技术人员将意识到，在不脱离本发明的范围的情况下，可以用各种替换和/或等同实施方式替代所示出和描述的特定实施例。本申请意图覆盖本文所讨论的特定实施例的任何改编或变形。作为示例，在一些实施例中，第一电互连131可以例如是接合线。因而，意图是，本发明仅由权利要求及其等同物限定。

Claims (27)

1.一种半导体器件，包括：
载体；
半导体芯片，包括第一主表面以及与所述第一主表面相对的第二主表面，其中在所述第一主表面上布置第一电极，以及所述半导体芯片以所述第二主表面面向所述载体的方式安装于所述载体上；
密封体，嵌入有所述半导体芯片；以及
接触夹，其中所述接触夹是具有接合到所述第一电极的接合部分且具有形成所述半导体器件的外部端子的端子部分的整体部件。
2.根据权利要求1所述的半导体器件，其中所述端子部分包括在所述密封体处暴露的外部接触区域。
3.根据权利要求1所述的半导体器件，其中所述半导体芯片是功率半导体芯片。
4.根据权利要求1所述的半导体器件，其中在所述半导体芯片的所述第二主表面上布置第二电极。
5.根据权利要求1所述的半导体器件，其中所述接触夹与由所述载体的顶表面限定的内部参考平面相交。
6.根据权利要求2所述的半导体器件，其中所述接触夹的所述外部接触区域与由所述载体的底表面限定的底参考平面基本上共面。
7.根据权利要求1所述的半导体器件，其中所述密封体的底表面与由所述载体的底表面限定的底参考平面基本上共面。
8.根据权利要求1所述的半导体器件，其中接合到所述第一电极的接合部分和在所述密封体处暴露的端子部分基本上与彼此平行。
9.根据权利要求1所述的半导体器件，其中所述接触夹进一步包括将所述接合部分与所述端子部分互连的中间部分，所述中间部分相对于所述接合部分和/或所述端子部分基本上倾斜或垂直地延伸。
10.根据权利要求2所述的半导体器件，其中所述端子部分的所述外部接触区域是无引线封装接触区域。
11.根据权利要求1所述的半导体器件，其中所述端子部分是引线封装的引线。
12.根据权利要求1所述的半导体器件，其中所述载体是引线框的管芯焊盘。
13.一种接触夹，被配置为电接触封装内的半导体芯片的电极，所述接触夹包括：
接合部分，被配置为接合到所述半导体芯片的所述电极；
第一端子部分，包括所述接触夹的第一侧向边缘以及被配置为形成所述封装的第一外部接触部；以及
第二端子部分，包括所述接触夹的第二侧向边缘以及被配置为形成所述封装的第二外部接触部。
14.根据权利要求13所述的接触夹，其中所述第一侧向边缘以及所述第二侧向边缘基本上与彼此垂直地延伸。
15.根据权利要求13所述的接触夹，其中所述第一侧向边缘以及所述第二侧向边缘布置在相对于所述封装的底平面的相同水平上。
16.一种接触夹，被配置为电接触封装内的半导体芯片的电极，所述接触夹包括：
接合部分，被配置为接合到所述半导体芯片的所述电极；以及
第一部分，包括所述接触夹的第一侧向边缘以及被配置为形成所述封装的外部端子。
17.根据权利要求16所述的接触夹，进一步包括：
第二部分，其包括所述接触夹的第二侧向边缘，所述第二部分被配置为形成所述封装的另一外部端子。
18.根据权利要求17所述的接触夹，其中所述第一侧向边缘以及所述第二侧向边缘基本上与彼此垂直地延伸。
19.根据权利要求16所述的接触夹，进一步包括：
第二部分，其包括所述接触夹的第二侧向边缘，所述第二部分被配置为形成所述封装的内部互连。
20.根据权利要求19所述的接触夹，其中所述第一侧向边缘以及所述第二侧向边缘基本上与彼此垂直地延伸。
21.根据权利要求19所述的接触夹，其中所述第一侧向边缘以及所述第二侧向边缘布置在相对于所述封装的底平面的不同水平上。
22.一种制造半导体器件的方法，所述方法包括：
提供包括第一主表面以及与所述第一主表面相对的第二主表面的半导体芯片，其中在所述第一主表面上布置第一电极；
在载体上安装所述半导体芯片，其中所述半导体芯片以所述第二主表面面向所述载体的方式安装于所述载体上；
将接触夹接合至所述半导体芯片，其中所述接触夹是具有接合到所述第一电极的接合部分以及端子部分的整体部件；以及
形成嵌入有所述半导体芯片的密封体，其中所述接触夹的所述端子部分形成在所述密封体处暴露的外部端子。
23.根据权利要求22所述的方法，进一步包括：
将接合线接合至布置于所述半导体芯片的所述第一主表面上的第二电极。
24.根据权利要求22所述的方法，其中所述载体是第一引线框的管芯焊盘，以及所述接触夹是第二引线框的一部分，所述方法包括：
当将所述接触夹接合到所述半导体芯片时，将所述第一引线框和所述第二引线框对齐。
25.一种半导体器件，包括：
安装于载体的第一管芯焊盘上的第一功率半导体芯片；
安装于载体的第二管芯焊盘上的第二功率半导体芯片；
第一接触夹，将所述第一功率半导体芯片的顶表面上的电极与所述第二管芯焊盘互连；以及
第二接触夹，其是具有接合至所述第二功率半导体芯片的顶表面上的电极的接合部分且具有形成所述半导体器件的外部端子的端子部分的整体部件。
26.根据权利要求25所述的半导体器件，进一步包括：
嵌入有所述第一功率半导体芯片和所述第二功率半导体芯片的密封体；以及其中所述端子部分具有在所述密封体处暴露的外部接触区域。
27.根据权利要求25所述的半导体器件，其中所述半导体器件是DC-DC转换器。
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