JP4916745B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4916745B2 JP4916745B2 JP2006087961A JP2006087961A JP4916745B2 JP 4916745 B2 JP4916745 B2 JP 4916745B2 JP 2006087961 A JP2006087961 A JP 2006087961A JP 2006087961 A JP2006087961 A JP 2006087961A JP 4916745 B2 JP4916745 B2 JP 4916745B2
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Description
前記第2金属板は、前記第2半導体チップのソース電極に接続された第1部分と、前記第2半導体チップの1つの角を挟んで交差する2つの辺のうちの一方の辺を跨いで延在する第2部分と、前記第2部分から分かれた状態で、前記2つの辺のうちの他方の辺を跨いで延在する第3部分とを一体的に有するものである。
図1は本実施の形態1の半導体装置を有する非絶縁型DC−DCコンバータ1の一例の回路図、図2は図1の非絶縁型DC−DCコンバータ1の基本動作波形図をそれぞれ示している。
本実施の形態2では、上記金属板8Bの構成が前記実施の形態1と異なる。それ以外の構成は、前記実施の形態1と同じである。
本実施の形態3では、上記金属板8Bに形成される応力緩和用の穴の形状が前記実施の形態2と異なる。それ以外の構成は、前記実施の形態1,2と同じである。
本実施の形態4では、上記金属板8Bに形態される応力緩和用の穴の外周に窪みを形成する例を説明する。それ以外の構成は、前記実施の形態1,2,3と同じである。
本実施の形態5では、金属板8Bに形態される応力緩和用の穴の配置が前記実施の形態3と異なる。それ以外の構成は、前記実施の形態1〜3と同じである。
本実施の形態6では、上記金属板の裏面に応力緩和用の凹みを形成する例を説明する。
本実施の形態7では、半導体チップの外周の厚さが半導体チップの中央よりも薄く形成されている例を説明する。
本実施の形態8では、ハイサイド用のパワーMOSQH1が形成された半導体チップ4PHに接合された金属板8Aの第2部分8A2が複数に分割されている例を説明する。
本実施の形態9では、上記金属板8A,8Bの裏面に突起を形成する例を説明する。
本実施の形態10では、ロウサイド用のパワーMOSQL1にショットキーバリアダイオード(Schottky Barrier Diode)SBDを並列に接続した例を説明する。
本実施の形態11では、ロウサイド用のパワーMOSが形成された半導体チップ4PLのゲート配線19Gの配置の変形例について説明する。
本実施の形態12では、本実施の形態1〜11で説明した半導体装置2の製造方法の一例を図77のフロー図に沿って説明する。なお、ここでは、前記実施の形態3で説明した半導体装置2の製造方法を一例として説明する。
本実施の形態13においては、上記接着層11a〜11cの材料として、上記半田ペーストに代えて銀ペーストを用いる場合の半導体装置の製造方法について説明する。
本実施の形態14では、半導体装置2の他の製造方法の一例を図77(または図82)の製造フロー図に沿って図85〜図94により説明する。
図95は図64の半導体装置2の他の例のパッケージPAの内部を透かして見せた全体平面図、図96は図95の金属板8A,8Bを外した状態のパッケージPAの内部を透かして見せた全体平面図、図97は図95の半導体装置2の半導体チップ4PLの最上層を示した全体平面図、図98は図97の半導体チップ4PLの最上の配線層を示した全体平面図である。
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
2 半導体装置
3 制御回路
4D 半導体チップ(第3半導体チップ)
4PH 半導体チップ(第1半導体チップ)
4PL 半導体チップ(第2半導体チップ)
4S 半導体基板
4S1 半導体層
4S2 エピタキシャル層
7 リードフレーム
7D1,7D2,7D3 ダイパッド(チップ搭載部)
7L,7L1,7L2,7L3,7L4,7L5 リード(外部端子)
7LB リード配線(配線部)
8 金属板フレーム
8A 金属板(第1金属板)
8A1 第1部分
8A2 第2部分
8A3 吊り部
8B 金属板(第2金属板)
8B1 第1部分
8B2 第2部分
8B3 第3部分
8B4 第4部分
8C 金属板
8D 金属板
8E 金属板
8E1 第1部分
8E2 第2部分
8E3 第3部分
8E4 第4部分
9 メッキ層
11a〜11c 接着層
12G ボンディングパッド
12S1,12S2 ボンディングパッド(第1ソース電極領域)
12S3 ボンディングパッド(第2ソース電極領域)
13A,13B,13C,13D,13E,13F ボンディングパッド
15G ボンディングパッド
15S1 ボンディングパッド(第3ソース電極領域)
15S2 ボンディングパッド(第4ソース電極領域)
18 保護膜
19G ゲート配線
19G1 ゲートパッド部
19G2,19G3 ゲートフィンガ部
19S ソース配線
20a〜20d 開口部
21,21a,21b 金属層
22G1,22G2 ゲート配線
22G3 ゲート電極
25 フィールド絶縁膜
26 半導体領域
27 半導体領域
30 溝
31 ゲート絶縁膜
32 絶縁膜
33a,33b,33c コンタクトホール
35 半導体領域
38 配線基板
39a〜39e 配線
40L リード
45 窪み
46 スリット
47A,47B,47C 穴
48A 凹み
48B 凹み
50 窪み
51 ダイシングテープ
52A ダイシングソー
52B ダイシングソー
53 突起
55A 金属板(第1金属板)
55B 金属板(第2金属板)
56A 金属板(第3金属板)
56B 金属板(第4金属板)
56C 金属板(第5金属板)
LD 負荷
QH1,QL1 パワーMOS・FET(パワートランジスタ)
Cin 入力コンデンサ
Cout 出力コンデンサ
L コイル
DR1,DR2 ドライバ回路
D ドレイン
S ソース
IM 位置決め用のテーパ
VIN 入力電源
ET1 端子(第1電源端子)
ET2 端子(第2電源端子)
N 出力ノード
Dp1,Dp2 寄生ダイオード
Ton パルス幅
T パルス周期
PA パッケージ(封止体)
PB,PC,PD,PE,PF,PG パッケージ
PWL1 p型ウエル
BE 裏面電極
WA ボンディングワイヤ
WB ボンディングワイヤ
CA,CB,CC チップ部品
SBD ショットキーバリアダイオード
LU 単位領域
MU 単位領域
Claims (6)
- 以下の工程を有することを特徴とする半導体装置の製造方法;
(a)第1、第2、第3チップ搭載部と、前記第1、第2、第3チップ搭載部の周囲に配置され、相対的に高い電源電位を供給する第1電源端子および相対的に低い電源電位を供給する第2電源端子を有する複数の外部端子とを単位領域に一体的に持つリードフレームを用意する工程、
(b)前記リードフレームの前記第1、第2、第3チップ搭載部に、それぞれ半田ペーストを介して第1、第2、第3半導体チップを搭載する工程、
(c)前記第1、第2半導体チップの電極に、それぞれ半田ペーストを介して第1、第2金属板を搭載する工程、
(d)前記(b)、(c)工程後、前記半田ペーストに熱を加えて溶融し、前記第1、第2、第3半導体チップをそれぞれ前記第1、第2、第3チップ搭載部に接合するとともに、前記第1、第2金属板をそれぞれ前記第1、第2半導体チップの電極に接合する工程、
(e)前記(d)工程後、前記第3半導体チップの電極にボンディングワイヤを接続する工程、
(f)前記(e)工程後、前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部、前記ボンディングワイヤおよび前記第1、第2、第3半導体チップを封止体によって封止する工程。 - 請求項1記載の半導体装置の製造方法において、
前記第1金属板は、前記第1半導体チップに形成された第1電界効果トランジスタのソースと、前記第2半導体チップに形成された第2電界効果トランジスタのドレインとを電気的に接続し、
前記第2金属板は、前記第2半導体チップに形成された第2電界効果トランジスタのソースと、前記第2電源端子とを電気的に接続することを特徴とする半導体装置の製造方法。 - 以下の工程を有することを特徴とする半導体装置の製造方法;
(a)第1、第2、第3チップ搭載部と、前記第1、第2、第3チップ搭載部の周囲に配置され、相対的に高い電源電位を供給する第1電源端子および相対的に低い電源電位を供給する第2電源端子を有する複数の外部端子とを単位領域に一体的に持つリードフレームを用意する工程、
(b)前記リードフレームの前記第1、第2、第3チップ搭載部に、それぞれ第1、第2、第3半導体チップを搭載する工程、
(c)前記第1、第2半導体チップの電極に、それぞれ第1、第2金属板を一括して搭載する工程、
(d)前記(a),(b),(c)工程後、前記第3半導体チップの電極にボンディングワイヤを接続する工程、
(e)前記(d)工程後、前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部、前記ボンディングワイヤおよび前記第1、第2、第3半導体チップを封止体によって封止する工程。 - 以下の工程を有することを特徴とする半導体装置の製造方法;
(a)第1、第2、第3チップ搭載部と、前記第1、第2、第3チップ搭載部の周囲に配置され、相対的に高い電源電位を供給する第1電源端子および相対的に低い電源電位を供給する第2電源端子を有する複数の外部端子とを単位領域に一体的に持つリードフレームを用意する工程、
(b)前記リードフレームの前記第1、第2、第3チップ搭載部に、それぞれ第1、第2、第3半導体チップを搭載する工程、
(c)前記第1、第2半導体チップの電極に、それぞれ第1、第2金属板を搭載する工程、
(d)前記(a),(b),(c)工程後、前記第1金属板に第3金属板を搭載し、前記第2金属板に第4、第5金属板を搭載する工程、
(e)前記(d)工程後、前記第3半導体チップの電極にボンディングワイヤを接続する工程、
(f)前記(e)工程後、前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部、前記ボンディングワイヤおよび前記第1、第2、第3半導体チップを封止体によって封止する工程を有し、
前記第3、第4、第5金属板は、同一構成であることを特徴とする半導体装置の製造方法。 - 以下の工程を有することを特徴とする半導体装置の製造方法;
(a)第1、第2、第3チップ搭載部と、前記第1、第2、第3チップ搭載部の周囲に配置され、相対的に高い電源電位を供給する第1電源端子および相対的に低い電源電位を供給する第2電源端子を有する複数の外部端子とを単位領域に一体的に持つリードフレームを用意する工程、
(b)前記リードフレームの前記第1、第2、第3チップ搭載部に、それぞれ銀ペーストを介して第1、第2、第3半導体チップを搭載する工程、
(c)前記第1、第2半導体チップの電極に、それぞれ銀ペーストを介して第1、第2金属板を搭載する工程、
(d)前記(b)、(c)工程後、前記銀ペーストに熱を加えて前記銀ペースト中の樹脂を硬化させ、前記第1、第2、第3半導体チップをそれぞれ前記第1、第2、第3チップ搭載部に接合するとともに、前記第1、第2金属板をそれぞれ前記第1、第2半導体チップの電極に接合する工程、
(e)前記(d)工程後、前記第3半導体チップの電極にボンディングワイヤを接続する工程、
(f)前記(e)工程後、前記第1、第2、第3チップ搭載部の一部、前記複数の外部端子の一部、前記ボンディングワイヤおよび前記第1、第2、第3半導体チップを封止体によって封止する工程。 - 請求項5記載の半導体装置の製造方法において、
前記第1金属板は、前記第1半導体チップに形成された第1電界効果トランジスタのソースと、前記第2半導体チップに形成された第2電界効果トランジスタのドレインとを電気的に接続し、
前記第2金属板は、前記第2半導体チップに形成された第2電界効果トランジスタのソースと、前記第2電源端子とを電気的に接続することを特徴とする半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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EP4152384A1 (en) * | 2021-09-17 | 2023-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
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US7932588B2 (en) | 2011-04-26 |
US20120273892A1 (en) | 2012-11-01 |
US8237232B2 (en) | 2012-08-07 |
US20100127683A1 (en) | 2010-05-27 |
US8592914B2 (en) | 2013-11-26 |
US20110169102A1 (en) | 2011-07-14 |
US7679173B2 (en) | 2010-03-16 |
US20070228534A1 (en) | 2007-10-04 |
JP2007266218A (ja) | 2007-10-11 |
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