TWI608583B - 共源極式封裝結構 - Google Patents

共源極式封裝結構 Download PDF

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Publication number
TWI608583B
TWI608583B TW105141464A TW105141464A TWI608583B TW I608583 B TWI608583 B TW I608583B TW 105141464 A TW105141464 A TW 105141464A TW 105141464 A TW105141464 A TW 105141464A TW I608583 B TWI608583 B TW I608583B
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TW
Taiwan
Prior art keywords
gate
electrode contact
pin
source
contact pad
Prior art date
Application number
TW105141464A
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English (en)
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TW201822334A (zh
Inventor
Chien Chung Chen
Sen Mao
Hsin Liang Lin
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Taiwan Semiconductor Co Ltd
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Application filed by Taiwan Semiconductor Co Ltd filed Critical Taiwan Semiconductor Co Ltd
Priority to TW105141464A priority Critical patent/TWI608583B/zh
Priority to DE102017103476.5A priority patent/DE102017103476B4/de
Priority to US15/439,268 priority patent/US9997500B1/en
Priority to US15/803,248 priority patent/US10056355B2/en
Application granted granted Critical
Publication of TWI608583B publication Critical patent/TWI608583B/zh
Publication of TW201822334A publication Critical patent/TW201822334A/zh

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Description

共源極式封裝結構
本發明係有關於一種共源極式封裝結構，尤其是指一種兩個晶粒之源極電極接觸墊彼此電性連接之共源極式封裝結構。
近年來隨著科技的發展，電子產品大量的發展使得人們的生活愈趨方便，其中，電子產品普遍需使用到如金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET)之功率電晶體，由於功率電晶體具有高集成密度與低靜態漏電流等優點，因而普遍應用於電子產品之電路設計上。
在輕薄短小的趨勢下，如何對功率電晶體封裝的半導體封裝結構的設計成為現有業者所面對之課題。其中，現有之封裝結構中，當電路設計為兩個以上MOSFET的連接時，現有封裝結構的設計中，兩個MOSFET所分別集成的封裝結構需要再使用導線使其彼此連接，因而導通時會有路徑長而造成較多線路損耗及無法縮小基板 面積之問題。
另外，現有MOSFET所集成的封裝結構中，其晶粒上的閘極電極接觸墊僅設有一個，因此實務上封裝結構需調整晶粒的位置時，會影響到佈線而使得研發人員難以設計，因此，現有技術仍具備改善之空間。
有鑒於現有封裝結構需另外使用導線彼此連接，因而普遍具有較多線路損耗及無法縮小基板面積之問題。緣此，本發明主要係提供一種共源極式封裝結構，其係兩個晶粒之源極電極接觸墊彼此電性連接並封裝於同一封裝體，以達到縮短路徑與縮小封裝結構，進而縮小基板面積之目的。
基於上述目的，本發明所採用之主要技術手段係提供一種共源極式封裝結構，包含一集成式晶粒組件以及一封裝體，集成式晶粒組件包含一集成式組件本體、一第一金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET)晶粒(die)、一第二MOSFET晶粒、至少一共用源極連結元件、至少一第一閘極連結元件以及至少一第二閘極連結元件。集成式組件本體係設有一共用源極接腳區域、一第一閘極接腳區域、一第二閘極接腳區域、一第一設置區域與一第二設置區域，第一設置區域與第二設置區域係彼此相間隔。第一MOSFET晶粒係設置於第一設置區 域，具有一第一上表層，並包含至少一第一源極電極接觸墊(source electrode pad)以及至少一第一閘極電極接觸墊(gate electrode pad)。該至少一第一源極電極接觸墊係外露於第一上表層，該至少一第一閘極電極接觸墊係與該至少一第一源極電極接觸墊相間隔地外露於第一上表層。
第二MOSFET晶粒設置於第二設置區域，具有一第二上表層，並包含至少一第二源極電極接觸墊以及至少一第二閘極電極接觸墊。該至少一第二源極電極接觸墊係外露於第二上表層，該至少一第二閘極電極接觸墊係與該至少一第二源極電極接觸墊相間隔地外露於第二上表層。該至少一共用源極連結元件係連結該至少一第一源極電極接觸墊、該至少一第二源極電極接觸墊與共用源極接腳區域。該至少一第一閘極連結元件係連結第一閘極電極接觸墊與第一閘極接腳區域。該至少一第二閘極連結元件係連結第二閘極電極接觸墊與第二閘極接腳區域。封裝體係至少局部包覆集成式晶粒組件。
在上述必要技術手段的基礎下，上述共源極式封裝結構還包含以下所述的較佳附屬技術手段。共用源極接腳區域包含至少一第一源極接腳與至少一第二源極接腳，第一閘極接腳區域包含至少一第一閘極接腳，第二閘極接腳區域包含至少一第二閘極接腳，該至少一第一閘極接腳、該至少一第一源極接腳、該至少一第二源極接腳與該至少一第二閘極接腳係沿一排列方向依序排列。
在上述必要技術手段的基礎下，上述共源 極式封裝結構還包含以下所述的較佳附屬技術手段。該至少一第一源極電極接觸墊包含至少一第一凹緣，該至少一第一閘極電極接觸墊係鄰近於該至少一第一凹緣而設置，該至少一第二源極電極接觸墊包含至少一第二凹緣，該至少一第二閘極電極接觸墊係鄰近於該至少一第二凹緣而設置。另外，該至少一共用源極連結元件係一體成型之金屬板，該至少一第一閘極連結元件與該至少一第二閘極連結元件係分別為至少一導線。
在上述必要技術手段的基礎下，上述共源極式封裝結構還包含以下所述的另一較佳附屬技術手段。該至少一共用源極連結元件係為至少一導線。
在採用本發明所提供之共源極式封裝結構之主要技術手段後，由於是將兩個MOEFET的晶粒集成於同一個封裝本體上，並採共源極之設計，因此可有效降低線路損耗而達到更穩定及有效縮小基板面積之功效。
另外，在採用本發明所提供之共源極式封裝結構之附屬技術手段後，由於閘極電極接觸墊的數量為兩個以上時，閘極電極接觸墊設計的位置為MOSFET晶粒相對應的角落，因此在實務上電路的佈線可更為彈性化而增加方便性。
本發明所採用的具體實施例，將藉由以下之實施例及圖式作進一步之說明。
1‧‧‧共源極式封裝結構
11‧‧‧集成式晶粒組件
111‧‧‧集成式組件本體
1111‧‧‧共用源極接腳區域
11111、1111b‧‧‧第一源極接腳
11112、1112b‧‧‧第二源極接腳
1112‧‧‧第一閘極接腳區域
11121‧‧‧第一閘極接腳
1113‧‧‧第二閘極接腳區域
11131‧‧‧第二閘極接腳
1114‧‧‧第一設置區域
1115‧‧‧第二設置區域
1116‧‧‧隔絕區域
112‧‧‧第一MOSFET晶粒
1121‧‧‧第一上表層
1122‧‧‧第一下表層
1123、1123a、1123b‧‧‧第一源極電極接觸墊
11231、11231a‧‧‧第一凹緣
1124、1124a‧‧‧第一閘極電極接觸墊
1125‧‧‧第一汲極電極接觸墊
1126‧‧‧第一半導體結構
113‧‧‧第二MOSFET晶粒
1131‧‧‧第二上表層
1132‧‧‧第二下表層
1133、1133a、1133b‧‧‧第二源極電極接觸墊
11331、11331a‧‧‧第二凹緣
1134、1134a‧‧‧第二閘極電極接觸墊
1135‧‧‧第二汲極電極接觸墊
1136‧‧‧第二半導體結構
114、114b‧‧‧共用源極連結元件
115‧‧‧第一閘極連結元件
116‧‧‧第二閘極連結元件
12‧‧‧封裝體
L‧‧‧排列方向
W‧‧‧間距
第一圖係顯示本發明第一較佳實施例之共源極式封裝結構之上視圖。
第二圖係顯示本發明第一較佳實施例之共源極式封裝結構之剖面示意圖。
第三圖係顯示本發明第二較佳實施例之共源極式封裝結構之上視圖。
第四圖係顯示本發明第三較佳實施例之共源極式封裝結構之上視圖。
第五圖係顯示本發明第三較佳實施例之共源極式封裝結構之剖面示意圖。
由於本發明所提供之共源極式封裝結構中，其組合實施方式不勝枚舉，故在此不再一一贅述，僅列舉三個較佳實施例加以具體說明。
請一併參閱第一圖與第二圖，第一圖係顯示本發明第一較佳實施例之共源極式封裝結構之上視圖，第二圖係顯示本發明第一較佳實施例之共源極式封裝結構之剖面示意圖。
如圖所示，本發明較佳實施例之共源極式封裝結構1包含一集成式晶粒組件11以及一封裝體12。集成式晶粒組件11包含一集成式組件本體111、一第一金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET)晶粒(die)112、一第二MOSFET晶粒113、至少一共用源極連結元件114、至少一第一閘極連結元件115以及至少一第二閘極連結元件116。
集成式組件本體111例如為導線架(lead frame)，並設有一共用源極接腳區域1111、一第一閘極接腳區域1112、一第二閘極接腳區域1113、一第一設置區域1114、一第二設置區域1115與一隔絕區域1116。共用源極接腳區域1111包含至少一第一源極接腳11111(圖中僅繪示三個，並標示一個)與至少一第二源極接腳11112(圖中僅繪示三個，並標示一個)。
第一閘極接腳區域1112包含至少一第一閘極接腳11121(圖中僅繪示一個)，第二閘極接腳區域1113包含至少一第二閘極接腳11131(圖中僅繪示一個)。該至少一第一閘極接腳11121、該至少一第一源極接腳11111、該至少一第二源極接腳11112與該至少一第二閘極接腳11131係沿一排列方向L依序排列，使得源極接腳及閘極接腳呈鏡射排列，因此，實務上研發人員設計連接源極電極接觸墊(將於下說明)的引線時較方便。
第一設置區域1114與第二設置區域1115係透過隔絕區域1116而彼此相對，使得第一設置區域1114與第二設置區域1115彼此相間，其中，隔絕區域1116例如填滿有環氧樹脂(Epoxy)，且隔絕區域1116中設有較大的間距W，此間距可用於提升耐壓(一般可提升至600V)，但 其他實施例中不限於此。
第一MOSFET晶粒112係設置於第一設置區域1114，具有一第一上表層1121與一第一下表層1122，並包含至少一第一源極電極接觸墊(source electrode pad)1123(圖中繪示兩個，僅標示一個)、至少一第一閘極電極接觸墊(gate electrode pad)1124、至少一第一汲極電極接觸墊(source electrode pad)1125與一第一半導體結構1126。
該至少一第一源極電極接觸墊1123係外露於第一上表層1121，並且包含至少一第一凹緣11231(圖中僅繪示一個)。該至少一第一閘極電極接觸墊1124係與該至少一第一源極電極接觸墊1123相間隔地外露於第一上表層1121，並鄰近於該至少一第一凹緣11231而設置。另外，該至少一第一汲極電極接觸墊1125係外露於第一下表層1122。第一半導體結構1126係位於第一源極電極接觸墊1123與第一汲極電極接觸墊1125之間，其係由現有之電路架構所組成，不再贅述。
第二MOSFET晶粒113設置於第二設置區域1115，具有一第二上表層1131與一第二下表層1132，並包含至少一第二源極電極接觸墊1133(圖中繪示兩個，僅標示一個)、至少一第二閘極電極接觸墊1134、至少一第二汲極電極接觸墊1135以及一第二半導體結構1136。
該至少一第二源極電極接觸墊1133係外露於第二上表層1131，並包含至少一第二凹緣11331，該至少 一第二閘極電極接觸墊1134係與該至少一第二源極電極接觸墊1133相間隔地外露於第二上表層1131，並鄰近於該至少一第二凹緣11331(圖中僅繪示一個)而設置。另外，該至少一第二汲極電極接觸墊1135係外露於第二下表層1132。第二半導體結構1136係位於第二源極電極接觸墊1133與第二汲極電極接觸墊1135之間，其係由現有之電路架構所組成，不再贅述。
該至少一共用源極連結元件114(圖中繪示複數個，僅標示一個)係連結該至少一第一源極電極接觸墊1123、該至少一第二源極電極接觸墊1133與共用源極接腳區域1111中的該至少一第一源極接腳11111與該至少一第二源極接腳11112。
其中，本發明第一較佳實施例中，該至少一共用源極連結元件114係為至少一利用一打線製程所連結之導線，因而第一較佳實施例中有多個導線，且需要一提的是，共用源極連結元件114係連結第一源極電極接觸墊1123與第二源極電極接觸墊1133，並連結第一源極電極接觸墊1123與該至少一第一源極接腳11111，以及連結第二源極電極接觸墊1133與該至少一第二源極接腳11112，但其他實施例中不限於此種設計。
該至少一第一閘極連結元件115係連結第一閘極電極接觸墊1124與第一閘極接腳區域1112之該至少一第一閘極接腳11121，且該至少一第一閘極連結元件115為一導線。
該至少一第二閘極連結元件116係連結第二閘極電極接觸墊1134與第二閘極接腳區域1113之該至少一第二閘極接腳11131，且該至少一第二閘極連結元件116也為一導線，但其他實施例中不限於此。封裝體12係至少局部包覆集成式晶粒組件11，其係為現有技術，不再贅述。
請參閱第三圖，第三圖係顯示本發明第二較佳實施例之共源極式封裝結構之上視圖。如圖所示，與第一較佳實施例不同的地方在於該至少一第一源極電極接觸墊1123a所包含的第一凹緣11231a(圖中為兩個第一源極電極接觸墊1123a各包含一個第一凹緣11231a，僅標示一個)分別位於相對應的角落(其他實施例中可位於相對應的側邊或是不對稱的位置)，且兩個第一閘極電極接觸墊1124a分別設置於兩個第一凹緣11231a，其他均與第一較佳實施例相同，不再贅述。
此外，該至少一第二源極電極接觸墊1133a所包含的兩個第二凹緣11331a(圖中為兩個第二源極電極接觸墊1133a各包含一個第二凹緣11331a，僅標示一個)分別位於相對應的角落(其他實施例中可位於相對應的側邊或是不對稱的位置)，且兩個第二閘極電極接觸墊1134a分別設置於兩個第二凹緣11331a，其他均與第一較佳實施例相同，不再贅述。
請參閱第四圖與第五圖，第四圖係顯示本發明第三較佳實施例之共源極式封裝結構之上視圖，第五圖係顯示本發明第三較佳實施例之共源極式封裝結構之剖 面示意圖。
如圖所示，與第一較佳實施例不同的地方在於該至少一共用源極連結元件114b係為一體成型之金屬板(clip)，並同時接觸於第一源極電極接觸墊1123b、第二源極電極接觸墊1133b、該至少一第一源極接腳11111b與該至少一第二源極接腳11112b，其餘均與第一較佳實施例相同，不再贅述。
綜合以上所述，在採用本發明所提供之共源極式封裝結構之主要技術手段後，由於是將兩個MOEFET的晶粒集成於同一個封裝本體上，並採共源極之設計，因此可有效降低線路損耗而達到更穩定及有效縮小基板面積之功效。另外，由於閘極電極接觸墊的數量為兩個以上時，閘極電極接觸墊設計的位置為MOSFET晶粒相對應的角落，因此在實務上電路的佈線可更為彈性化而增加方便性。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。
1‧‧‧共源極式封裝結構
111‧‧‧集成式組件本體
1111‧‧‧共用源極接腳區域
11111‧‧‧第一源極接腳
11112‧‧‧第二源極接腳
1112‧‧‧第一閘極接腳區域
11121‧‧‧第一閘極接腳
1113‧‧‧第二閘極接腳區域
11131‧‧‧第二閘極接腳
1114‧‧‧第一設置區域
1115‧‧‧第二設置區域
1116‧‧‧隔絕區域
112‧‧‧第一MOSFET晶粒
1123‧‧‧第一源極電極接觸墊
11231‧‧‧第一凹緣
1124‧‧‧第一閘極電極接觸墊
113‧‧‧第二MOSFET晶粒
1133‧‧‧第二源極電極接觸墊
11331‧‧‧第二凹緣
1134‧‧‧第二閘極電極接觸墊
114‧‧‧共用源極連結元件
115‧‧‧第一閘極連結元件
116‧‧‧第二閘極連結元件
L‧‧‧排列方向

Claims (7)

  1. 一種共源極式封裝結構，包含：一集成式晶粒組件，包含：一集成式組件本體，係設有一共用源極接腳區域、一第一閘極接腳區域、一第二閘極接腳區域、一第一設置區域與一第二設置區域，該第一設置區域與該第二設置區域係彼此相間隔；一第一金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET)晶粒(die)，係設置於該第一設置區域，具有一第一上表層，並包含：至少一第一源極電極接觸墊(source electrode pad)，係外露於該第一上表層；以及至少一第一閘極電極接觸墊(gate electrode pad)，係與該至少一第一源極電極接觸墊相間隔地外露於該第一上表層；一第二MOSFET晶粒，係設置於該第二設置區域，具有一第二上表層，並包含：至少一第二源極電極接觸墊，係外露於該第二上表層；以及至少一第二閘極電極接觸墊，係與該至少一第二源極電極接觸墊相間隔地外露於該第二上表層；至少一共用源極連結元件，係連結該至少一第一源極電極接觸墊、該至少一第二源極電極接觸墊與該共用源 極接腳區域；至少一第一閘極連結元件，係連結該第一閘極電極接觸墊與該第一閘極接腳區域；以及至少一第二閘極連結元件，係連結該第二閘極電極接觸墊與該第二閘極接腳區域；以及一封裝體，係至少局部包覆該集成式晶粒組件。
  2. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該共用源極接腳區域包含至少一第一源極接腳與至少一第二源極接腳，該第一閘極接腳區域包含至少一第一閘極接腳，該第二閘極接腳區域包含至少一第二閘極接腳，該至少一第一閘極接腳、該至少一第一源極接腳、該至少一第二源極接腳與該至少一第二閘極接腳係沿一排列方向依序排列。
  3. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該至少一第一源極電極接觸墊包含至少一第一凹緣，該至少一第一閘極電極接觸墊係鄰近於該至少一第一凹緣而設置。
  4. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該至少一第二源極電極接觸墊包含至少一第二凹緣，該至少一第二閘極電極接觸墊係鄰近於該至少一第二凹緣而設置。
  5. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該至少一共用源極連結元件係一體成型之金屬板。
  6. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該至少一共用源極連結元件係為至少一導線。
  7. 如申請專利範圍第1項所述之共源極式封裝結構，其中，該至少一第一閘極連結元件與該至少一第二閘極連結元件係分別為至少一導線。
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