WO2023279794A1 - 开关功率器件 - Google Patents

开关功率器件 Download PDF

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Publication number
WO2023279794A1
WO2023279794A1 PCT/CN2022/086201 CN2022086201W WO2023279794A1 WO 2023279794 A1 WO2023279794 A1 WO 2023279794A1 CN 2022086201 W CN2022086201 W CN 2022086201W WO 2023279794 A1 WO2023279794 A1 WO 2023279794A1
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Prior art keywords
chip
gate
switching power
power device
bonding pad
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PCT/CN2022/086201
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English (en)
French (fr)
Inventor
傅玥
孔令涛
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南京芯干线科技有限公司
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Publication date
Priority claimed from CN202121527454.6U external-priority patent/CN215183941U/zh
Priority claimed from CN202121848994.4U external-priority patent/CN216354227U/zh
Application filed by 南京芯干线科技有限公司 filed Critical 南京芯干线科技有限公司
Priority to US17/938,856 priority Critical patent/US20230032828A1/en
Publication of WO2023279794A1 publication Critical patent/WO2023279794A1/zh

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Definitions

  • the present disclosure relates to the technical field of power devices, in particular to a switching power device.
  • gallium nitride power devices can achieve higher switching frequency, higher system efficiency and power density.
  • the maximum output current capability of a single GaN discrete device is limited by chip cost, packaging form and heat dissipation conditions.
  • multiple GaN power devices need to be connected in parallel to achieve high-power applications and more. Good cooling conditions.
  • the technical problem to be solved in the present disclosure is to provide a switching power device with a symmetrical gate and its parallel structure, which can form a symmetrical gate and source on the switching power device, and the pin design has a high degree of symmetry.
  • the use of symmetrical gate design, as far as the switching power device itself is concerned, makes its internal heating more balanced, improves the ability of the chip to withstand current and brings better reliability.
  • the present disclosure provides a switching power device, which includes a device frame on which a gate, a Kelvin source and a drain are formed; the gate and the Kelvin source are arranged on the One end of the device frame, the drain is arranged at the other end of the device frame; two gates and two Kelvin sources are provided; one end of the device frame is sequentially provided with the gate, Kelvin source Pole, Kelvin source and gate to form a symmetrical pin structure.
  • the switching power device includes a power chip, and the power chip is arranged on the device frame; a chip gate bonding pad, a chip source bonding pad and a chip drain bonding pad are arranged on the power chip.
  • a wire pad; the gate is connected to the chip gate wire pad, the Kelvin source is connected to the source wire pad, and the drain is connected to the chip drain wire pad.
  • each of the chip gate bonding pads is connected to a gate.
  • the area of the chip gate bonding pad is smaller than the area of the chip source bonding pad and the chip drain bonding pad.
  • the device frame is provided with a heat dissipation plate metal, and the power chip is disposed on the heat dissipation plate metal.
  • the metal width of the chip gate bonding pad, the metal width of the chip source bonding pad and the metal width of the chip drain bonding pad are all 50-500 microns.
  • the two chip gate bonding pads of the power chip are connected through a metal interconnection layer.
  • the switching power device is a gallium nitride power device or a silicon carbide power device
  • the power chip is a gallium nitride power chip or a silicon carbide power chip.
  • the switching power device includes a packaging structure
  • the packaging structure is a surface mount package, an in-line package or a flip chip.
  • the package structure has a size of 5mm*6mm, 6mm*8mm or 8mm*8mm.
  • the present disclosure further provides a parallel structure of switching power devices, including a driver chip and two switching power devices; the two switching power devices are connected in parallel, and the output terminal of the driving chip is connected to the gate and the gate of the switching power device.
  • the Kelvin sources are both connected to form a drive circuit.
  • the gates of the two switching power devices are connected through a gate driving wiring, and the gate driving wiring is connected to the output end of the driving chip to form a gate driving circuit.
  • One end of the switching power device of the present disclosure is sequentially provided with the gate, the Kelvin source, the Kelvin source and the gate to form a symmetrical pin structure.
  • the use of symmetrical gate design, as far as the switching power device itself is concerned, makes its internal heating more balanced, improves the ability of the chip to withstand current and brings better reliability.
  • the switching power device of the present disclosure is a symmetrical gate.
  • the gate drive traces can be shared to achieve the same gate drive circuit design.
  • it has shorter leads, which can reduce the parasitic resistance and inductance caused by the package leads, and is beneficial to improve the overall performance of switching power devices.
  • FIG. 1 is a schematic structural diagram of a device frame and a power chip of the present disclosure
  • FIG. 2 is a schematic diagram of the package structure of the switching power device of the present disclosure
  • FIG. 3 is a schematic diagram of a parallel structure of switching power devices of the present disclosure
  • FIG. 4 is a schematic diagram of the internal chip gate circuit and interdigitation distribution of the switching power device of the present disclosure
  • FIG. 5 is a schematic diagram of realizing gate symmetry design of internal chips of the switching power device of the present disclosure.
  • the present disclosure discloses a switching power device and its parallel structure, including:
  • a switching power device wherein the switching power device includes a device frame 11 and a power chip.
  • the aforementioned power chips are arranged on the device frame 11 .
  • the switching power device may be a gallium nitride power device or a silicon carbide power device.
  • the power chip may be a gallium nitride power chip or a silicon carbide power chip.
  • a gate 20 , a Kelvin source 30 and a drain 40 are formed on the above-mentioned device frame 11 .
  • the gate 20 and the Kelvin source 30 are arranged at one end of the device frame 11
  • the drain 40 is arranged at the other end of the device frame 11 .
  • one end of the device frame 11 is provided with a gate 20 , a Kelvin source 30 , a Kelvin source 30 and a gate 20 in sequence, and the other end of the device frame is provided with a drain 40 .
  • the pin structure of the switching power device 10 is a symmetrical design, and the switching power device 10 has a symmetrical gate 20 and a Kelvin source, so that the internal heating of the switching power device 10 can be more balanced, and the ability of the switching power device 10 to withstand current is better. Good and with better reliability.
  • the above switching power device 10 includes a power chip, and a heat sink metal 12 is arranged on the device frame, and the power chip is arranged on the heat sink metal 12 .
  • a chip gate bonding pad 21 , a chip source bonding pad 31 and a chip drain bonding pad 41 are arranged on the power chip.
  • the chip gate bonding pad 21 and the chip source bonding pad 31 are arranged at one end of the power chip
  • the chip drain bonding pad 41 is arranged at the other end of the power chip
  • the chip gate bonding pad 21 is provided with Two
  • chip source bonding pads 31 are arranged between the above two chip gate bonding pads 21 .
  • the above gate 20 is connected to the chip gate bonding pad 21 through metal bonding, the Kelvin source 30 is connected to the chip source bonding pad 31 through metal bonding, and the drain 40 is connected to the chip drain.
  • the wire trays 41 are connected by metal bonding wires, and the source electrode of the chip is directly bonded to the heat sink of the frame.
  • the chip gate bonding pads on the left side and the right side are connected to the driver chip, and the current flows into the power chip through the chip gate bonding pad and the fingers (that is, the white lines in Figure 4).
  • the current at both ends flows in through the closer fingers, for example, each finger between finger 1 and finger 4 passes through The current flowing into the gate bonding pad on the left, and the fingers between fingers 4 and 3 pass through the current flowing into the gate bonding pad of the chip on the right, so the current of finger 3 does not need to be like
  • the traditional technology the solution with only one gate bonding pad
  • it can only flow in from the chip gate bonding pad on the left through the finger 2, but directly from the chip gate bonding pad on the right, thus reducing the The resistance is reduced, thereby reducing the problem of uneven voltage between the left and right fork fingers.
  • the area of the chip gate bonding pad 21 is smaller than the area of the chip source bonding pad 31 and the chip drain bonding pad 41. By setting the above two chip gate bonding pads 21, it can be connected with multiple metal bonding pads. , to ensure reliable connection between the chip gate bonding plate 21 and multiple metal bonding wires, so that the reliability of the switching power device 10 is higher.
  • the above-mentioned power chip substrate is a silicon substrate, and the silicon wafer substrate of the above-mentioned chip generally has a size of six inches or eight inches.
  • the metal width of the chip gate bonding pad 21 , the chip source bonding pad 31 and the chip drain bonding pad 41 in the switching power device 10 are generally 50-500 microns.
  • the above-mentioned switching power device 10 includes a packaging structure, and the above-mentioned packaging structure also has symmetry.
  • the above package structures include but not limited to surface mount package, in-line package and flip chip.
  • the size of the surface mount package includes 5mm*6mm, 6mm*8mm and 8mm*8mm.
  • the package type and size need to be determined.
  • the design of the lead frame is first required.
  • Lead frames can usually be used for some specific chips of different sizes and types.
  • the packaging process includes wafer front-side coating, back grinding, wafer laser and diamond knife cutting, chip fixing on the frame, chip bonding, chip plastic packaging, etc.
  • a parallel structure of switching power devices which includes a driver chip and two switching power devices 10 .
  • the above two switching power devices 10 are connected in parallel, the gates 20 of the two switching power devices 10 are connected through gate drive wiring, and the Kelvin sources 30 of the above two switching power devices 10 are connected through source wiring.
  • the output terminal of the above-mentioned driving chip is connected with the gate 20 and the Kelvin source 30 of the switching power device 10 to form a driving circuit.
  • the above-mentioned gate drive wiring is connected to the output terminal of the driver chip to form a gate drive loop. Since the pins of the switching power device 10 are highly symmetrical, the gate drive wiring can be shared to achieve the same gate drive loop design.
  • FIG. 4 shows the gate circuit and interdigitation distribution inside the chip of the present invention.
  • the symmetrical gate design of the switching power device 10 is beneficial to circuit board wiring design in practical application in electronic systems, and is more suitable for parallel connection of multiple switching power devices 10 .
  • the lead wire is shorter, which can reduce the parasitic resistance and inductance caused by the lead wire of the package, and is beneficial to improve the overall performance of the switching power device 10 .
  • the gate symmetry design of the internal chip of the switching power device can also be implemented in different ways.
  • the two gate bonding pads are elliptical or circular, and are distributed at both ends of the strip-shaped source bonding pads.
  • two gate bonding pads are distributed on both ends of a plurality of source bonding pads arranged at intervals in an elliptical or circular shape.
  • the power chip process generally includes more than ten photomask processes. These processes define the channel of the device, the withstand voltage performance of the device, the size of the device, the peripheral guard ring of the device, and so on.
  • the process of the power chip also includes the subsequent metal interconnection process, including defining the metal width of the chip gate bonding pad 21, the chip source bonding pad 31, and the chip drain bonding pad 41 of the device, and the interconnection of the metal wires. connections to the outside world, etc.
  • the two-chip gate bonding pads 21 of the power chips can be connected through a metal interconnection layer to reduce impedance.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Wire Bonding (AREA)

Abstract

提供了一种开关功率器件（10），其特征在于，包括：器件框架（11），在所述器件框架（11）上形成有门极（20）、开尔文源极（30）和漏极（40）；所述门极（20）和开尔文源极（30）设置在所述器件框架（11）的其中一端，所述漏极（40）设置在器件框架（11）的另一端；所述门极（20）和开尔文源极（30）均设置有两个；所述器件框架（11）的其中一端依次设置有所述门极（20）、开尔文源极（30）、开尔文源极（30）和门极（20），以形成对称式管脚结构。使用对称门极设计，就开关功率器件本身而言，让其内部发热更加均衡，提升芯片承受电流的能力的同时带来更好的可靠性。

Description

开关功率器件 技术领域
本公开涉及功率器件技术领域，尤其是指一种开关功率器件。
背景技术
开关功率器件，例如氮化镓功率器件，其作为第三代半导体材料，氮化镓功率器件可以实现更高的开关频率，更高的系统效率和功率密度。然而单个氮化镓分立器件的最大输出电流能力受到芯片成本、封装形式及散热条件的限制，在一些大功率电力电子应用中，需要并联多个氮化镓功率器件，以实现大功率应用及更好的散热条件。
传统的氮化镓分立器件门极为单管脚。从氮化镓器件的设计角度而言，传统的门极设计会导致芯片内部门极驱动电流供应不均匀，距离门极打线盘较近的部分芯片叉指(元胞)门极供电电压高于那些距离打线盘远一些的叉指(元胞)。这样也会造成芯片热量分布不均，影响芯片性能；在版图设计中难以实现多颗器件并联的驱动回路一致性，回路寄生参数导致驱动同步及均流困难，限制了氮化镓在中高功率的应用。
发明内容
本公开要解决的技术问题是提供一种具有对称门极的开关功率器件及其并联结构，其能够在开关功率器件上形成对称的门极和源极，管脚设计具有高度对称性。使用对称门极设计，就开关功率器件本身而言，让其内部发热更加均衡，提升芯片承受电流的能力的同时带来更好的可靠性。
为解决上述技术问题，本公开提供了一种开关功率器件，其包括器件框架，在所述器件框架上形成有门极、开尔文源极和漏极；所述门极和开尔文源极设置在所述器件框架的其中一端，所述漏极设置在器件框架的另一端；所述门极和开尔文源极均设置有两个；所述器件框架的其中一端依次设置有所述门极、开尔文源极、开尔文源极和门极，以形成对称式管脚结构。
在一实施例中，所述开关功率器件包括功率芯片，所述功率芯片设置在器件框架上；所述功率芯片上设置有芯片门极打线盘、芯片源极打线盘和芯片漏极打线盘；所述门极与所述芯片门极打线盘连接，所述开尔文源极与所述源极打线盘连接，所述漏极与芯片漏极打线盘连接。
在一实施例中，所述芯片门极打线盘设置有两个，每个所述芯片门极打线盘均与一个门极相连接。
在一实施例中，所述芯片门极打线盘的面积小于所述芯片源极打线盘和芯片漏极打线盘的面积。
在一实施例中，所述器件框架上设置有散热盘金属，所述功率芯片设置在所述散热盘金属上。
在一实施例中所述芯片门极打线盘的金属宽度、芯片源极打线盘的金属宽度和芯片漏极打线盘的金属宽度均为50-500微米。
在一实施例中，所述功率芯片的两所述芯片门极打线盘通过金属互联层相连接。
在一实施例中，所述开关功率器件为氮化镓功率器件或碳化硅功率器件，所述功率芯片为氮化镓功率芯片或碳化硅功率芯片。
在一实施例中，所述开关功率器件包括封装结构，所述封装结构为表面贴封装，直插封装或倒装。
在一实施例中，所述封装结构的尺寸为5mm*6mm、6mm*8mm或8mm*8mm。
本公开另提供一种开关功率器件的并联结构，包括驱动芯片和两上述个开关功率器件；两个所述开关功率器件并联，所述驱动芯片的输出端与所述开关功率器件的门极和开尔文源极均连接以形成驱动电路。
在一实施例中，两个所述开关功率器件的门极通过门极驱动走线连接，所述门极驱动走线与所述驱动芯片的输出端连接以形成门极驱动电路。
本公开的上述技术方案相比现有技术具有以下优点：
1、本公开开关功率器件的其中一端依次设置有所述门极、开尔文源极、开尔文源极和门极，以形成对称式管脚结构。使用对称门极设计，就开关功率器件本身而言，让其内部发热更加均衡，提升芯片承受电流的能力的同时带来更好的可靠性。
2、本公开开关功率器件为对称门极。两个开关功率器件并联时，因为管脚高度对称，门极驱动走线可以共用，以便实现相同的门极驱动回路设计。比传统封装具有更短的引线，可以减小因为封装引线带来的寄生电阻和电感，有利于提升开关功率器件的整体性能。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并于说明书一起用于解释本申请的原理。
为了使本公开的内容更容易被清楚的理解，下面根据本公开的具体实施例并结合附图，对本公开作进一步详细的说明，其中：
图1为本公开的器件框架及功率芯片的结构示意图；
图2为本公开开关功率器件的封装结构示意图；
图3为本公开开关功率器件的并联结构示意图；
图4为本公开开关功率器件内部芯片门极电路及叉指分布示意图；
图5为本公开开关功率器件内部芯片的门极对称设计的实现示意图。
说明书附图标记说明：10-开关功率器件，11-器件框架，12-散热盘金属，20-门极，30-开尔文源极，40-漏极，21-芯片门极打线盘，31-芯片源极打线盘，41-芯片漏极打线盘。
本发明的实施方式
下面结合附图和具体实施例对本公开作进一步说明，以使本领域的技术人员可以更好地理解本公开并能予以实施，但所举实施例不作为对本公开的限定。
参照图1～图5所示，本公开公开了一种开关功率器件及其并联结构，包括：
一种开关功率器件，其中，上述开关功率器件包括器件框架11和功率芯片。上述功率芯片设置在器件框架11上。其中，该开关功率器件可以是氮化镓功率器件或碳化硅功率器件。该功率芯片可以是氮化镓功率芯片或碳化硅功率芯片。
其中，在上述器件框架11上形成门极20、开尔文源极30和漏极40。在开关功率器件中，上述门极20和开尔文源极30设置在器件框架11的其中一端，漏极40设置在器件框架11的另外一端。
优选的，参照图1所述，上述器件框架11的其中一端依次设置有门极20、开尔文源极30、开尔文源极30和门极20，上述器件框架的另外一端设置漏极40。开关功率器件10的管脚结构为对称式设计，开关功率器件10具有左右对称的门极20和开尔文源极，使得开关功率器件10的内部发热能够更加均衡，开关功率器件10承受电流的能力更好且具备更好的可靠性。
上述开关功率器件10包括功率芯片，在器件框架上设置有散热盘金属12，功率芯片设置在散热盘金属12上。在上述功率芯片上设置有芯片门极打线盘21、芯片源极打线盘31和芯片漏极打线盘41。其中，芯片门极打线盘21和芯片源极打线盘31设置在上述功率芯片的一端，芯片漏极打线盘41设置在功率芯片的另外一端，上述芯片门极打线盘21设置有两个，芯片源极打线盘31设置在上述两个芯片门极打线盘21之间。上述门极20与芯片门极打线盘21之间通过金属打线相连接，开尔文源极30与芯片源极打线盘31之间通过金属打线相连接，漏极40与芯片漏极打线盘41之间通过金属打线相连接，芯片源极打线直接到框架散热盘。通过设置上述两个芯片门 极打线盘21和芯片源极打线盘31，不仅能够保证设计的对称性，也能够使得打线最短，另外双门极20设计也降低了因为芯片内部门极金属走线较长引起的开关功率器件内部各个叉指(元胞)不均匀性。如图4所示，左边一侧和右边一侧的芯片门极打线盘连接驱动芯片，电流通过芯片门极打线盘和叉指(即图4中的一条条的白线)流入功率芯片内部，由于本申请功率芯片的两端各设置有芯片门极打线盘，因此两端的电流通过较近的叉指流入，例如，叉指1和叉指4之间的各叉指通过的是左边的门极打线盘流入的电流，而叉指4和叉指3之间的各叉指通过的是右边的芯片门极打线盘流入的电流，如此，叉指3的电流不需要像传统技术那样(只有一个门极打线盘的方案)只能从左边的芯片芯片门极打线盘通过叉指2流入，而是从右边的芯片门极打线盘上直接流入，如此减小了电阻，进而减小左右两侧叉指电压不均匀的问题。
上述芯片门极打线盘21的面积小于芯片源极打线盘31和芯片漏极打线盘41的面积，通过设置上述两个芯片门极打线盘21，能够与多根金属打线连接，保证芯片门极打线盘21与多根金属打线连接可靠，使得开关功率器件10的可靠性更高。
优选的，上述功率芯片衬底为硅衬底，上述芯片的晶圆硅衬底的尺寸一般选用六寸或是八寸。上述开关功率器件10中芯片门极打线盘21的金属宽度、芯片源极打线盘31的金属宽度和芯片漏极打线盘41的金属宽度一般为50-500微米。
上述开关功率器件10包括封装结构，上述封装结构也具有对称性。上述封装结构包括但不限于表面贴封装，直插封装和倒装。表面贴封装的尺寸包括5mm*6mm、6mm*8mm和8mm*8mm。
封装制程之前需要确定封装类型和尺寸。以表面贴DFN封装为例，为实现该封装，首先需要有引线框架的设计。引线框架通常可以给一些特定的不同大小和类型的芯片共用。封装过程包括晶圆正面贴膜，背部磨片，晶圆激光及钻石刀切割，芯片在框架上固定，芯片打线，芯片塑封等。
一种开关功率器件的并联结构，其包括驱动芯片以及两个开关功率器件10。上述两个开关功率器件10并联，上述两个开关功率器件10的门极20通过门极驱动走线连接，上述两个开关功率器件10的开尔文源极30通过源极走线连接。上述驱动芯片的输出端与开关功率器件10的门极20和开尔文源极30均连接以形成驱动回路。
上述门极驱动走线与驱动芯片的输出端连接以形成门极驱动回路，由于开关功率 器件10的管脚高度对称，门极驱动走线可以共用，以便实现相同的门极驱动回路设计。图4为本发明芯片内部门极电路及叉指分布。
开关功率器件10通过对称门极设计，在电子系统中的实际应用而言，有利于电路板走线设计，更适用于多个开关功率器件10并联的情况。相比传统封装引线更短，可以减小因为封装引线带来的寄生电阻和电感，有利于提升开关功率器件10的整体性能。
参照图5，开关功率器件内部芯片的门极对称设计也可以有不同的实现方式。例如，两门极打线盘为椭圆形或圆形，其分布在长条状源极打线盘的两端。又例如，两门极打线盘分布在多个间隔分布呈椭圆形状或圆形状的源极打线盘的两端。
功率芯片工艺制程，一般包含十多道光罩工艺。这些工艺定义器件的沟道，器件的耐电压性能，器件的大小，器件外围保护环等。功率芯片的工艺制程还包括后道金属互联工艺，包含定义器件的芯片门极打线盘21、芯片源极打线盘31、芯片漏极打线盘41的金属宽度，金属线走向互联，与外界的联结等。通常金属与金属之间会有氧化物或氮化物等介质形成的保护和绝缘。
在一些实施例中，功率芯片的两芯片门极打线盘21可通过金属互联层相连接以降低阻抗。
显然，上述实施例仅仅是为清楚地说明所作的举例，并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本公开创造的保护范围之中。

Claims (12)

  1. 一种开关功率器件，其特征在于，包括：
    器件框架，在所述器件框架上形成有门极、开尔文源极和漏极；
    所述门极和开尔文源极设置在所述器件框架的其中一端，所述漏极设置在器件框架的另一端；
    所述门极和开尔文源极均设置有两个；所述器件框架的其中一端依次设置有所述门极、开尔文源极、开尔文源极和门极，以形成对称式管脚结构。
  2. 根据权利要求1所述的开关功率器件，其特征在于，所述开关功率器件包括功率芯片，所述功率芯片设置在器件框架上；所述功率芯片上设置有芯片门极打线盘、芯片源极打线盘和芯片漏极打线盘；所述门极与所述芯片门极打线盘连接，所述开尔文源极与所述源极打线盘连接，所述漏极与芯片漏极打线盘连接。
  3. 根据权利要求2所述的开关功率器件，其特征在于，所述芯片门极打线盘设置有两个，每个所述芯片门极打线盘均与一个门极相连接。
  4. 根据权利要求2所述的开关功率器件，其特征在于，所述芯片门极打线盘的面积小于所述芯片源极打线盘和芯片漏极打线盘的面积。
  5. 根据权利要求2所述的开关功率器件，其特征在于，所述器件框架上设置有散热盘金属，所述功率芯片设置在所述散热盘金属上。
  6. 根据权利要求2所述的开关功率器件，其特征在于，所述芯片门极打线盘的金属宽度、芯片源极打线盘的金属宽度和芯片漏极打线盘的金属宽度均为50-500微米。
  7. 根据权利要求2所述的开关功率器件，其特征在于，所述功率芯片的两所述芯片门极打线盘通过金属互联层相连接。
  8. 根据权利要求2所述的开关功率器件，其特征在于，所述开关功率器件为氮化镓功率器件或碳化硅功率器件，所述功率芯片为氮化镓功率芯片或碳化硅功率芯片。
  9. 根据权利要求1所述的开关功率器件，其特征在于，所述开关功率器件包括封装结构，所述封装结构为表面贴封装，直插封装或倒装。
  10. 根据权利要求9所述的开关功率器件，其特征在于，所述封装结构的尺寸为5mm*6mm、6mm*8mm或8mm*8mm。
  11. 一种开关功率器件的并联结构，其特征在于，包括驱动芯片和两个如权利要求1至10任一所述的开关功率器件；两个所述开关功率器件并联，所述驱动芯片的输出端与所述开关功率器件的门极和开尔文源极均连接以形成驱动电路。
  12. 根据权利要求11所述的开关功率器件的并联结构，其特征在于，两个所述开关功率器件的门极通过门极驱动走线连接，所述门极驱动走线与所述驱动芯片的输出端连接以形成门极驱动电路。
PCT/CN2022/086201 2021-07-06 2022-04-12 开关功率器件 WO2023279794A1 (zh)

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