CN106952880A - 半导体装置及使用其的便携式设备 - Google Patents

半导体装置及使用其的便携式设备 Download PDF

Info

Publication number
CN106952880A
CN106952880A CN201611127563.2A CN201611127563A CN106952880A CN 106952880 A CN106952880 A CN 106952880A CN 201611127563 A CN201611127563 A CN 201611127563A CN 106952880 A CN106952880 A CN 106952880A
Authority
CN
China
Prior art keywords
encapsulation
transistor
chip
semiconductor chip
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611127563.2A
Other languages
English (en)
Other versions
CN106952880B (zh
Inventor
柳田正道
小谷野雅史
松浦伸悌
新井宽己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UPI Semiconductor Corp
Original Assignee
Ubiq Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ubiq Semiconductor Corp filed Critical Ubiq Semiconductor Corp
Publication of CN106952880A publication Critical patent/CN106952880A/zh
Application granted granted Critical
Publication of CN106952880B publication Critical patent/CN106952880B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Telephone Set Structure (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

本发明提供一种可实现封装尺寸小型化或薄型化，同时维持MOSFET特性，且可降低导通电阻值的半导体装置及使用其的便携式设备。半导体芯片10的栅极电极26及28被配置于封装2的长边方向(纸面X轴方向)的2个侧面2A及2B附近，而与栅极电极26及28倒装(flip‑chip)封装的栅极端子13及14沿封装2的长边方向延伸，且从2个侧面2A及2B往外部引出。通过此构造，可使半导体芯片尺寸相对于封装尺寸得以最大化，进而可使作为模块的元件特性为高性能化。

Description

半导体装置及使用其的便携式设备
技术领域
本发明是关于一种内建具多个芯片的封装(package)，利用倒装(flip-chip)封装来降低导通电阻值，同时可实现封装尺寸的小型化或薄型化的半导体装置及使用其的便携式设备。
背景技术
众所皆知图6所示的构造是作为用于常见的充电保护装置的半导体装置。于如图所示的树脂封装101中，内建有：作为充电控制用开关的FET 102(以下称“充电用FET102”)；作为放电控制用开关的FET 103(以下称“放电用FET 103”)；及保护IC 104。以虚线105所示的线系树脂封装101的外围线，以此实现1个封装构造。
充电用FET 102的漏极电极透过银胶(silver paste)固定于导线框架(leadframe)106的晶粒座(diepad)内部引脚107上。且，充电用FET 102的源极电极108及栅极电极109透过布线110电性连接于导线框架(frame)106的内部引脚(Inner lead)107。
放电用FET 103及保护IC 104也与充电用FET 102同样，固定于导线框架106，且透过布线110电性连接于内部引脚107(譬如参考专利文献1)。
另外，众所皆知图7所示的构造是作为常见的内建有多个功率金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)的半导体装置。如图所示的2个MOSFET 121及122被固定于导线框架的安装部123上面，安装部123从封装124的一侧面边以4个漏极端子125往外部引出。另外，导线框架形成有与安装部123分离的栅极端子126及127与源极端子128及129，其自与漏极端子125引出的封装124的侧面为相反侧的侧面各别往外部引出。
MOSFET 121的源极电极130与源极端子128通过3条接合布线(bonding wire)131电性连接，MOSFET 122的源极电极132与源极端子129通过3条接合布线133电性连接，如图所示，对源极电极130及132各利用多条接合布线131及133来实现大电流化(譬如参考专利文献2)。
另外，众所皆知图8所示的构造作为常见的内建有MOSFET的半导体装置。如图所示，于形成功率MOSFET的硅芯片141的主面上，形成有源极垫片(源极电极)142及栅极垫片(栅极电极)143，于该背面形成有漏极垫片(未图示)。再者，硅芯片141透过银胶接而接合于晶粒座(die pad)144的上面，使得与晶粒座144连接的漏极用的4个接脚145可从树脂封装146的侧面往外部引出。
硅芯片141的源极垫片142与源极用的接脚148通过铝带(Al ribbon)147电性连接，进而实现降低的导通电阻值。再者，使得源极用的3个接脚148可自与接脚145引出的侧面为相反侧的树脂封装146的侧面侧往外部引出。硅芯片141的栅极垫片143与导线框架通过导线(Al wire)149电性连接，使栅极用的接脚150可从树脂封装146的侧面往外部引出(譬如参考专利文献3)。
专利文献
专利文献1：特开2010-11736号公报
专利文献2：特开2009-38138号公报
专利文献3：特开2013-16837号公报
发明内容
发明所欲解决的问题
近年来，随着行动电话或智能手机等的便携式设备的小型化或薄型化，于其内部使用的电子部件的小型化或薄型化也相对有所要求。因此，有必要实现对应于电子部件的大电流，降低的导通电阻值或封装尺寸的小型化。
如图6所示的半导体装置是用于锂离子电池等的二次电池的保护装置。并且，充电用FET 102、放电用FET 103及保护IC 104并列配置于导线框架106上面，虽形成1个封装化，但是不使用芯片相互间的堆栈构造，将产生难以达成更多的树脂封装的小型化的问题。
另外，于如图6所示的半导体装置上，对于流过大电流的充电用FET 102的源极电极108或放电用FET 103的源极电极111来说，由于连接有布线110的构造关系，所以会产生不易达成降低导通电阻值的问题。
于此，于如图7及图8所示的半导体装置上，虽未内建有IC芯片，但如图7所示，为了要对应于大电流化，众所皆知使用多条粗线的接合布线131及133的构造。另外，于使用多条粗线的接合布线131及133的构造上，不易降低导通电阻值，如图8所示，通过使用铝带147，可对应于大电流化，同时达到降低导通电阻值或连接电阻值的构造亦为常见的。
基于上述，于图6所示的半导体装置上，利用铝带对应于大电流化可降低导通电阻值，然而铝带为了对应于大电流化等，通常会形成涵盖固定于源极电极108及111的几乎整面上的构造。基于此构造，从空间的观点来看，要让保护IC 104堆栈于充电用FET 102及放电用FET 103上面较为困难，使用铝带的构造会产生不易达到树脂封装的小型化的问题。
另外，随着上述便携式设备的薄型化，被收纳于便携式设备的封装内的电路基板，譬如用来进行锂离子电池等的二次电池的充放电的电池管理的保护电路基板的尺寸，就会由于便携式设备的厚度而受到限制。因此，就连被封装于保护电路基板的电子部件的尺寸也会随之受到限制，为了于该尺寸的限制内最大化元件特性，且实现上述降低的导通电阻值，亦寻求基于半导体芯片的电极的布局(layout)或框架的布局的设计。
本发明乃有鉴于上述情况而发明之，对于1个封装(package)中内建有多个芯片构造，提供一种半导体装置及使用其的便携式设备，该半导体装置及使用其的便携式设备使用倒装(flip-chip)封装，可降低导通电阻值，同时也可实现封装尺寸的小型化或薄型化。
解决问题的技术手段
本发明的半导体装置，其中具备：框架；半导体芯片，其中半导体芯片的一主面被倒装封装于框架上；IC芯片，IC芯片堆栈且固定于与半导体芯片的该主面对向的另一主面上；金属导线，金属导线用来电性连接半导体芯片及IC芯片；及封装，封装密封框架、半导体芯片、IC芯片及金属导线，其中，封装具有于长边方向对向的2个侧面，于半导体芯片形成有第一晶体管及第二晶体管，被形成于该主面边的第一晶体管的栅极电极(GateElectrode)被配置于封装的其中一边的侧面边。
另外，于本发明的半导体装置中，第一晶体管的栅极电极所倒装封装的框架沿长边方向延伸且从封装的其中一方侧面露出，第二晶体管的栅极电极所倒装封装的该框架则沿长边方向延伸且从封装的另一方侧面露出。
另外，于本发明的半导体装置中，用来电性连接第一晶体管的栅极电极的金属导线与在第一晶体管的栅极电极及封装的其中一方侧面之间的框架连接；用来电性连接第二晶体管的栅极电极的金属导线与在第二晶体管的栅极电极及封装的另一方侧面之间的框架连接。
另外，于本发明的半导体装置中，半导体芯片具有：被形成于其一主面边的第一晶体管的源极电极；被形成于其一主面边的第二晶体管的源极电极；以及被形成于其另一主面边的第一晶体管及第二晶体管的共用漏极电极(Drain Electrode)，第一晶体管的源极电极所倒装封装的框架从封装的其中一方向的侧面露出；第二晶体管的源极电极所倒装封装的框架则从封装的另一方向的侧面露出。
另外，本发明的半导体装置具有：与第一晶体管的栅极电极并排而配置于该半导体芯片的长边方向的第一晶体管的源极电极；以及与第二晶体管的栅极电极并排而配置于半导体芯片的长边方向的第二晶体管的源极电极，其中第一晶体管的栅极电极与源极电极、以及第二晶体管的栅极电极与源极电极是相对于半导体芯片的中心点配置为旋转对称的。
另外，于本发明的便携式设备中，半导体装置的封装被安装于便携式设备的二次电池的保护电路基板上，封装的长边方向沿着保护电路基板的长边方向配置，保护电路基板的短边方向则沿着便携式设备的壳体的厚度方向配置。
对照现有技术的功效
于本发明的半导体装置，于导线架上倒装封装有半导体芯片，于半导体芯片上面堆栈有用来控制半导体芯片的IC芯片。半导体芯片及IC芯片通过金属导线而电性连接。再者，半导体芯片的2个栅极电极被配置于封装的长边方向中对向的侧面附近，与上述电极倒装封装的导线架从封装的2个侧面露出。通过此构造，可使半导体芯片尺寸相对于封装尺寸得以最大化，且作为模块的元件特性可高性能化。
另外，于本发明的半导体装置上，半导体芯片的2个栅极电极被配置于封装的二侧面边，使得与上述栅极电极倒装封装的导线架沿封装的长边方向来延伸。再者，利用上述金属导线连接于沿长边方向延伸的导线架上，使得半导体芯片尺寸可相对于封装的短边方向达到最大化。
另外，于本发明的半导体装置上，半导体芯片尺寸相对于封装尺寸可得以最大化。
另外，于本发明的半导体装置上，于半导体芯片形成有2个MOSFET，使各源极电极及栅极电极可相对于半导体芯片的中心点配置成旋转对称的。基于此构造，在即使半导体芯片相对于导线架从正确位置旋转到180度的状态而被封装的情况下也可作动，受到封装不当影响的良率进而可得到改善。
另外，于本发明的便携式设备中，可相对于收纳于薄型化壳体内的二次电池的保护电路基板来封装小型化的上述封装。通过此构造，可抑制电力消耗，也可实现可长时间使用的便携式设备。
附图说明
图1为说明本发明的一较佳实施形态的半导体装置的内部构造的平面图。
图2(A)及图2(B)为说明本发明的一较佳实施形态的被内建于半导体装置的半导体芯片，其中图2(A)为平面图，图2(B)为剖面图。
图3(A)及图3(B)为说明本发明的一较佳实施形态的半导体装置的内部构造，其中图3(A)为剖面图，图3(B)为剖面图。
图4(A)至图4(C)为说明本发明的一较佳实施形态的图4(A)为半导体装置的内部构造平面图，图4(B)为被内建于半导体装置的半导体芯片的平面图，图4(C)为用于半导体装置的导线架的平面图。
图5(A)至图5(D)为说明使用本发明的一较佳实施形态的半导体装置的便携式设备的示意图，其中图5(A)为说明便携式设备的壳体的斜视图，图5(B)为电路图，图5(C)为说明便携式设备的二次电池的保护电路基板的平面图，图5(D)为说明便携式设备的二次电池的保护电路基板的平面图。
图6为说明常见的半导体装置的内部构造的平面图。
图7为说明常见的半导体装置的内部构造的平面图。
图8为说明常见的半导体装置的内部构造的平面图。
主要元件符号说明：
1、51 半导体装置
2、52、124 封装
3、4、5、6、7、8、145、148、150 接脚
9、59 导线架
10、60 半导体芯片
11、12、53、55、75、76、128、129 源极端子
13、14、57、58、73、74、126、127 栅极端子
15、61 IC芯片
16、56 VDD端子
17、54 VM端子
18、19、20、21、22、62、63、64、65、66 金属导线
2A、2B、52A、52B、10A、10B、10C 侧面
23、24、67、68、121、122 MOSFET
25、27、69、71、108、111、130、132 源极电极
26、28、34、70、72、109 栅极电极
31 漏极电极
29 半导体基板
a、b、c、d 距离
e、f 宽度
30 外延层
32 背面栅极区域
33 源极区域
35 栅极氧化膜
36 TEOS膜
37 SiN膜
38 PI膜
39 UBM层
40 绝缘层
41、42 开口部
43、44 焊料
45 绝缘性黏着薄膜
60A 中心点
81 便携式设备
82 二次电池
83 保护电路基板
84 壳体
85 二点虚线
101、146 树脂封装
102 充电用FET
103 放电用FET
104 保护IC
105 虚线
106 导线框架
107 内部引脚
110 布线
123 安装部
125 漏极端子
131、133 接合布线
141 硅芯片
142 源极垫片
143 栅极垫片
144 晶粒座
147 铝带
149 导线
P+、P-、B+、B- 电极
具体实施方式
以下，乃基于图面详细说明本发明的一实施形态的半导体装置。又，于说明实施形态之际，相同的构件原则上将使用相同的符号，并省略重复说明的部分。
图1为说明半导体装置的封装内部构造的平面图。图2(A)为说明被内建于半导体装置的半导体芯片的平面图，图2(B)为图2(A)所示半导体芯片的B-B线方向的部分的剖面图。图3(A)为说明图1所示的半导体装置的A-A线方向的剖面的剖面图，图3(B)为说明图1所示的半导体装置的A-A线方向的剖面的变化例的剖面图。
如图1所示，于本实施形态的半导体装置1，其为从点虚线所示的封装2的2个侧面2A、2B往外部引出6根接脚(pin)3、4、5、6、7、8的构造。且，封装2的尺寸，譬如纸面X轴方向(封装的长边方向)的宽度为5mm，纸面Y轴方向(封装的短边方向)的宽度为2mm。此外，于本实施形态，半导体装置1虽以6根接脚说明，但是并非限定于此构造，也可为8根接脚或可适当变更设计。另外，封装尺寸也可适当变更设计。
导线架(或称框体)9是由Cu或Fe-Ni合金等的金属构成且于表面进行Ni-Pd-Au等的电镀。导线架9具有：与半导体芯片10的源极电极25及27(参考图2(A))所倒装封装的源极端子11及12；与半导体芯片10的栅极电极26及28(参考图2(A))所倒装封装的栅极端子13及14；以及透过金属导线21及22与IC芯片15的电极垫片(未图示)连接的作为电源端子的VDD端子16及VM端子17。
源极端子11及12于封装2的中央区域沿着纸面Y轴方向被分割且各自往纸面X轴方向延伸。源极端子11及12与半导体芯片10的源极电极25及27(参考图2(A))倒装封装且固定大部分的半导体芯片10，亦发挥作为晶粒座的作用。
接着，从源极端子11及12于封装2的2个侧面2A及2B往外部引出的部分用来作为源极电极用的接脚4及7。如图所示，利用将接脚4及7的宽度形成为较广，来降低于配线部分的导通电阻值，也可对应于大电流。
栅极端子13及14从封装2的纸面左上或纸面右上各往纸面X轴方向延伸。栅极端子13及14与半导体芯片10的栅极电极26、28(兹参考图2(A))倒装封装。此外，从栅极端子13及14于封装2的2个侧面2A及2B往外部引出的部分用来作为栅极电极用的接脚3及6。
如图所示，栅极端子13及14沿纸面X轴方向以直线状延伸且从封装2的2个侧面2A及2B引出。接着，金属导线18及19从IC芯片15的电极垫片往大略纸面X轴方向延伸，而电性连接半导体芯片10的端部与侧面2A及2B之间的栅极端子13及14。
基于此构造，就不需考量栅极端子13及14与栅极电极用的接脚3及6朝相较于半导体芯片10的端部更靠近纸面Y轴方向的外侧来延伸的空间。接着，于纸面Y轴方向中，半导体芯片10的宽度可相对于封装2的宽度作最大化扩广，且可防止起因于芯片尺寸的缩小化的半导体芯片10的元件特性的恶化。换言之，半导体芯片10的元件特性可相对于封装2的尺寸最大限度地高性能化。
另外，利用接脚3至8形成从封装2的2个侧面2A及2B引出的构造，也使金属导线20、21及22也可从IC芯片15的电极垫片往略为纸面X轴方向延伸。如图所示，电性连接IC芯片15与半导体芯片10的金属导线18至22配置成欧洲字符的略X字型。另外，金属导线18至22之间并不会交叉，可实现封装2的薄型化。
如图2(A)所示，于半导体芯片10形成有2个譬如N通道型MOSFET 23及24的MOSFET23及24，于该主面各形成有源极电极25及27与栅极电极26及28。譬如MOSFET 23、24于纸面左右方向区分而配置，MOSFET 23的栅极电极26被配置于半导体芯片10的纸面右侧上端附近，MOSFET 24的栅极电极28被配置于半导体芯片10的纸面左侧上端附近。
使用图1如上述所言，半导体芯片10虽对导线架9(兹参考图1)倒装封装，但是通过栅极电极26及28配置于半导体芯片10的纸面X轴方向的两端部附近，可实现让栅极电极用的接脚3及6(参考图1)从封装2(参考图1)的2个侧面2A及2B(兹参考图1)往外部引出的构造。
通过上述接脚配置，于纸面Y轴方向之中，利用让半导体芯片10的宽度形成较广，也使得源极电极25及27的宽度也可形成为较宽，于半导体芯片10形成的单元数(cell)亦形成较多。此外，虽然二次电池用的保护电路基板被配置于智能手机等的便携式设备内的狭窄空间内而使尺寸受到限制，但相对于保护电路基板，利用尽量加大的MOSFET 23及24的尺寸，可使模块的特性高性能化。
另外，于各MOSFET 23及24之中，栅极电极26及28与半导体芯片10的侧面10A及10B的相隔距离a短于栅极电极26及28与源极电极25及27的相隔距离b。
通过此构造，成为当半导体芯片10被倒装封装于导线架9之际，不易由于焊接让栅极电极26、28及源极电极25、27产生短路的构造。再者，利用让栅极电极26、28尽量配置于半导体芯片10的侧面10A、10B附近，广阔地配置源极电极25、27，可减少于配线上的导通电阻值，进而可对应于大电流。
相同之，栅极电极26、28与半导体芯片10的侧面10C的相隔距离c，短于源极电极25、27间的相隔距离d。通过该构造，于纸面X轴方向上，形成不易由于焊接使源极电极25、27间产生短路的构造。另外，于纸面Y轴方向上，广阔地配置源极电极25、27，可减少于配线上的导通电阻值，进而可对应于大电流。
又，如图所示，源极电极25、27及栅极电极26、28的角落部形成为曲面状。如上述所言，半导体芯片10虽被倒装封装于导线架9，但是形成为在焊接中使应力不易集中于上述电极25～28的角落部的构造，进而实现不易由于焊锡产生龟裂等或封装不良的构造。
如图2(B)所示，半导体芯片10譬如于N型的半导体基板29上堆栈有N型的外延(epitaxial)层30，于半导体基板29及外延层30形成有2个MOSFET23、24。MOSFET 23、24于半导体芯片10的中央区域形成一定的相隔距离来电性隔离，且于半导体基板29的背面侧形成有共用漏极电极31。
漏极电极31以铝或铝合金为主体的金属层形成为堆栈构造，举例而言，具有10μm至20μm的厚度，利用增加该膜厚度，来降低于配线上的导通电阻值，进而可对应于大电流。此外，利用共用漏极电极31可缩短电流路径，亦可基于高集成化来增加作动区域。
于外延层30形成有多个P型的背面栅极(back gate)区域32，对背面栅极区域32形成N型的源极区域33、中介沟槽(trench)的栅极电极34、栅极氧化膜35。于外延层30形成有上述构造的多个单元(cell)区域。另外，于外延层30上面例如形成TEOS膜36、SiN膜37、PI膜38来作为绝缘层。
另外，于外延层30上面，形成由铝或铝合金等的金属层所形成的源极电极25、27及栅极电极26、28(未图示)。如图2(A)所示，上述绝缘层部分为开口，让源极电极25、27及栅极电极26、28(未图示)可于半导体芯片10的主面边露出。接着，以覆盖露出的源极电极25、27及栅极电极26、28(未图示)的方式形成UBM层39。作为UBM层39例如可为镍-钯-金(Ni-Pd-Au)层。
如图3(A)所示，让绝缘层40以覆盖导线架9的方式来涂布，开口部41、42通过蚀刻形成于绝缘层40上。开口部41、42对应配置于半导体芯片10的源极电极25、27，开口部41、42的形状与源极电极25、27的形状相似。具体而言，如图2(A)所示，源极电极25、27的形状略为欧洲字符的L字型，开口部41、42的形状也是略为欧洲字符的L字型。
如图所示，开口部41、42的开口宽度e形成比源极电极25、27的宽度f稍微广阔的形状。且，于开口部41、42的源极端子11、12上面网版印刷(screen printing)焊膏，倒装封装半导体芯片10，且进行回流(reflow)步骤。另外，也可使用银胶(silver paste)来取代焊膏。
通过使上述开口宽度e比电极宽度f较广，可使得于导线架9侧边的宽度变得较大，让半导体芯片10在稳定于导线架9上的状态下固定焊料43、44的硬化形状。且，利用焊料43、44于安定形状下硬化，可抑制于焊料43、44产生由于应力集中所产生的龟裂，进而防止发生连接不良的现象。
又，虽未图示，但于绝缘层40也形成对应于栅极电极26、28的开口部，该开口形状也与栅极电极26、28的形状相似，成为略微大于栅极电极26、28的形状。
IC芯片15于半导体芯片10的漏极电极31上面透过绝缘性黏着薄膜45加以固定。IC芯片15及半导体芯片10通过绝缘性黏着薄膜45而电性绝缘。此外，IC芯片15的电极垫片(未图示)及源极端子11透过金属导线20电性连接。又，半导体芯片10的漏极电极31虽为露出的状态，但是金属导线20形成为不与漏极电极31接触。
封装2，譬如通过环氧系列的密封树脂等来密封导线架9、半导体芯片10、IC芯片15、金属导线20等。如图所示，源极端子11、12从封装2的背面侧露出，源极电极用的接脚4、7从封装2的侧面2A、2B往外部引出。
如上述所言，于半导体芯片10，流过主电流的源极电极25、27对于导线架9倒装封装，相同地，流过主电流的漏极电极31利用增加金属层的膜厚度来各自实现降低导通电阻值。另外，IC芯片15半导体芯片10的控制IC，半导体芯片10及IC芯片15之间有小电流流通。因此，特别使用减少考量导通电阻值的必要性的金属导线18-22。
通过此构造，于半导体装置1上，不使用金属带且可降低导通电阻值，也可因为降低发热量而实现大电流化或降低的消耗电力。另外，通过不使用金属带的构造，也可实现封装尺寸的小型化。
图3(B)表示图3(A)所示的构造的变化例。如图所示，绝缘性黏着薄膜45覆盖半导体芯片10的漏极电极31整面，于绝缘性黏着薄膜45上面固定有IC芯片15。且，IC芯片15的电极垫片(未图示)及源极端子11透过金属导线20电性连接。
此时，在金属导线20被球焊接于IC芯片15的电极垫片之后，一度地，于绝缘性黏着薄膜45上弯曲，且被针脚式接合(stitch bonding)于源极端子11上面。通过此构造，可降低金属导线20的线环(wire loop)高度，进而实现封装2的薄膜化。并且，无论金属导线20是否连接于绝缘性黏着薄膜45，在位于绝缘性黏着薄膜45附近下，并不会让源极电极25及漏极电极31产生短路。
尤其，如同被封装于二次电池的保护电路基板上的封装2一般，在宽幅地形成于纸面X轴方向的封装2上，为了避免让金属导线20接触到漏极电极31的端部，如图3(A)所示，让金属导线20的环圈顶部倾向为变高。所以，利用将金属导线20的形状作成图3(B)所示的形状，即可降低金属导线20的环圈顶部，可易于实现封装2的薄型化。另外，因应于封装2的长度，金属导线20也可于绝缘性黏着薄膜45上面以多次接触方式形成环圈形状。
其次，图3(B)所示的其他构成要素的构造与图3(A)说明过的构造相同，于此，将省略其说明。
另外，于图3(A)及图3(B)的说明上，虽然已说明于绝缘层40设置有开口部41、42的情况，但是本案并非限定于此情况。举例而言，不使用绝缘层40，且形成与开口部41、42的形状为相同形状的沟槽于导线架9，进而可防止焊料流动的构造亦适用。
另外，虽然已说明开口部41、42的开口宽度e比源极电极25、27宽度f较宽的情况，但是本案并非限定于此情况。譬如于开口宽度e与宽度f为相同宽度的情况下，让焊料43、44的硬化形状为桶子形状，此种情况也可实现不易集中应力于焊料的构造。
其次，基于图4(A)-图4(C)来详细说明作为上述半导体装置的变化例的导线框架形状及半导体芯片的其他实施形态。
图4(A)说明半导体装置内的内部构造的平面图，图4(B)为说明被内建于图4(A)所示的半导体装置的半导体芯片的平面图。
如图4(A)所示，半导体装置51的构造形成为具有从以点虚线所示的封装52的2个侧面52A、52B露出的源极端子53、55；以及露出作为电源端子的VM端子54、VDD端子56。其次，栅极端子57、58虽未从封装52的2个侧面52A、52B露出，但形成从封装52的背面(未图示)露出的构造。
另外，各端子53-56的一部分从封装52露出的露出面，实质上是形成为与侧面52A、52B为同一面，以作为与外部图案连接的外部接脚并加以运作。相同地，栅极端子57、58的一部分从封装52露出的露出面，实质上是形成为与封装52的背面为同一面，以作为与外部图案连接的外部接脚并加以运作。
封装52的尺寸，举例而言于纸面X轴方向(封装的长边方向)的宽度为5mm，于纸面Y轴方向(封装的短边方向)的宽度为2mm。此外，于本实施形态中，虽以6根接脚来说明，但是本案并非限定于此构造，其亦可为8根接脚构造等，并可适当变更设计。
导线架59由铜(Cu)或铁-镍(Fe-Ni)合金等的金属所构成，且于该表面进行镍-钯-金(Ni-Pd-Au)等的电镀。导线架59具有：与半导体芯片60的源极电极69、71(参考图4(B))倒装封装的源极端子53、55；与半导体芯片60的栅极电极70、72(参考图4(B))倒装封装的栅极端子57、58；以及透过金属导线62、63与IC芯片16的电极垫片(未图示)所连接的VM端子54及VDD端子56。
源极端子53、55于封装52的中央区域沿着纸面X轴方向被分割且往各纸面X轴方向延伸。源极端子53、55与半导体芯片60的源极电极69、71倒装封装且固定大部分的半导体芯片60，也发挥作为晶粒座的作用。
栅极端子57、58配置于封装52的纸面左上角落部附近或纸面右下角落部附近。栅极端子57、58与半导体芯片60的栅极电极70、72倒装封装。
栅极端子57、58，譬如为欧洲字符的略L字型，其中一端配置于2个侧面52A、52B附近，该其中一部分往纸面X轴方向延伸。栅极端子57、58具有比半导体芯片60较靠近2个侧面52A、52B边所配置的区域，且对于该区域以金属导线64、65作电性连接。
通过此构造，于纸面Y轴方向中，半导体芯片60的宽度可对封装52的宽度作最大化扩展，且可防止起因于芯片尺寸的缩小化所造成的半导体芯片60的元件特性的恶化。换言之，半导体芯片60的元件特性，相对于封装52的尺寸可最大限度地高性能化。
另外，如图所示，电性连接IC芯片61与半导体芯片60的金属导线62-66配置成欧洲字符的略X字型。且，金属导线62-66之间并不会交叉，而可实现封装62的薄型化。
如图4(B)所示，于半导体芯片60形成有2个譬如N通道型MOSFET 67、68的MOSFET67、68，于其主面各形成有源极电极69、71及栅极电极70、72。譬如，MOSFET67、68于纸面上下方向区分而配置，MOSFET 67的栅极电极70被配置于半导体芯片60的纸面右侧上端部附近，MOSFET 68的栅极电极72被配置于半导体芯片60的纸面左侧下端部附近。
如图所示，于半导体芯片60的一主面上，源极电极69、71及栅极电极70、72相对于半导体芯片60的中心点60A配置为旋转对称的。基于构造，当半导体芯片60于封装于导线架59之际，即使从正确位置旋转到180度的状态而被封装的情况下也可于半导体芯片60内具有2个N通道型的MOSFET 67、68，而不会发生故障，进而改善受到封装不当所影响的良率。
另外，源极电极69、71可于纸面X轴方向上广阔地形成，MOSFET67、68间的对向区域亦可广阔地形成。通过此构造，可缩短半导体芯片60内的电流路径，也可增加电流流通的接合面积，进而提高半导体芯片60的导通电阻特性。
另外，二次电池用的保护电路基板，虽然为了被配置于智能手机等的便携式设备内的狭窄空间而对尺寸有所限制，但是相对于该保护电路基板，可通过尽量增大MOSFET67、68的尺寸，使模块的特性得以高性能化。
其他，使各电极69-72的角落部形成为曲面状的构造或是基于各电极69-72间的相隔距离所产生的效果，与上列使用图1及图2所述的半导体芯片10相同，兹参考其说明，于此则省略其说明。
另外，也可如图4(C)所示的导线架形状，使栅极端子73、74及源极端子75、76形成吊销(Hanger pin)形状的情况亦适用。
其次，图5(A)为说明被收纳于便携式设备的壳体的二次电池及二次电池的保护电路基板的斜视图，图5(B)为说明被形成于保护电路基板的保护电路图，图5(C)及图5(D)用来说明图5(A)所示的保护电路基板的概略平面图。又，于图5(C)及图5(D)中，保护电路图案简略化图示。
如图5(A)所示的行动电话或智能手机等的便携式设备18通过锂电池等的二次电池82来供应电源，二次电池82透过保护电路基板83从外部电源来充电。保护电路基板83是一种用来进行二次电池82的充放电的电池管理的基板。
近年来，随着便携式设备81的小型化或薄型化，二次电池82或保护电路基板83也随之小型化或薄型化。如图所示，举例而言，便携式设备81的壳体84形成为于纸面Z轴方向(导线架的长边方向)的长度为150mm程度，于纸面X轴方向(导线架的短边方向)的长度为80mm程度，于纸面Y轴方向(导线架的厚度方向)的厚度为7mm程度的较薄长方体形状。另外，若在壳体84的厚度为7mm的程度的情况下时，被收纳于其内部的电子部件在纸面Y轴方向上的宽度必须形成为4mm程度的宽度。
图5(B)所示的保护电路，如图5(C)及图5(D)所示，使用保护电路基板83的正反面来形成。且，P+及P-为与设置于便携式设备81的壳体84的+电极及-电极连接的电极，而B+及B-表示与二次电池82的+电极及-电极连接的电极。以二点虚线85所示的电路形成于使用图1-图4(C)说明过的封装2、52内的电路。
如图5(C)及图5(D)的保护电路基板83，为了以并排于纸面XY平面的方式配置于壳体84内，在纸面Y轴方向上的宽度为3mm程度，形成在纸面X轴方向上宽幅的基板。此外，虽然于图5(C)显示从二次电池82侧所见的平面，于该保护电路的配线上封装有使用图1-图4说明的封装2、52。又，图5(D)表示图5(C)所示的保护电路基板83的背面侧的平面。
如上述使用图1及图4所言，封装2、52形成为于纸面Y轴方向较短且于纸面X轴方向较长的形状。如图5(C)所示，封装2、52相对于由于壳体84的厚度方向(纸面Y轴方向)的宽度而受限的保护电路基板83进行封装。且，如上述使用图2(A)及图4(B)所言，半导体芯片10、60的纸面Y轴方向的宽度，可相对于封装2、52的纸面Y轴方向的宽度尽可能宽广地配置。
换言之，封装2、52虽特别限制了在纸面Y轴方向上的宽度，但是利用导线架9、59的布局或MOSFET23、24、67、68的电极的布局等的设计，可使半导体芯片10、60的尺寸最大化，进而实现作为模块的高性能化。
再者，如上述使用图1所言，MOSFET 23的接脚3、4及VDD端子16的接脚5从封装2的侧面2A侧引出，MOSFET 24的接脚6、7及VM端子17的接脚8从封装2的侧面2B侧引出。基于该封装构造，虽然未图式于保护电路基板83上的所有配线，与接脚3-8连接的配线被配置于纸面X轴方向，且于纸面Y轴方向的封装2上下侧无须设置与接脚3-8连接的配线。另外，封装2可相对于保护电路基板83于纸面Y轴方向上较短而于纸面X轴方向上较长来有效率地封装。此外，对于使用图4(A)说明的封装52亦相同。
又，于本实施形态中，虽然说明从封装2的侧面2A、2B往外部引出接脚3-8的情况，但是并非限定于此种情况。例如，也可以为接脚3-8形成为与封装2侧面为相同一面，且不往外部引出的非接脚型的封装情况。
另外，虽然说明从封装2的正反侧露出导线架9的源极端子11、12，栅极端子13、14、VDD端子16及VM端子17的情况，但是并非限定于此情况。例如，通过密封树脂来覆盖直到上述端子的背面侧为止，且让从封装2的侧面2A、2B引出的接脚3-8譬如加工成鸥翼(Gull-wing)形状，封装于保护电路基板的配线的情况亦适用。除此之外，只要不脱离本发明的宗旨的范围内，亦可进行各种变更。

Claims (7)

1.一种半导体装置，其特征在于，包含：
一框架；
一半导体芯片，其一主面被倒装封装于该框架上；
一IC芯片，堆栈且固定于与该半导体芯片的该主面相对的另一主面上；
金属导线，用来电性连接该半导体芯片及该IC芯片；及
一封装，密封该框架、该半导体芯片、该IC芯片及该金属导线，
其中，该封装具有于该长边方向相对的二个侧面，
于该半导体芯片形成一第一晶体管及一第二晶体管，被形成于该主面一侧的该第一晶体管的栅极电极被配置于该封装的其中一边的该侧面一侧，而被形成于该主面一侧的该第二晶体管的栅极电极被配置于该封装的另一边的该侧面一侧。
2.如权利要求1所述的半导体装置，其特征在于，该第一晶体管的栅极电极所倒装封装的该框架于该长边方向延伸，且从该封装的其中一边的该侧面露出，而该第二晶体管的栅极电极所倒装封装的该框架于该长边方向延伸，且从该封装的另一边的该侧面露出。
3.如权利要求1或2所述的半导体装置，其特征在于，与该第一晶体管的栅极电极电性连接的该金属导线，与该第一晶体管的栅极电极及该封装的其中一边的该侧面之间的该框架连接；
与该第二晶体管的栅极电极电性连接的该金属导线，是与该第二晶体管的栅极电极及该封装的另一边的该侧面之间的该框架连接。
4.如权利要求1或2所述的半导体装置，其特征在于，该半导体芯片具有：形成于该主面一侧的该第一晶体管的源极电极；形成于该主面一侧的该第二晶体管的源极电极；以及形成于该另一主面一侧的该第一晶体管及该第二晶体管的共用漏极电极，
该第一晶体管的源极电极所倒装封装的该框架从该封装的其中一边的该侧面露出；该第二晶体管的源极电极所倒装封装的该框架从该封装的另一边的该侧面露出。
5.如权利要求3所述的半导体装置，其特征在于，该半导体芯片具有：形成于该主面一侧的该第一晶体管的源极电极；形成于该主面一侧的该第二晶体管的源极电极；以及形成于该另一主面一侧的该第一晶体管及该第二晶体管的共用漏极电极，
该第一晶体管的源极电极所倒装封装的该框架从该封装的其中一边的该侧面露出；该第二晶体管的源极电极所倒装封装的该框架从该封装的另一边的该侧面露出。
6.如权利要求1所述的半导体装置，其特征在于，包含：与该第一晶体管的栅极电极并排而配置于该半导体芯片的该长边方向上的该第一晶体管的源极电极；以及与该第二晶体管的该栅极电极并排而配置于该半导体芯片的该长边方向上的该第二晶体管的源极电极，
该第一晶体管的栅极电极与源极电极、以及该第二晶体管的栅极电极与源极电极相对于该半导体芯片的一中心点配置为旋转对称的。
7.一种便携式设备，于该便携式设备的一二次电池的一保护电路基板上安装有如权利要求1至6的任一项所述的半导体装置的该封装，其特征在于，
该封装的该长边方向沿着该保护电路基板的一长边方向配置，
该保护电路基板的一短边方向沿着该便携式设备的一壳体的一厚度方向配置。
CN201611127563.2A 2016-01-06 2016-12-09 半导体装置及使用其的便携式设备 Active CN106952880B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-001045 2016-01-06
JP2016001045A JP6795888B2 (ja) 2016-01-06 2016-01-06 半導体装置及びそれを用いた携帯機器

Publications (2)

Publication Number Publication Date
CN106952880A true CN106952880A (zh) 2017-07-14
CN106952880B CN106952880B (zh) 2020-05-19

Family

ID=59226759

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611127563.2A Active CN106952880B (zh) 2016-01-06 2016-12-09 半导体装置及使用其的便携式设备

Country Status (5)

Country Link
US (1) US10490659B2 (zh)
JP (1) JP6795888B2 (zh)
KR (1) KR102122961B1 (zh)
CN (1) CN106952880B (zh)
TW (1) TWI686917B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023279794A1 (zh) * 2021-07-06 2023-01-12 南京芯干线科技有限公司 开关功率器件

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7339933B2 (ja) * 2020-09-11 2023-09-06 株式会社東芝 半導体装置
JP7100219B1 (ja) * 2021-03-29 2022-07-12 ヌヴォトンテクノロジージャパン株式会社 半導体装置および半導体モジュール
TWI820648B (zh) * 2021-03-29 2023-11-01 日商新唐科技日本股份有限公司 半導體裝置、電池保護電路及電源管理電路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368217A (ja) * 2001-06-08 2002-12-20 Sanyo Electric Co Ltd １チップデュアル型絶縁ゲート型半導体装置
US20040070081A1 (en) * 2000-12-11 2004-04-15 Chino-Excel Technologies Corp. Lower the on-resistance in protection circuit of rechargeable battery by using flip-chip technology
JP2005011986A (ja) * 2003-06-19 2005-01-13 Sanyo Electric Co Ltd 半導体装置
US20110278709A1 (en) * 2005-01-05 2011-11-17 Alpha & Omega Semiconductor Incorporated Stacked-die package for battery power management

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4617524B2 (ja) 1999-10-29 2011-01-26 ミツミ電機株式会社 電池保護装置
JP2013016837A (ja) 2007-04-27 2013-01-24 Renesas Electronics Corp 半導体装置
JP2009038138A (ja) 2007-07-31 2009-02-19 Panasonic Corp 樹脂封止型半導体装置およびこれを用いた回路モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040070081A1 (en) * 2000-12-11 2004-04-15 Chino-Excel Technologies Corp. Lower the on-resistance in protection circuit of rechargeable battery by using flip-chip technology
JP2002368217A (ja) * 2001-06-08 2002-12-20 Sanyo Electric Co Ltd １チップデュアル型絶縁ゲート型半導体装置
JP2005011986A (ja) * 2003-06-19 2005-01-13 Sanyo Electric Co Ltd 半導体装置
US20110278709A1 (en) * 2005-01-05 2011-11-17 Alpha & Omega Semiconductor Incorporated Stacked-die package for battery power management

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023279794A1 (zh) * 2021-07-06 2023-01-12 南京芯干线科技有限公司 开关功率器件

Also Published As

Publication number Publication date
JP2017123386A (ja) 2017-07-13
KR20170082460A (ko) 2017-07-14
US10490659B2 (en) 2019-11-26
KR102122961B1 (ko) 2020-06-16
JP6795888B2 (ja) 2020-12-02
US20170194294A1 (en) 2017-07-06
CN106952880B (zh) 2020-05-19
TW201735317A (zh) 2017-10-01
TWI686917B (zh) 2020-03-01

Similar Documents

Publication Publication Date Title
US7843044B2 (en) Semiconductor device
US9589869B2 (en) Packaging solutions for devices and systems comprising lateral GaN power transistors
US9824949B2 (en) Packaging solutions for devices and systems comprising lateral GaN power transistors
US8866283B2 (en) Chip package structure and method of making the same
CN101971332B (zh) 包括嵌入倒装芯片的半导体管芯封装
TWI435507B (zh) 多晶片模組、電氣組體及系統、以及形成多晶片模組之方法
US8669650B2 (en) Flip chip semiconductor device
US5872403A (en) Package for a power semiconductor die and power supply employing the same
US20130106388A1 (en) Semiconductor device
US8436429B2 (en) Stacked power semiconductor device using dual lead frame and manufacturing method
US20100032819A1 (en) Compact Co-packaged Semiconductor Dies with Elevation-adaptive Interconnection Plates
US20100259201A1 (en) Semiconductor device
CN105470245B (zh) 半导体器件
CN103824853B (zh) 应用于开关型调节器的集成电路组件
KR102114785B1 (ko) 멀티-칩 모듈 파워 클립
CN106952880A (zh) 半导体装置及使用其的便携式设备
CN112530919B (zh) 公共源极平面网格阵列封装
EP2309538A2 (en) Package for semiconductor devices
CN220963243U (zh) 晶体管封装装置
JPH11111750A (ja) 半導体装置
KR100639700B1 (ko) 칩 스케일 적층 칩 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20190814

Address after: Taiwan Hsinchu County China jhubei City, Taiwan 5 yuan a Street No. 9 Building 1

Applicant after: Upi Semiconductor Corp.

Address before: 6, No. 5, Taiyuan street, No. 5, Taiyuan street, bamboo North City, county

Applicant before: UBIQ Semiconductor Corp.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant