TW201735317A - 半導體裝置及使用其之便攜式設備 - Google Patents

半導體裝置及使用其之便攜式設備 Download PDF

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Publication number
TW201735317A
TW201735317A TW105140917A TW105140917A TW201735317A TW 201735317 A TW201735317 A TW 201735317A TW 105140917 A TW105140917 A TW 105140917A TW 105140917 A TW105140917 A TW 105140917A TW 201735317 A TW201735317 A TW 201735317A
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Taiwan
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package
transistor
semiconductor wafer
gate electrode
electrode
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TW105140917A
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TWI686917B (zh
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柳田正道
小谷野雅史
松浦伸悌
新井寛己
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力祥半導體股份有限公司
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Abstract

本發明提供一種可實現封裝尺寸之小型化或薄型化，同時維持MOSFET之特性，且可降低導通電阻值之半導體裝置及使用其之便攜式設備。半導體晶片10之閘極電極26及28係被配置於封裝2之長邊方向(紙面X軸方向)之2個側面2A及2B附近，而與閘極電極26及28覆晶(flip-chip)封裝之閘極端子13及14係沿封裝2之長邊方向延伸，且從2個側面2A及2B往外部引出。藉由此構造，可使半導體晶片尺寸相對於封裝尺寸得以最大化，進而可使作為模組之元件特性為高性能化。

Description

半導體裝置及使用其之便攜式設備
本發明關於一種內建具多個晶片之封裝(package)，利用覆晶(flip-chip)封裝來降低導通電阻值，同時可實現封裝尺寸之小型化或薄型化之半導體裝置及使用其之便攜式設備。
眾所皆知圖6所示之構造係作為用於習知之充電保護裝置之半導體裝置。於如圖所示之樹脂封裝101中，內建有：作為充電控制用開關之FET 102(以下稱之「充電用FET 102」)；作為放電控制用開關之FET 103(以下稱之「放電用FET 103」)；及保護IC 104。以虛線105所示之線係樹脂封裝101之外圍線，以此實現1個封裝構造。
充電用FET 102之汲極電極透過銀膠(silver paste)固定於導線框架(lead frame)106之晶粒座(diepad)內部引腳107上。且，充電用FET 102之源極電極108及閘極電極109透過佈線110電性連接於導線框架106之內部引腳(Inner lead)107。
放電用FET 103及保護IC 104也與充電用FET 102同樣，固定於導線框架106，且透過佈線110電性連接於內部引腳107(譬如參考專利文獻1)。
另外，眾所皆知圖7所示之構造係作為習知之內建有多個功率金 屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)之半導體裝置。如圖所示之2個MOSFET 121及122被固定於導線框架之安裝部123上面，安裝部123從封裝124之一側面邊以4個汲極端子125往外部引出。另外，導線框架形成有與安裝部123分離之閘極端子126及127與源極端子128及129，其自與汲極端子125引出之封裝124的側面為相反側之側面各別往外部引出。
MOSFET 121之源極電極130與源極端子128藉由3條接合佈線(bonding wire)131電性連接，MOSFET 122之源極電極132與源極端子129藉由3條接合佈線133電性連接，如圖所示，對源極電極130及132各利用多條接合佈線131及133來實現大電流化(譬如參考專利文獻2)。
另外，眾所皆知圖8所示之構造係作為習知之內建有MOSFET之半導體裝置。如圖所示，於形成功率MOSFET之矽晶片141之主面上，形成有源極墊片(源極電極)142及閘極墊片(閘極電極)143，於該背面形成有汲極墊片(未圖示)。再者，矽晶片141透過銀膠接而接合於晶粒座(die pad)144的上面，使得與晶粒座144連接之汲極用的4個接腳145可從樹脂封裝146之側面往外部引出。
矽晶片141之源極墊片142與源極用之接腳148藉由鋁帶(Al ribbon)147電性連接，進而實現降低之導通電阻值。再者，使得源極用之3個接腳148可自與接腳145引出之側面為相反側的樹脂封裝146之側面側往外部引出。矽晶片141之閘極墊片143與導線框架藉由導線149電性連接，使閘極用之接腳150可從樹脂封裝146之側面往外部引出(譬如參考專利文獻3)。
專利文獻
專利文獻1：特開2010-11736號公報
專利文獻2：特開2009-38138號公報
專利文獻3：特開2013-16837號公報
近年來，隨著行動電話或智慧型手機等之便攜式設備的小型化或薄型化，於其內部使用之電子部件之小型化或薄型化也相對有所要求。因此，有必要實現對應於電子部件之大電流，降低之導通電阻值或封裝尺寸之小型化。
如圖6所示之半導體裝置係用於鋰離子電池等之二次電池之保護裝置。並且，充電用FET 102、放電用FET 103及保護IC 104並列配置於導線框架106上面，雖形成1個封裝化，但是不使用晶片相互間之堆疊構造，將產生難以達成更多之樹脂封裝之小型化的問題。
另外，於如圖6所示之半導體裝置上，對於流過大電流之充電用FET 102之源極電極108或放電用FET 103之源極電極111來說，由於連接有佈線110之構造關係，所以會產生不易達成降低導通電阻值之問題。
於此，於如圖7及圖8所示之半導體裝置上，雖未內建有IC晶片，但如圖7所示，為了要對應於大電流化，眾所皆知係使用多條粗線之接合佈線131及133之構造。另外，於使用多條粗線之接合佈線131及133之構造上，不易降低導通電阻值，如圖8所示，藉由使用鋁帶147，可對應於大電流化，同時達到降低導通電阻值或連接電阻值之構造亦為習知的。
基於上述，於圖6所示之半導體裝置上，利用鋁帶對應於大電流化可降低導通電阻值，然而鋁帶為了對應於大電流化等，通常會形成涵蓋 固定於源極電極108及111之幾乎整面上的構造。基於此構造，從空間之觀點來看，要讓保護IC 104堆疊於充電用FET 102及放電用FET 103上面較為困難，使用鋁帶之構造會產生不易達到樹脂封裝之小型化的問題。
另外，隨著上述便攜式設備之薄型化，被收納於便攜式設備之封裝內之電路基板，譬如用來進行鋰離子電池等之二次電池的充放電之電池管理的保護電路基板之尺寸，就會由於便攜式設備之厚度而受到限制。因此，就連被封裝於保護電路基板之電子部件的尺寸也會隨之受到限制，為了於該尺寸之限制內最大化元件特性，且實現上述降低之導通電阻值，亦尋求基於半導體晶片之電極之佈局(layout)或框架之佈局的設計。
本發明乃有鑑於上述情況而發明之，對於1個封裝中內建有多個晶片構造，提供一種半導體裝置及使用其之便攜式設備，該半導體裝置及使用其之便攜式設備係使用覆晶(flip-chip)封裝，可降低導通電阻值，同時也可實現封裝尺寸之小型化或薄型化。
本發明之半導體裝置，其中具備：框架；半導體晶片，其中半導體晶片之一主面被覆晶封裝於框架上；IC晶片，IC晶片堆疊且固定於與半導體晶片之該主面對向之另一主面上；金屬導線，金屬導線用來電性連接半導體晶片及IC晶片；及封裝，封裝係密封框架、半導體晶片、IC晶片及金屬導線。封裝具有於長邊方向對向之2個側面，於半導體晶片形成有第一電晶體及第二電晶體，被形成於該主面邊之第一電晶體的閘極電極被配置於封裝之其中一邊之側面邊。
另外，於本發明之半導體裝置中，第一電晶體的閘極電極所覆晶封裝之框架係沿長邊方向延伸且從封裝之其中一方側面露出，第二電晶 體的閘極電極所覆晶封裝之該框架則沿長邊方向延伸且從封裝之另一方側面露出。
另外，於本發明之半導體裝置中，用來電性連接第一電晶體的閘極電極之金屬導線與在第一電晶體的閘極電極及封裝之其中一方側面之間的框架連接；用來電性連接第二電晶體的閘極電極之金屬導線與在第二電晶體的閘極電極及封裝之另一方側面之間的框架連接。
另外，於本發明之半導體裝置中，半導體晶片具有：被形成於其一主面邊之第一電晶體的源極電極；被形成於其一主面邊之第二電晶體的源極電極；以及被形成於其另一主面邊之第一電晶體及第二電晶體的共用汲極電極，第一電晶體的源極電極所覆晶封裝之框架係從封裝之其中一方向之側面露出；第二電晶體的源極電極所覆晶封裝之框架則從封裝之另一方向之側面露出。
另外，本發明之半導體裝置具有：與第一電晶體的閘極電極並排而配置於該半導體晶片之長邊方向之第一電晶體之源極電極；以及與第二電晶體的閘極電極並排而配置於半導體晶片之長邊方向之第二電晶體之源極電極，其中第一電晶體的閘極電極與源極電極、以及第二電晶體的閘極電極與源極電極係相對於半導體晶片之中心點配置為旋轉對稱的。
另外，於本發明之便攜式設備中，半導體裝置之封裝被安裝於便攜式設備之二次電池的保護電路基板上，封裝之長邊方向係沿著保護電路基板之長邊方向配置，保護電路基板之短邊方向則沿著便攜式設備之殼體之厚度方向配置。
於本發明之半導體裝置，於導線架上覆晶封裝有半導體晶片，於半導體晶片上面堆疊有用來控制半導體晶片之IC晶片。半導體晶片及IC晶片藉由金屬導線而電性連接。再者，半導體晶片之2個閘極電極被配置於封裝之長邊方向中對向之側面附近，與上述電極覆晶封裝之導線架從封裝之2個側面露出。藉由此構造，可使半導體晶片尺寸相對於封裝尺寸得以最大化，且作為模組之元件特性可高性能化。
另外，於本發明之半導體裝置上，半導體晶片之2個閘極電極被配置於封裝之二側面邊，使得與上述閘極電極覆晶封裝之導線架沿封裝之長邊方向來延伸。再者，利用上述金屬導線連接於沿長邊方向延伸之導線架上，使得半導體晶片尺寸可相對於封裝之短邊方向達到最大化。
另外，於本發明之半導體裝置上，半導體晶片尺寸相對於封裝尺寸可得以最大化。
另外，於本發明之半導體裝置上，於半導體晶片形成有2個MOSFET，使各源極電極及閘極電極可相對於半導體晶片之中心點配置成旋轉對稱的。基於此構造，在即使半導體晶片相對於導線架從正確位置旋轉到180度之狀態而被封裝之情況下也可作動，受到封裝不當影響之良率進而可得到改善。
另外，於本發明之便攜式設備中，可相對於收納於薄型化殼體內之二次電池的保護電路基板來封裝小型化之上述封裝。藉由此構造，可抑制電力消耗，也可實現可長時間使用之便攜式設備。
1、51‧‧‧半導體裝置
2、52、124‧‧‧封裝
3、4、5、6、7、8、145、148、150‧‧‧接腳
9、59‧‧‧導線架
10、60‧‧‧半導體晶片
11、12、53、55、75、76、128、129‧‧‧源極端子
13、14、57、58、73、74、126、127‧‧‧閘極端子
15、61‧‧‧IC晶片
16、56‧‧‧VDD端子
17、54‧‧‧VM端子
18、19、20、21、22、62、63、64、65、66‧‧‧金屬導線
2A、2B、52A、52B、10A、10B、10C‧‧‧側面
23、24、67、68、121、122‧‧‧MOSFET
25、27、69、71、108、111、130、132‧‧‧源極電極
26、28、34、70、72、109‧‧‧閘極電極
31‧‧‧汲極電極
29‧‧‧半導體基板
a、b、c、d‧‧‧距離
e、f‧‧‧寬度
30‧‧‧晶膜層
32‧‧‧背面閘極區域
33‧‧‧源極區域
35‧‧‧閘極氧化膜
36‧‧‧TEOS膜
37‧‧‧SiN膜
38‧‧‧PI膜
39‧‧‧UBM層
40‧‧‧絕緣層
41、42‧‧‧開口部
43、44‧‧‧焊料
45‧‧‧絕緣性黏著薄膜
60A‧‧‧中心點
81‧‧‧便攜式設備
82‧‧‧二次電池
83‧‧‧保護電路基板
84‧‧‧殼體
85‧‧‧二點虛線
101、146‧‧‧樹脂封裝
102‧‧‧充電用FET
103‧‧‧放電用FET
104‧‧‧保護IC
105‧‧‧虛線
106‧‧‧導線框架
107‧‧‧內部引腳
110‧‧‧佈線
123‧‧‧安裝部
125‧‧‧汲極端子
131、133‧‧‧接合佈線
141‧‧‧矽晶片
142‧‧‧源極墊片
143‧‧‧閘極墊片
144‧‧‧晶粒座
147‧‧‧鋁帶
149‧‧‧導線
P+、P-、B+、B-‧‧‧電極
圖1為說明本發明之一較佳實施形態之半導體裝置之內部構造的平面圖。
圖2(A)及圖2(B)為說明本發明之一較佳實施形態之被內建於半導體裝置之半導體晶片，其中圖2(A)為平面圖，圖2(B)為剖面圖。
圖3(A)及圖3(B)為說明本發明之一較佳實施形態之半導體裝置之內部構造，其中圖3(A)為剖面圖，圖3(B)為剖面圖。
圖4(A)至圖4(C)為說明本發明之一較佳實施形態之圖4(A)為半導體裝置之內部構造平面圖，圖4(B)為被內建於半導體裝置之半導體晶片之平面圖，圖4(C)為用於半導體裝置之導線架之平面圖。
圖5(A)至圖5(D)為說明使用本發明之一較佳實施形態之半導體裝置之便攜式設備之示意圖，其中圖5(A)為說明便攜式設備之殼體之斜視圖，圖5(B)為電路圖，圖5(C)為說明便攜式設備之二次電池之保護電路基板之平面圖，圖5(D)為說明便攜式設備之二次電池之保護電路基板之平面圖。
圖6為說明習知之半導體裝置之內部構造之平面圖。
圖7為說明習知之半導體裝置之內部構造之平面圖。
圖8為說明習知之半導體裝置之內部構造之平面圖。
以下，乃基於圖面詳細說明本發明之一實施形態之半導體裝置。又，於說明實施形態之際，相同之構件原則上將使用相同之符號，並省略重複說明之部分。
圖1為說明半導體裝置之封裝內部構造之平面圖。圖2(A)為說明 被內建於半導體裝置之半導體晶片之平面圖，圖2(B)為圖2(A)所示半導體晶片之B-B線方向之部分的剖面圖。圖3(A)為說明圖1所示之半導體裝置之A-A線方向之剖面的剖面圖，圖3(B)為說明圖1所示之半導體裝置之A-A線方向之剖面之變化例之剖面圖。
如圖1所示，於本實施形態之半導體裝置1，其為從點虛線所示之封裝2之2個側面2A、2B往外部引出6根接腳(pin)3、4、5、6、7、8之構造。封裝2之尺寸，譬如紙面X軸方向(封裝之長邊方向)之寬度為5mm，紙面Y軸方向(封裝之短邊方向)之寬度為2mm。此外，於本實施形態，半導體裝置1雖以6根接腳說明，但是並非限定於此構造，也可為8根接腳或可適當變更設計。另外，封裝尺寸也可適當變更設計。
導線架(或稱框體)9係由Cu或Fe-Ni合金等之金屬構成且於表面進行Ni-Pd-Au等之電鍍。導線架9具有：與半導體晶片10之源極電極25及27(參考圖2(A))所覆晶封裝之源極端子11及12；與半導體晶片10之閘極電極26及28(參考圖2(A))所覆晶封裝之閘極端子13及14；以及透過金屬導線21及22與IC晶片15之電極墊片(未圖示)連接之作為電源端子的VDD端子16及VM端子17。
源極端子11及12於封裝2之中央區域沿著紙面Y軸方向被分割且各自往紙面X軸方向延伸。源極端子11及12與半導體晶片10之源極電極25及27(參考圖2(A))覆晶封裝且固定大部分之半導體晶片10，亦發揮作為晶粒座之作用。
接著，從源極端子11及12於封裝2之2個側面2A及2B往外部引出之部分用來作為源極電極用之接腳4及7。如圖所示，利用將接腳4及7之寬 度形成為較廣，來降低於配線部分之導通電阻值，也可對應於大電流。
閘極端子13及14從封裝2之紙面左上或紙面右上各往紙面X軸方向延伸。閘極端子13及14與半導體晶片10之閘極電極26、28(茲參考圖2(A))覆晶封裝。此外，從閘極端子13及14於封裝2之2個側面2A及2B往外部引出之部分用來作為閘極電極用之接腳3及6。
如圖所示，閘極端子13及14沿紙面X軸方向以直線狀延伸且從封裝2之2個側面2A及2B引出。接著，金屬導線18及19係從IC晶片15之電極墊片往大略紙面X軸方向延伸，而電性連接半導體晶片10之端部與側面2A及2B之間的閘極端子13及14。
基於此構造，就不需考量閘極端子13及14與閘極電極用之接腳3及6朝相較於半導體晶片10之端部更靠近紙面Y軸方向之外側來延伸之空間。接著，於紙面Y軸方向中，半導體晶片10之寬度可相對於封裝2之寬度作最大化擴廣，且可防止起因於晶片尺寸之縮小化之半導體晶片10之元件特性之惡化。換言之，半導體晶片10之元件特性可相對於封裝2之尺寸最大限度地高性能化。
另外，利用接腳3至8形成從封裝2之2個側面2A及2B引出之構造，也使金屬導線20、21及22也可從IC晶片15之電極墊片往略為紙面X軸方向延伸。如圖所示，電性連接IC晶片15與半導體晶片10之金屬導線18至22係配置成歐洲字符之略X字型。另外，金屬導線18至22之間並不會交叉，可實現封裝2之薄型化。
如圖2(A)所示，於半導體晶片10形成有2個譬如N通道型MOSFET 23及24之MOSFET 23及24，於該主面各形成有源極電極25及27與閘極電極 26及28。譬如MOSFET 23、24係於紙面左右方向區分而配置，MOSFET 23之閘極電極26被配置於半導體晶片10之紙面右側上端附近，MOSFET 24之閘極電極28被配置於半導體晶片10之紙面左側上端附近。
使用圖1如上述所言，半導體晶片10雖對導線架9(茲參考圖1)覆晶封裝，但是藉由閘極電極26及28配置於半導體晶片10之紙面X軸方向之兩端部附近，可實現讓閘極電極用之接腳3及6(參考圖1)從封裝2(參考圖1)之2個側面2A及2B(茲參考圖1)往外部引出之構造。
藉由上述接腳配置，於紙面Y軸方向之中，利用讓半導體晶片10之寬度形成較廣，也使得源極電極25及27之寬度也可形成為較寬，於半導體晶片10形成之單元數(cell)亦形成較多。此外，雖然二次電池用之保護電路基板被配置於智慧型手機等之便攜式設備內之狹窄空間內而使尺寸受到限制，但相對於保護電路基板，利用盡量加大之MOSFET 23及24之尺寸，可使模組之特性高性能化。
另外，於各MOSFET 23及24之中，閘極電極26及28與半導體晶片10之側面10A及10B的相隔距離a係短於閘極電極26及28與源極電極25及27之相隔距離b。
藉由此構造，成為當半導體晶片10被覆晶封裝於導線架9之際，不易由於焊接讓閘極電極26、28及源極電極25、27產生短路之構造。再者，利用讓閘極電極26、28盡量配置於半導體晶片10之側面10A、10B附近，廣闊地配置源極電極25、27，可減少於配線上之導通電阻值，進而可對應於大電流。
相同之，閘極電極26、28與半導體晶片10之側面10C之相隔距離 c，短於源極電極25、27間之相隔距離d。藉由該構造，於紙面X軸方向上，形成不易由於焊接使源極電極25、27間產生短路之構造。另外，於紙面Y軸方向上，廣闊地配置源極電極25、27，可減少於配線上之導通電阻值，進而可對應於大電流。
又，如圖所示，源極電極25、27及閘極電極26、28之角落部形成為曲面狀。如上述所言，半導體晶片10雖被覆晶封裝於導線架9，但是形成為在焊接中使應力不易集中於上述電極25~28之角落部的構造，進而實現不易由於銲錫產生龜裂等或封裝不良之構造。
如圖2(B)所示，半導體晶片10譬如於N型之半導體基板29上堆疊有N型之晶膜(epitaxial)層30，於半導體基板29及磊晶層30形成有2個MOSFET 23、24。MOSFET 23、24於半導體晶片10之中央區域形成一定之相隔距離來電性隔離，且於半導體基板29之背面側形成有共用汲極電極31。
汲極電極31係以鋁或鋁合金為主體之金屬層形成為堆疊構造，舉例而言，具有10μm至20μm之厚度，利用增加該膜厚度，來降低於配線上之導通電阻值，進而可對應於大電流。此外，利用共用汲極電極31可縮短電流路徑，亦可基於高集成化來增加作動區域。
於晶膜層30形成有多個P型之背面閘極(back gate)區域32，對背面閘極區域32形成N型之源極區域33、中介溝槽(trench)之閘極電極34、閘極氧化膜35。於晶膜層30形成有上述構造之多個單元(cell)區域。另外，於晶膜層30上面例如形成TEOS膜36、SiN膜37、PI膜38來作為絕緣層。
另外，於晶膜層30上面，形成由鋁或鋁合金等之金屬層所形成之源極電極25、27及閘極電極26、28(未圖示)。如圖2(A)所示，上述絕緣 層部分為開口，讓源極電極25、27及閘極電極26、28(未圖示)可於半導體晶片10之主面邊露出。接著，以覆蓋露出之源極電極25、27及閘極電極26、28(未圖示)之方式形成UBM層39。作為UBM層39例如可為鎳-鈀-金(Ni-Pd-Au)層。
如圖3(A)所示，讓絕緣層40以覆蓋導線架9之方式來塗佈，開口部41、42藉由蝕刻形成於絕緣層40上。開口部41、42係對應配置於半導體晶片10之源極電極25、27，開口部41、42之形狀係與源極電極25、27之形狀相似。具體而言，如圖2(A)所示，源極電極25、27之形狀略為歐洲字符之L字型，開口部41、42之形狀也是略為歐洲字符之L字型。
如圖所示，開口部41、42之開口寬度e係形成比源極電極25、27之寬度f稍微廣闊之形狀。且，於開口部41、42之源極端子11、12上面網版印刷(screen printing)焊膏，覆晶封裝半導體晶片10，且進行回流(reflow)步驟。另外，也可使用銀膠(silver paste)來取代焊膏。
藉由使上述開口寬度e比電極寬度f較廣，可使得於導線架9側邊之寬度變得較大，讓半導體晶片10在穩定於導線架9上之狀態下固定焊料43、44之硬化形狀。且，利用銲料43、44於安定形狀下硬化，可抑制於焊料43、44產生由於應力集中所產生之龜裂，進而防止發生連接不良之現象。
又，雖未圖示，但於絕緣層40也形成對應於閘極電極26、28之開口部，該開口形狀也與閘極電極26、28之形狀相似，成為略微大於閘極電極26、28之形狀。
IC晶片15係於半導體晶片10之汲極電極31上面透過絕緣性黏著薄膜45加以固定。IC晶片15及半導體晶片10係藉由絕緣性黏著薄膜45而電 性絕緣。此外，IC晶片15之電極墊片(未圖示)及源極端子11係透過金屬導線20電性連接。又，半導體晶片10之汲極電極31雖為露出之狀態，但是金屬導線20係形成為不與汲極電極31接觸。
封裝2，譬如藉由環氧系列之密封樹脂等來密封導線架9、半導體晶片10、IC晶片15、金屬導線20等。如圖所示，源極端子11、12係從封裝2之背面側露出，源極電極用之接腳4、7從封裝2之側面2A、2B往外部引出。
如上述所言，於半導體晶片10，流過主電流之源極電極25、27係對於導線架9覆晶封裝，相同地，流過主電流之汲極電極31係利用增加金屬層之膜厚度來各自實現降低導通電阻值。另外，IC晶片15係半導體晶片10之控制IC，半導體晶片10及IC晶片15之間有小電流流通。因此，特別使用減少考量導通電阻值之必要性的金屬導線18-22。
藉由此構造，於半導體裝置1上，不使用金屬帶且可降低導通電阻值，也可因為降低發熱量而實現大電流化或降低之消耗電力。另外，藉由不使用金屬帶之構造，也可實現封裝尺寸之小型化。
圖3(B)係表示圖3(A)所示之構造的變化例。如圖所示，絕緣性黏著薄膜45覆蓋半導體晶片10之汲極電極31整面，於絕緣性黏著薄膜45上面固定有IC晶片15。且，IC晶片15之電極墊片(未圖示)及源極端子11係透過金屬導線20電性連接。
此時，在金屬導線20被球焊接於IC晶片15之電極墊片之後，一度地，於絕緣性黏著薄膜45上彎曲，且被針腳式接合(stitch bonding)於源極端子11上面。藉由此構造，可降低金屬導線20之線環(wire loop)高度， 進而實現封裝2之薄膜化。並且，無論金屬導線20是否連接於絕緣性黏著薄膜45，在位於絕緣性黏著薄膜45附近下，並不會讓源極電極25及汲極電極31產生短路。
尤其，如同被封裝於二次電池之保護電路基板上之封裝2一般，在寬幅地形成於紙面X軸方向之封裝2上，為了避免讓金屬導線20接觸到汲極電極31之端部，如圖3(A)所示，讓金屬導線20之環圈頂部傾向為變高。所以，利用將金屬導線20之形狀作成圖3(B)所示之形狀，即可降低金屬導線20之環圈頂部，可易於實現封裝2之薄型化。另外，因應於封裝2之長度，金屬導線20也可於絕緣性黏著薄膜45上面以複數次接觸方式形成環圈形狀。
其次，圖3(B)所示之其他構成要素之構造係與圖3(A)說明過之構造相同，於此，將省略其說明。
另外，於圖3(A)及圖3(B)之說明上，雖然已說明於絕緣層40設置有開口部41、42之情況，但是本案並非限定於此情況。舉例而言，不使用絕緣層40，且形成與開口部41、42之形狀為相同形狀的溝槽於導線架9，進而可防止銲料流動之構造亦適用。
另外，雖然已說明開口部41、42之開口寬度e比源極電極25、27寬度f較寬之情況，但是本案並非限定於此情況。譬如於開口寬度e與寬度f為相同寬度之情況下，讓銲料43、44之硬化形狀為桶子形狀，此種情況也可實現不易集中應力於銲料之構造。
其次，基於圖4(A)-圖4(C)來詳細說明作為上述半導體裝置之變化例的導線框架形狀及半導體晶片之其他實施形態。
圖4(A)係說明半導體裝置內之內部構造之平面圖，圖4(B)為說明 被內建於圖4(A)所示之半導體裝置的半導體晶片之平面圖。
如圖4(A)所示，半導體裝置51之構造係形成為具有從以點虛線所示之封裝52之2個側面52A、52B露出之源極端子53、55；以及露出作為電源端子之VM端子54、VDD端子56。其次，閘極端子57、58雖未從封裝52之2個側面52A、52B露出，但係形成從封裝52之背面(未圖示)露出之構造。
另外，各端子53-56之一部分從封裝52露出之露出面，實質上係形成為與側面52A、52B為同一面，以作為與外部圖案連接之外部接腳並加以運作。相同地，閘極端子57、58之一部分從封裝52露出之露出面，實質上係形成為與封裝52之背面為同一面，以作為與外部圖案連接之外部接腳並加以運作。
封裝52之尺寸，舉例而言於紙面X軸方向(封裝之長邊方向)之寬度為5mm，於紙面Y軸方向(封裝之短邊方向)之寬度為2mm。此外，於本實施形態中，雖以6根接腳來說明，但是本案並非限定於此構造，其亦可為8根接腳構造等，並可適當變更設計。
導線架59係由銅(Cu)或鐵-鎳(Fe-Ni)合金等之金屬所構成，且於該表面進行鎳-鈀-金(Ni-Pd-Au)等之電鍍。導線架59具有：與半導體晶片60之源極電極69、71(參考圖4(B))覆晶封裝之源極端子53、55；與半導體晶片60之閘極電極70、72(參考圖4(B))覆晶封裝之閘極端子57、58；以及透過金屬導線62、63與IC晶片16之電極墊片(未圖示)所連接之VM端子54及VDD端子56。
源極端子53、55於封裝52之中央區域沿著紙面X軸方向被分割且往各紙面X軸方向延伸。源極端子53、55與半導體晶片60之源極電極69、71 覆晶封裝且固定大部分之半導體晶片60，也發揮作為晶粒座之作用。
閘極端子57、58配置於封裝52之紙面左上角落部附近或紙面右下角落部附近。閘極端子57、58係與半導體晶片60之閘極電極70、72覆晶封裝。
閘極端子57、58，譬如為歐洲字符之略L字型，其中一端係配置於2個側面52A、52B附近，該其中一部分係往紙面X軸方向延伸。閘極端子57、58具有比半導體晶片60較靠近2個側面52A、52B邊所配置之區域，且對於該區域以金屬導線64、65作電性連接。
藉由此構造，於紙面Y軸方向中，半導體晶片60之寬度可對封裝52之寬度作最大化擴展，且可防止起因於晶片尺寸之縮小化所造成之半導體晶片60之元件特性的惡化。換言之，半導體晶片60之元件特性，相對於封裝52之尺寸可最大限度地高性能化。
另外，如圖所示，電性連接IC晶片61與半導體晶片60之金屬導線62-66係配置成歐洲字符之略X字型。且，金屬導線62-66之間並不會交叉，而可實現封裝62之薄型化。
如圖4(B)所示，於半導體晶片60形成有2個譬如N通道型MOSFET 67、68之MOSFET 67、68，於其主面各形成有源極電極69、71及閘極電極70、72。譬如，MOSFET67、68於紙面上下方向區分而配置，MOSFET 67之閘極電極70被配置於半導體晶片60之紙面右側上端部附近，MOSFET 68之閘極電極72係被配置於半導體晶片60之紙面左側下端部附近。
如圖所示，於半導體晶片60之一主面上，源極電極69、71及閘極電極70、72係相對於半導體晶片60之中心點60A配置為旋轉對稱的。基於 構造，當半導體晶片60於封裝於導線架59之際，即使從正確位置旋轉到180度之狀態而被封裝之情況下也可於半導體晶片60內具有2個N通道型之MOSFET 67、68，而不會發生故障，進而改善受到封裝不當所影響之良率。
另外，源極電極69、71可於紙面X軸方向上廣闊地形成，MOSFET67、68間之對向區域亦可廣闊地形成。藉由此構造，可縮短半導體晶片60內之電流路徑，也可增加電流流通之接合面積，進而提高半導體晶片60之導通電阻特性。
另外，二次電池用的保護電路基板，雖然為了被配置於智慧型手機等之便攜式設備內的狹窄空間而對尺寸有所限制，但是相對於該保護電路基板，可藉由盡量增大MOSFET 67、68之尺寸，使模組之特性得以高性能化。
其他，使各電極69-72之角落部形成為曲面狀之構造或是基於各電極69-72間之相隔距離所產生之效果，係與上列使用圖1及圖2所述之半導體晶片10相同，茲參考其說明，於此則省略其說明。
另外，也可如圖4(C)所示之導線架形狀，使閘極端子73、74及源極端子75、76形成吊銷(Hanger pin)形狀之情況亦適用。
其次，圖5(A)為說明被收納於便攜式設備之殼體之二次電池及二次電池之保護電路基板之斜視圖，圖5(B)為說明被形成於保護電路基板之保護電路圖，圖5(C)及圖5(D)係用來說明圖5(A)所示之保護電路基板之概略平面圖。又，於圖5(C)及圖5(D)中，保護電路圖案係簡略化圖示。
如圖5(A)所示之行動電話或智慧型手機等之便攜式設備18係藉由鋰電池等之二次電池82來供應電源，二次電池82係透過保護電路基板83從 外部電源來充電。保護電路基板83係一種用來進行二次電池82之充放電之電池管理之基板。
近年來，隨著便攜式設備81之小型化或薄型化，二次電池82或保護電路基板83也隨之小型化或薄型化。如圖所示，舉例而言，便攜式設備81之殼體84係形成為於紙面Z軸方向(導線架之長邊方向)之長度為150mm程度，於紙面X軸方向(導線架之短邊方向)之長度為80mm程度，於紙面Y軸方向(導線架之厚度方向)之厚度為7mm程度之較薄長方體形狀。另外，若在殼體84之厚度為7mm之程度的情況下時，被收納於其內部之電子部件在紙面Y軸方向上之寬度必須形成為4mm程度之寬度。
圖5(B)所示之保護電路，如圖5(C)及圖5(D)所示，係使用保護電路基板83之正反面來形成。且，P+及P-係為與設置於便攜式設備81之殼體84之+電極及-電極連接之電極，而B+及B-係表示與二次電池82之+電極及-電極連接之電極。以二點虛線85所示之電路係形成於使用圖1-圖4(C)說明過之封裝2、52內的電路。
如圖5(C)及圖5(D)之保護電路基板83，為了以並排於紙面XY平面之方式配置於殼體84內，在紙面Y軸方向上之寬度為3mm程度，形成在紙面X軸方向上寬幅之基板。此外，雖然於圖5(C)顯示從二次電池82側所見之平面，於該保護電路之配線上封裝有使用圖1-圖4說明之封裝2、52。又，圖5(D)係表示圖5(C)所示之保護電路基板83之背面側之平面。
如上述使用圖1及圖4所言，封裝2、52係形成為於紙面Y軸方向較短且於紙面X軸方向較長之形狀。如圖5(C)所示，封裝2、52係相對於由於殼體84之厚度方向(紙面Y軸方向)之寬度而受限的保護電路基板83進行 封裝。且，如上述使用圖2(A)及圖4(B)所言，半導體晶片10、60之紙面Y軸方向之寬度，可相對於封裝2、52之紙面Y軸方向之寬度盡可能寬廣地配置。
換言之，封裝2、52雖特別限制了在紙面Y軸方向上之寬度，但是利用導線架9、59之佈局或MOSFET23、24、67、68之電極的佈局等之設計，可使半導體晶片10、60之尺寸最大化，進而實現作為模組之高性能化。
再者，如上述使用圖1所言，MOSFET 23之接腳3、4及VDD端子16之接腳5從封裝2之側面2A側引出，MOSFET 24之接腳6、7及VM端子17之接腳8從封裝2之側面2B側引出。基於該封裝構造，雖然未圖式於保護電路基板83上之所有配線，與接腳3-8連接之配線係被配置於紙面X軸方向，且於紙面Y軸方向之封裝2上下側無須設置與接腳3-8連接之配線。另外，封裝2可相對於保護電路基板83於紙面Y軸方向上較短而於紙面X軸方向上較長來有效率地封裝。此外，對於使用圖4(A)說明之封裝52亦相同。
又，於本實施形態中，雖然說明從封裝2之側面2A、2B往外部引出接腳3-8之情況，但是並非限定於此種情況。例如，也可以為接腳3-8係形成為與封裝2側面為相同一面，且不往外部引出之非接腳型之封裝情況。
另外，雖然說明從封裝2之正反側露出導線架9之源極端子11、12，閘極端子13、14、VDD端子16及VM端子17之情況，但是並非限定於此情況。例如，藉由密封樹脂來覆蓋直到上述端子之背面側為止，且讓從封裝2之側面2A、2B引出之接腳3-8譬如加工成鷗翼(Gull-wing)形狀，封裝於保護電路基板之配線的情況亦適用。除此之外，只要不脫離本發明之宗旨之範圍內，亦可進行各種變更。
1‧‧‧半導體裝置
2‧‧‧封裝
3、4、5、6、7、8‧‧‧接腳
9‧‧‧導線架
10‧‧‧半導體晶片
11、12‧‧‧源極端子
13、14‧‧‧閘極端子
15‧‧‧IC晶片
16‧‧‧VDD端子
17‧‧‧VM端子
18、19、20、21、22‧‧‧金屬導線
2A、2B‧‧‧側面

Claims (7)

  1. 一種半導體裝置，其包含：一框架(frame)；一半導體晶片，其一主面被覆晶(flip-chip)封裝於該框架上；一IC晶片，堆疊且固定於與該半導體晶片之該主面相對之另一主面上；金屬導線，用來電性連接該半導體晶片及該IC晶片；及一封裝(package)，密封該框架、該半導體晶片、該IC晶片及該金屬導線，其中，該封裝具有於該長邊方向相對之二個側面，於該半導體晶片形成一第一電晶體及一第二電晶體，被形成於該主面一側之該第一電晶體的閘極電極係被配置於該封裝之其中一邊之該側面一側，而被形成於該主面一側之該第二電晶體的閘極電極係被配置於該封裝之另一邊之該側面一側。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一電晶體的閘極電極所覆晶封裝之該框架係於該長邊方向延伸，且從該封裝之其中一邊之該側面露出，而該第二電晶體的閘極電極所覆晶封裝之該框架係於該長邊方向延伸，且從該封裝之另一邊之該側面露出。
  3. 如申請專利範圍第1項或第2項所述之半導體裝置，其中與該第一電晶體的閘極電極電性連接之該金屬導線，係與該第一電晶體的閘極電極及該封裝之其中一邊之該側面之間的該框架連接；與該第二電晶體的閘極電極電性連接之該金屬導線，係與該第二電晶體的閘極電極及該封裝之另一邊之該側面之間的該框架連接。
  4. 如申請專利範圍第1項或第2項所述之半導體裝置，其中該半導體晶片具 有：形成於該主面一側之該第一電晶體的源極電極；形成於該主面一側之該第二電晶體的源極電極；以及形成於該另一主面一側之該第一電晶體及該第二電晶體的共用汲極電極，該第一電晶體的源極電極所覆晶封裝之該框架係從該封裝之其中一邊之該側面露出；該第二電晶體的源極電極所覆晶封裝之該框架係從該封裝之另一邊之該側面露出。
  5. 如申請專利範圍第3項所述之半導體裝置，其中該半導體晶片具有：形成於該主面一側之該第一電晶體的源極電極；形成於該主面一側之該第二電晶體的源極電極；以及形成於該另一主面一側之該第一電晶體及該第二電晶體的共用汲極電極，該第一電晶體的源極電極所覆晶封裝之該框架係從該封裝之其中一邊之該側面露出；該第二電晶體的源極電極所覆晶封裝之該框架係從該封裝之另一邊之該側面露出。
  6. 如申請專利範圍第1項所述之半導體裝置，其包含：與該第一電晶體的閘極電極並排而配置於該半導體晶片之該長邊方向上之該第一電晶體之源極電極；以及與該第二電晶體的該閘極電極並排而配置於該半導體晶片之該長邊方向上之該第二電晶體之源極電極，該第一電晶體的閘極電極與源極電極、以及該第二電晶體的閘極電極與源極電極係相對於該半導體晶片之一中心點配置為旋轉對稱的。
  7. 一種便攜式設備，於該便攜式設備之一二次電池的一保護電路基板上安裝有根據申請專利範圍第1項至第6項之任一項所述之半導體裝置之該封裝，其中， 該封裝之該長邊方向係沿著該保護電路基板之一長邊方向配置，該保護電路基板之一短邊方向係沿著該便攜式設備之一殼體之一厚度方向配置。
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