JP5405785B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5405785B2 JP5405785B2 JP2008240825A JP2008240825A JP5405785B2 JP 5405785 B2 JP5405785 B2 JP 5405785B2 JP 2008240825 A JP2008240825 A JP 2008240825A JP 2008240825 A JP2008240825 A JP 2008240825A JP 5405785 B2 JP5405785 B2 JP 5405785B2
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- Prior art keywords
- pad
- power supply
- semiconductor chip
- internal power
- semiconductor device
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Description
図1は、本発明の実施の形態1における半導体装置の機能ブロック図である。
金属線wireBの金属線長さよりも短い方がよい。
図13は、本発明の実施の形態2における半導体装置のリード端子VREG1と金属線wireA,BおよびCとの接続部の拡大図である。
図14は、本発明の実施の形態3における半導体装置の降圧スイッチ部SWのPMOSトランジスタPtr3および周辺部の断面の詳細を示す図である。
図16は、本発明の実施の形態4における半導体装置のパッドCと複数の内部回路circ2が接続されていることを示す図である。
図17は、本発明の実施の形態5における半導体装置のリード端子VREG1と金属線wireA,BおよびCとの接続部の拡大図である。
図18は、本発明の実施の形態6における半導体装置のレギュレータ回路および周辺部の詳細を示す図である。
図19は、本発明の実施の形態7における半導体装置のレギュレータ回路および周辺部の詳細を示す図である。
図20は、本発明の実施の形態8における半導体装置のレギュレータ回路および周辺部の詳細を示す図である。
図21は、本発明の実施の形態9における半導体装置のレギュレータ回路および周辺部の詳細を示す図である。
これらは、モニタパッドであるパッドBの接続について、2つに大別できる。
図22は、本発明の実施の形態10における半導体装置のパッケージ構造の平面図である。
てきた。これらの特徴は、全てを備える必要はなく、これらの中の1つの特徴を有するものであってもよく、複数を組み合わせたものであってもよい。
図29は、本発明の実施の形態11における半導体装置のパッケージ構造の平面図である。
図30は、本発明の実施の形態12における半導体装置のパッケージ構造の平面図である。
本発明の実施の形態13における半導体装置の実施の形態10との違いは、第1の半導体チップchip1が、2つのレギュレータ回路を有し、第2の半導体チップchip2に電圧値の異なる2種類の電源電圧を供給する構成となっていることである。
図34は、本発明の実施の形態14における半導体装置のパッケージ構造の平面図である。
図36は、本発明の実施の形態15における半導体装置のパッケージ構造の平面図である。
S、V、X、BP1、BP2 パッド
ball 半田ボール
Cap コンデンサ
chip1 第1の半導体チップ
chip2 第2の半導体チップ
circ1 内部回路
circ1−1 内部回路
circ1−2 内部回路
circ2 内部回路
circ2−1 内部回路
circ2−2 内部回路
circ2−3 内部回路
circ2−4 内部回路
circ3 内部回路
corner1 角
corner2 角
CS 定電流源
extVcc 外部電源電圧
film1、film2 接着フィルム
GND 接地電圧(グランド)
ifD ドレイン電極のコンタクト部
ifS ソース電極のコンタクト部
IN 入力部
inter インターポーザ基板
intVcc、intVcc2 内部電源電圧
Lac、Lbc、Lda、Lsv、t1、t2 距離
La、Lv 長さ
LD1、LD2 ランド
Lead、VREG0、VREG1 リード端子
VREG2、Vcc、Vss リード端子
VDD、VDD2 リード端子
LP ランドパッド
metal、metalA、metalB 金属配線
metalC、metalH、metalJ 金属配線
metalV、metalG、metalX 金属配線
mold 封止体
Ntr1、Ntr2 NMOSトランジスタ
PKG パッケージ
pointA、pointB、pointC 接点
PowArea 電源領域
Ptr1、Ptr2、Ptr3 PMOSトランジスタ
R1、R2 抵抗
Ref 比較部
Reg レギュレータ回路
Reg2 レギュレータ回路
Rvreg1、Rvdd 導体抵抗
RwireA、RwireB、RwireC 配線抵抗
S1、S2 領域
secP セカンドパッド
Sep 分圧部
SigArea 信号領域
sig1、sig2、sig3、sig4 信号端子
SW 降圧スイッチ部
tab タブ
Vback 入力電圧
via 貫通孔
Vmon モニタ電圧
Vref 参照電圧
wire、wireA、wireB 金属線
wireC、wireD、wireE 金属線
wireF、wireH、wireJ 金属線
wireHJ、wireV、wireG 金属線
wireSub 回路基板上の配線
1L1、2L1 第1長辺
1L2、2L2 第2長辺
1S1、2S1 第1短辺
1S2、2S2 第2短辺
Claims (22)
- 第1の辺を含む4辺を有し、主面にパッドが設けられた第1の半導体チップと、
第2の辺を含む4辺を有し、主面にパッドが設けられ、前記第1の半導体チップの主面上に前記第1の辺と前記第2の辺とが並び、かつ各主面が同一方向を向くように積層された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとを封止する封止体と、
前記パッドに接続され、端子の一部が前記封止体の外部に露出した複数の外部端子と、を有し、
前記第1の半導体チップは、
前記外部端子から外部電源電圧が供給される外部電源入力パッドと、
前記外部電源入力パッドに電気的に接続され、参照電圧とこの参照電圧と比較される入力電圧に応じて前記外部電源電圧を降圧した内部電源電圧を生成するレギュレータ回路と、
前記レギュレータ回路に電気的に接続され、前記内部電源電圧が出力される内部電源電圧出力パッドと、
前記入力電圧が入力される前記レギュレータ回路の入力部に電気的に接続されたモニタパッドと、を有し、
前記第2の半導体チップは、
前記内部電源電圧出力パッドから前記内部電源電圧が入力される内部電源入力パッドを有し、
前記内部電源電圧出力パッドと前記モニタパッドは、前記第1の半導体チップの前記第1の辺に沿って配置され、
前記内部電源入力パッドは、前記第2の半導体チップの前記第2の辺に沿って配置され、
前記モニタパッドは、前記内部電源電圧出力パッドと前記内部電源入力パッドとの接続経路間で電気的に接続、
もしくは、前記内部電源入力パッドを経由して前記内部電源電圧出力パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の半導体チップは、前記第1の辺とは異なる辺に沿って、前記第2の半導体チップとの間で信号を送受信する第1の信号パッドを有し、
前記第2の半導体チップは、前記第1の信号パッドが配置された辺と並ぶ辺に沿って、前記第1の信号パッドに電気的に接続された第2の信号パッドを有することを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記内部電源電圧出力パッドと前記内部電源入力パッドとは、第1金属線により接続され、
前記モニタパッドと前記内部電源入力パッドとは、第2金属線により接続され、
前記第1金属線の長さは、前記第2金属線の長さよりも短いことを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記第1の信号パッドと前記第2の信号パッドとは、第3金属線により接続され、
前記第3金属線の長さは、前記第1金属線の長さよりも短いことを特徴とする半導体装置。 - 第1の角を含む4つの角を有し、主面にパッドが設けられた第1の半導体チップと、
第2の角を含む4つの角を有し、主面にパッドが設けられ、前記第1の半導体チップの主面上に各主面が同一方向を向くように、かつ前記第1の角と前記第2の角が近づくように積層された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとを封止する封止体と、
前記パッドに接続され、端子の一部が前記封止体の外部に露出した複数の外部端子と、を有し、
前記第1の半導体チップは、
前記外部端子から外部電源電圧が供給される外部電源入力パッドと、
前記外部電源入力パッドに電気的に接続され、参照電圧とこの参照電圧と比較される入力電圧に応じて前記外部電源電圧を降圧した内部電源電圧を生成するレギュレータ回路と、
前記レギュレータ回路に電気的に接続された前記内部電源電圧が出力される内部電源電圧出力パッドと、
前記入力電圧が入力される前記レギュレータ回路の入力部に電気的に接続されたモニタパッドと、を有し、
前記第2の半導体チップは、
前記内部電源電圧出力パッドから前記内部電源電圧が入力される内部電源入力パッドを有し、
前記内部電源電圧出力パッドおよび前記モニタパッドは、前記4つの角の中で前記第1の角の近くになるように配置され、
前記内部電源入力パッドは、前記4つの角の中で前記第2の角の近くになるように配置され、
前記モニタパッドは、前記内部電源電圧出力パッドと前記内部電源入力パッドとの接続経路間で電気的に接続、
もしくは、前記内部電源入力パッドを経由して前記内部電源電圧出力パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記第1の半導体チップは、前記第1の角を構成する辺とは異なる辺に沿って、前記第2の半導体チップとの間で信号を送受信する第1の信号パッドを有し、
前記第2の半導体チップは、前記第1の信号パッドが配置された辺と並ぶ辺に沿って、前記第1の信号パッドに電気的に接続された第2の信号パッドを有することを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記内部電源電圧出力パッドと前記外部端子とは、第1金属線により接続され、
前記モニタパッドと前記外部端子とは、第2金属線により接続され、
前記第1金属線の長さは、前記第2金属線の長さよりも短いことを特徴とする半導体装置。 - 請求項7に記載の半導体装置において、
前記第1の信号パッドと前記第2の信号パッドとは、第3金属線により接続され、
前記第3金属線の長さは、前記第1金属線の長さよりも短いことを特徴とする半導体装置。 - 第1の辺と、
その第1の辺に対向する第2の辺と、
その第2の辺に交差する第3および第4の辺と、を有し、
主面に複数のパッドが設けられた第1の半導体チップと、
第5の辺と、
その第5の辺に対向する第6の辺と、を有し、
主面に複数のパッドが設けられ、前記第1の辺と前記第5の辺とで挟まれる第1領域、および前記第2の辺と前記第6の辺とで挟まれる第2領域に前記第1の半導体チップの前記複数のパッドが露出し、平面視において、前記第3の辺と前記第4の辺のそれぞれの一部を覆うように、かつ前記第1の半導体チップの前記主面上に各主面が同一方向を向くように積層された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとを封止する封止体と、
前記第1の半導体チップの前記複数のパッド、あるいは、前記第2の半導体チップの前記複数のパッドに接続され、端子の一部が前記封止体の外部に露出した複数の外部端子と、を有し、
前記第1の半導体チップは、
前記第1の半導体チップの前記複数のパッドの内、前記第1領域に配置され、前記外部端子から外部電源電圧が供給される外部電源入力パッドと、
前記第1領域に配置され、前記外部電源入力パッドに電気的に接続されて参照電圧とこの参照電圧と比較される入力電圧に応じて前記外部電源電圧を降圧した内部電源電圧を生成するレギュレータ回路と、
前記第1の半導体チップの前記複数のパッドの内、前記第1領域に配置され、前記レギュレータ回路に電気的に接続されて前記内部電源電圧が出力される内部電源電圧出力パッドと、
前記第1の半導体チップの前記複数のパッドの内、前記第1領域に配置され、前記入力電圧が入力される前記レギュレータ回路の入力部に電気的に接続されたモニタパッドと、を有し、
前記第2の半導体チップは、
前記第2の半導体チップの前記複数のパッドの内、前記内部電源電圧出力パッドから前記内部電源電圧が入力される内部電源入力パッドを有し、
前記内部電源入力パッドは、平面視において、前記第6の辺より前記第5の辺に近い位置に配置されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第1の半導体チップは、前記第1の辺と前記第3の辺とで形成される第1の角を含む4つの角を有し、
前記第2の半導体チップは、前記第5の辺とその第5の辺と交差する第7の辺とで形成され、前記第1の半導体チップの他の角よりも前記第1の角に近い第2の角を含む4つの角を有し、
前記内部電源電圧出力パッドおよび前記モニタパッドは、前記4つの角の中で前記第1の角に近くなるように配置され、
前記内部電源入力パッドは、前記4つの角の中で前記第2の角に近くなるように配置され、
前記モニタパッドは、前記内部電源電圧出力パッドと前記内部電源入力パッドとの接続経路間で電気的に接続、
もしくは、前記内部電源入力パッドを経由して前記内部電源電圧出力パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記内部電源電圧出力パッドと前記外部端子とが第1金属線により接続され、
前記モニタパッドと前記外部端子とが第2金属線により接続されていることで、前記モニタパッドは、前記内部電源電圧出力パッドと前記内部電源入力パッドとの接続経路間で電気的に接続されていることを特徴とする半導体装置。 - 請求項11に記載の半導体装置において、
前記第1金属線の長さは、前記第2金属線の長さよりも短いことを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記内部電源電圧出力パッドと前記内部電源入力パッドとが第1金属線により接続され、
前記モニタパッドと前記内部電源入力パッドとが第2金属線により接続されていることで、前記モニタパッドは、前記内部電源入力パッドを経由して前記内部電源電圧出力パッドと電気的に接続されていることを特徴とする半導体装置。 - 請求項13に記載の半導体装置において、
前記第1金属線の長さは、前記第2金属線の長さよりも短いことを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
平面視において、前記レギュレータ回路の前記第5の辺から露出している部分の面積は、前記第2の半導体チップが、前記レギュレータ回路を覆っている部分の面積よりも大きいことを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記レギュレータ回路は、前記外部電源電圧を降圧した前記内部電源電圧を生成する降圧スイッチ部を有し、
前記降圧スイッチ部は、前記第5の辺から露出していることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第2の半導体チップの前記複数のパッドのそれぞれは、前記第5の辺を除く他の辺に沿って配置されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第1領域における前記第1の辺から前記第5の辺までの距離は、前記第2領域における前記第2の辺から前記第6の辺までの距離よりも長いことを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第2の半導体チップのパッド数は、前記第1の半導体チップのパッド数よりも多いことを特徴とする半導体装置。 - 請求項19に記載の半導体装置において、
前記第1の半導体チップは、アナログ回路を有し、電源制御を行うアナログチップであり、
前記第2の半導体チップは、前記アナログチップを制御し、情報を処理するためのマイクロコンピュータチップであることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記第1の半導体チップは、前記第2領域に前記第2の半導体チップとの間で信号を送受信する第1の信号パッドを有し、
前記第2の半導体チップは、前記第6の辺に沿って、前記第1の信号パッドに電気的に接続された第2の信号パッドを有することを特徴とする半導体装置。 - 請求項21に記載の半導体装置において、
前記第1の信号パッドと前記第2の信号パッドとは、第3金属線により接続されていることを特徴とする半導体装置。
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CN201310353825.7A CN103400818B (zh) | 2008-09-19 | 2009-06-12 | 半导体器件 |
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US12/489,714 US8134228B2 (en) | 2008-09-19 | 2009-06-23 | Semiconductor device for battery power voltage control |
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US13/403,038 US9000574B2 (en) | 2008-09-19 | 2012-02-23 | Semiconductor device for battery power voltage control |
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JP2010073951A (ja) | 2010-04-02 |
US20150102501A1 (en) | 2015-04-16 |
TWI581393B (zh) | 2017-05-01 |
CN103400818A (zh) | 2013-11-20 |
US9209113B2 (en) | 2015-12-08 |
TW201603222A (zh) | 2016-01-16 |
CN103794591A (zh) | 2014-05-14 |
CN101677096B (zh) | 2013-09-11 |
US20120146245A1 (en) | 2012-06-14 |
HK1195667A1 (zh) | 2014-11-14 |
US20100072604A1 (en) | 2010-03-25 |
US8134228B2 (en) | 2012-03-13 |
US20160035706A1 (en) | 2016-02-04 |
TWI462260B (zh) | 2014-11-21 |
TW201013890A (en) | 2010-04-01 |
JP2014060417A (ja) | 2014-04-03 |
TW201511207A (zh) | 2015-03-16 |
TWI505426B (zh) | 2015-10-21 |
CN103794591B (zh) | 2016-08-10 |
CN101677096A (zh) | 2010-03-24 |
US9000574B2 (en) | 2015-04-07 |
CN103400818B (zh) | 2016-06-22 |
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