JP2008251901A - 複合半導体装置 - Google Patents
複合半導体装置 Download PDFInfo
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- JP2008251901A JP2008251901A JP2007092310A JP2007092310A JP2008251901A JP 2008251901 A JP2008251901 A JP 2008251901A JP 2007092310 A JP2007092310 A JP 2007092310A JP 2007092310 A JP2007092310 A JP 2007092310A JP 2008251901 A JP2008251901 A JP 2008251901A
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Abstract
【解決手段】GND電位となるp型半導体基板1の裏面2に薄型コンデンサ7の電極9を導電型DAF8(Die Attach Film)や導電性接着剤で接続し、p型半導体基板1の表面3の電極5、6と薄型インダクタ12の端子13、16をバンプ19、20で接続して積層することにより、ノイズの発生を抑制し製造コストを低減でき、また実装面積を小さくできる。
【選択図】 図1
Description
図9は、DC−DCコンバータの要部回路構成図である。電源IC50にインダクタLとこのインダクタLにコンデンサCの一方の電極が接続し、接続点がDC−DCコンバータの主直端子であるVDD端子と接続する。また電源IC50のGNDとコンデンサCの他方の電極が接続し、接続点がDC−DCコンバータのGND端子と接続する。このVDD端子とGND端子は負荷と接続する。多チャネルの電源IC50は、複数のインダクタLにそれぞれ接続する制御回路が集積されている。
電源IC50aに6個のチャネルが形成され、各チャネルに配線61で6個のインダクタLと接続し、これらのインダクタLと6個のコンデンサCがそれぞれ接続し、これらのインダクタLとコンデンサCとのそれぞれの接続点に各負荷51〜56が接続される。電源IC50a、インダクタL、コンデンサCおよび負荷51〜56であるICはPCB100上に固着している。
また、特許文献2では、半導体基板91と薄型インダクタ92の端子93の表面をバンプで接続し、薄型インダクタ92の端子93の裏面に薄型コンデンサ95の電極96を導電性接着剤で接続しているため、半導体基板91と薄型コンデンサ95の電気的接続は、バンプ94、薄型インダクタ92を貫通する端子93および薄型コンデンサ95の電極96を介したものになっている。薄型コンデンサ95の一方の電極にGNDを接続するのもこの経路によることになるが、コストやノイズに関する特性を向上させるためには、この接続をより直接的にとることが必要になる。
また、前記半導体基板の素子が形成される表側の表面に形成した電極と一方の端子がバンプで固着される薄型インダクタを有する。この薄型インダクタの他方の端子と、前記薄型コンデンサの他方の電極とをワイヤボンディングで接続した構成とする。
また、前記半導体基板の素子が形成される表側の表面に形成した電極と一方の端子がバンプで固着される薄型インダクタを有し、前記半導体基板の裏面に金属膜を形成し、該金属膜と前記電極を前記半導体基板を貫通する接続導体で接続する構成とする。
また、前記導電性DAFの代わりに導電性接着剤を用いてもよい。
また、前記導電性接着剤はAgペーストもしくははんだであるとよい。
また、前記半導体基板の裏面に金属膜を形成し、該金属膜を介して前記薄型コンデンサの一方の電極と前記半導体基板の裏面が固着されるとよい。
また、薄型コンデンサをp型半導体基板の裏面に導電性DAFで貼り付け固着することでワイヤボンディングによるGND電位をとることが不要となり、また薄型コンデンサの電極構造を簡易なものにでき製造コストを低減できる。
また、DC−DCコンデンサの構成要素である電源IC(制御回路)、薄型インダクタ、薄型コンデンサが最短距離で接続されているため、ノイズの発生を抑制し、DC−DCコンバータ本来の特性を発揮できる。
導電性DAF8で薄型コンデンサ7とp型半導体基板1を貼りあわせて固着して接続することで、特許文献1の場合と比べて製造プロセスが簡略化でき低コスト化できる。また、個別に形成した薄型コンデンサ7とp型半導体基板1(電源IC)をそれぞれ導電性DAF8を介して貼りあわせて接続するので、特許文献1の薄型コンデンサ7と電源ICを一緒に半導体プロセスで形成する場合と比べて、薄型コンデンサ7や電源ICの特性ばらつきを小さくすることができる。
また、前記の薄型インダクタ12から樹脂モールド22上面までの高さHを、携帯電話などに搭載する場合には1.2mm以下とする。
図1および図2の場合には、図3に示すように、薄型コンデンサ7から図示しないGND端子13と接続する裏面の電極5に向かって流れる電流iが大きいと、p型半導体基板1の縦方向の抵抗24により電圧降下を生じて裏面2のGND電位が不安定となる。それを防止する方法を次の実施例で説明する。
3をワイヤボンディング26で接続する。また、薄型コンデンサ12の電極9と
p型半導体基板1の裏面2との接続は導電性DAF8で行うことで、図1や図2と同様の効果が得られる。
これにより図1や図2のようにp型半導体基板1の裏面2を直接GNDに接続するので、薄型コンデンサ7からの電流iによる電圧降下の影響が少なくp型半導体基板1の裏面2のGND電位を安定化できる。
一方、図4の場合は、p型半導体基板1の裏面2に金属膜25を形成し、この金属膜25と薄型インダクタ1のGND端子13をワイヤボンディング26で接続することで、薄型コンデンサ7の電流iがp型半導体基板1を縦方向に通らなくなり、そのため電圧降下が小さくなり、p型半導体基板1の裏面2のGND電位を安定化できる。
尚、第1実施例〜第3実施例ではp型半導体基板1に薄型コンデンサ7と薄型インダクタ12を積層した場合について説明したが、薄型コンデンサ7のみp半導体基板1に積層し、インダクタを個別に外付けしても構わない。
板1の裏面2の全域に金属膜28を形成し、この金属膜28と薄型インダクタ12のGND端子13をワイヤボンディング26で接続する。この場合も裏面電極26と電極5をワイヤボンディング26の代わりに点線で示す接続導体29で結合してもよい。このように裏面2全面に金属膜28を形成すると、裏面2に生ずる自然酸化膜に対処できるとともに、薄型コンデンサ7を流れる電流iは金属膜26を流れてp型半導体基板1の内部に流れなくなるので、図4の場合より裏面2のGND電位は一層安定化できる。また、薄型コンデンサ12の電極9とp型半導体基板1の裏面2に形成した金属膜28との接続を導電性DAF8で行うことで、図1や図2と同様の効果が得られる。
尚、本実施例においても、裏面2からGND端子13に流れる電流が小さい場合は、ワイヤボンディング26や接続導体29をもうけなくてもよい。
また、図8、9は降圧型のコンバータを規定したものであるが、本発明の実施の形態はこれに限るものではなく、昇圧型や極性逆転型のDC−DCコンバータ、シリーズレギュレータ(この場合、インダクタは不要となる)であってもよい。特に極性逆転型のDC−DCの場合は、図5に示すインダクタ12の端子13と16を同じものにすることができる。
2、32 裏面
3、33 表側の表面(素子形成領域がある側)
4、34 素子形成領域
5、6、9、11 電極
7、35 薄型コンデンサ
8 導電性DAF
10 誘電体
12 薄型インダクタ
12a フェライト
13、14 GND端子
15、18、29 接続導体
16、17、27 端子
19、20 バンプ
21、26 ワイヤボンディング
22 樹脂モールド
23 導電性接着剤
24 抵抗
25、28 金属膜
31 半導体基板
Claims (8)
- 薄型コンデンサと、該薄型コンデンサの一方の電極とGND電位となる裏面が導電性DAF(Die Attach Film)を介して固着される半導体基板とを有することを特徴とする複合半導体装置。
- 前記半導体基板の素子が形成される表側の表面に形成した電極と一方の端子がバンプで固着される薄型インダクタを有し、該薄型インダクタの他方の端子と、前記薄型コンデンサの他方の電極とをワイヤボンディングで接続したことを特徴とする請求項1に記載の複合半導体装置。
- 前記半導体基板の素子が形成される表側の表面に形成した電極と一方の端子がバンプで固着される薄型インダクタを有し、前記半導体基板の裏面に金属膜を形成し、該金属膜と前記インダクタに形成したGND端子をワイヤボンディングで接続したことを特徴とする請求項1に記載の複合半導体装置。
- 前記半導体基板の素子が形成される表側の表面に形成した電極と一方の端子がバンプで固着される薄型インダクタを有し、前記半導体基板の裏面に金属膜を形成し、該金属膜と前記電極とを前記半導体基板を貫通する接続導体で接続したことを特徴とする請求項1に記載の複合半導体装置。
- 前記半導体基板の導電型がp型であることを特徴とする請求項1〜4のいずれか一項に記載の複合半導体装置。
- 前記導電性DAFの代わりに導電性接着剤を用いることを特徴とする請求項1に記載の複合半導体装置。
- 前記導電性接着剤がAgペーストもしくははんだであることを特徴とする請求項6に記載の複合半導体装置。
- 前記半導体基板の裏面に金属膜を形成し、該金属膜を介して前記薄型コンデンサの一方の電極と前記半導体基板の裏面が固着されることを特徴とする請求項1、2、3、4、6、7のいすれか一項に記載の複合半導体装置。
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JP2011119582A (ja) * | 2009-12-07 | 2011-06-16 | Shindengen Electric Mfg Co Ltd | 基板の積層固定構造、及び、基板の積層固定方法 |
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US9263177B1 (en) * | 2012-03-19 | 2016-02-16 | Volterra Semiconductor LLC | Pin inductors and associated systems and methods |
US9281739B2 (en) | 2012-08-29 | 2016-03-08 | Volterra Semiconductor LLC | Bridge magnetic devices and associated systems and methods |
US9083332B2 (en) | 2012-12-05 | 2015-07-14 | Volterra Semiconductor Corporation | Integrated circuits including magnetic devices |
US10217810B2 (en) | 2015-12-07 | 2019-02-26 | Microchip Technology Incorporated | Capacitor formed on heavily doped substrate |
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