TW201603222A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201603222A
TW201603222A TW104130159A TW104130159A TW201603222A TW 201603222 A TW201603222 A TW 201603222A TW 104130159 A TW104130159 A TW 104130159A TW 104130159 A TW104130159 A TW 104130159A TW 201603222 A TW201603222 A TW 201603222A
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Taiwan
Prior art keywords
semiconductor wafer
pad
power supply
connection point
semiconductor device
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TW104130159A
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English (en)
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TWI581393B (zh
Inventor
Mikihiko Komatsu
Takao Hidaka
Junko Kimura
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Renesas Electronics Corp
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Publication of TW201603222A publication Critical patent/TW201603222A/zh
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Publication of TWI581393B publication Critical patent/TWI581393B/zh

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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract

本發明係提供關於複數半導體晶片層積於同一封裝之半導體裝置中，將複數半導體晶片之中任一個所產生的電壓作為電源電壓供給其他的半導體晶片並可使其穩定動作之技術。 本發明之主要一例，係將2個晶片層積，將焊墊A、B及C分別配置於各自晶片並排的邊，將該等焊墊分別以金屬線wireA、B及C共同地連接。另一例，係沿著與配置有焊墊A、B及C的邊不同的邊配置焊墊H及焊墊J，並進一歩通過金屬線wireHJ將晶片間接合連接。

Description

半導體裝置
本發明係關於將複數半導體晶片層積於同一封裝之半導體裝置，係關於將由複數半導體晶片之中任一個所產生的電壓作為電源電壓供給其他的半導體晶片之技術。
兩個半導體晶片之間的關係，一般已知的有如下。
一個半導體晶片，包含：調節器電路，其係被供給外部電源電壓，並輸出將外部電源電壓降壓後的內部電源電壓(第1半導體晶片)。
另一方的半導體晶片則被供給該內部電源電壓作為動作電源電壓(第2半導體晶片)。
此時，第1半導體晶片係以高的電源電壓進行動作，例如可以4~25V來進行動作。第2半導體晶片係以比第1半導體晶片低的電源電壓動作，例如可以1.4-3.6V來進行動作。
即，以半導體產品目錄所示之最大電壓值比較時，第1半導體晶片係最大電壓值比第2半導體晶片高的半導體晶片。
過去，第1與第2半導體晶片係收容於不同的封裝，經由連接於半導體晶片之外部端子，向兩個半導體晶片供給電源電壓。
但是，於電路基板上並排搭載兩個封裝時，則存在需要很大構裝面積的問題。
為使構裝面積變小，已知有如下的先前技術。
於日本公開特許公報特開2005-183611號公報(專利文獻1)中，記載有關於多晶片型半導體裝置之技術，其係將設於外部之調節器電路內建於晶片，於1個封裝中將2個晶片排列裝載(平放)。
可將2個晶片並排收容於一個封裝，與將2個封裝並排構裝相比，可減少構裝面積，即可使封裝尺寸變小。
該文獻雖記載了在1個封裝內平放2個晶片之技術，但是並沒有充分的記載通過1個封裝化而使調節器電路更加穩定地動作之技術。
另外，作為構裝方法，使封裝尺寸更小的技術一般被認為是晶片層積技術。
但是，在本次的先前技術調查中，並未發現著重於層積時使調節器電路穩定地動作之技術文獻。
另一方面，在本次的先前技術調查中，找到了記載關於使調節器電路之動作穩定化之電路及半導體裝置之技術之專利第3732884號(專利文獻2)。
但是，該文獻係記載關於在1晶片內之調節器電路之穩定化技術。並未記載在有複數晶片及層積該等晶片之構造中，使調節器電路穩定地動作之技術。
[專利文獻1]日本公開特許公報特開2005-183611號公報
[專利文獻2]專利第3732884號
本發明之目的在於提供一種在複數的半導體晶片層積於同一封裝之半導體裝置中，可將複數的半導體晶片之中任一個所產生的電壓提供作為其他的半導體晶片之電源電壓，且可穩定動作之技術。
於本案所公開的技術中，其中一實施例如下。即，關於本發明 之半導體裝置，包含：第1半導體晶片，其具有包含第1邊的4個邊，並在主面設有焊墊；第2半導體晶片，其具有包含第2邊的4個邊，於主面設有焊墊，上述第1邊與上述第2邊並排層積於上述第1半導體晶片之主面上，且各主面朝向同一方向；封裝體，其係將上述第1半導體晶片及上述第2半導體晶片進行封裝；及複數個外部端子，其係連接於上述焊墊，且端子的一部分露出在上述封裝體之外部。上述第1半導體晶片包含：外部電源輸入焊墊，其係由上述外部端子供給外部電源電壓；調節器電路，其係電性連接於上述外部電源輸入焊墊，按照參考電壓及與該參考電壓比較之輸入電壓以產生將上述外部電源電壓降壓後之內部電源電壓；內部電源電壓輸出焊墊，其係電性連接於上述調節器電路，輸出上述內部電源電壓；及監測器焊墊，其係電性連接於輸入有上述輸入電壓之上述調節器電路之輸入部。上述第2半導體晶片包含：內部電源輸入焊墊，其係由上述內部電源電壓輸出焊墊輸入上述內部電源電壓；上述內部電源電壓輸出焊墊及上述監測器焊墊，係沿著上述第1半導體晶片之上述第1邊配置，上述內部電源輸入焊墊，係沿著上述第2半導體晶片之上述第2邊配置，上述監測器焊墊與上述內部電源電壓輸出焊墊和上述內部電源輸入焊墊之連接路徑間電性連接，或經由上述內部電源輸入焊墊與上述內部電源電壓輸出焊墊電性連接。再者，上述第1半導體晶片具有：第1信號焊墊，其係沿著與上述第1邊不同的邊，於與上述第2半導體晶片之間收發信號；上述第2半導體晶片具有：第2信號焊墊，其係沿著與配置上述第1信號焊墊的邊並排的邊，並與上述第1信號焊墊電性連接。
在本案所公開的發明中，對於解決上述課題之手段所示之一實施例可得到之效果簡單說明如下。
即，藉由將上述晶片作成層積構造，可減少因第1信號焊墊與第 2信號焊墊之間所進行之信號收發所產生的雜訊對內部電源電壓之影響。
1L1、2L1‧‧‧第1長邊
1L2、2L2‧‧‧第2長邊
1S1、2S1‧‧‧第1短邊
1S2、2S2‧‧‧第2短邊
A、B、C、D、E、F、G、H、J‧‧‧焊墊
Ball‧‧‧銲錫球
Cap‧‧‧電容器
chip1‧‧‧第1半導體晶片
chip2‧‧‧第2半導體晶片
circ1‧‧‧內部電路
circ1-1‧‧‧內部電路
circ1-2‧‧‧內部電路
circ2‧‧‧內部電路
circ2-1‧‧‧內部電路
circ2-2‧‧‧內部電路
circ2-3‧‧‧內部電路
circ2-4‧‧‧內部電路
circ3‧‧‧內部電路
corner1‧‧‧角
corner2‧‧‧角
CS‧‧‧定電流源
extVcc‧‧‧外部電源電壓
film1、film2‧‧‧接著膜
GND‧‧‧接地電壓(接地極)
ifD‧‧‧汲極電極的接觸部
ifS‧‧‧源極電極的接觸部
IN‧‧‧輸入部
Inter‧‧‧內插器基板
intVcc、intVcc2‧‧‧內部電源電壓
La、Lv‧‧‧長度
Lac、Lbc、Lda、Lsv、t1、t2‧‧‧距離
LD1、LD2‧‧‧觸點
Lead、VREG0、VREG1‧‧‧引線端子
LP‧‧‧觸點焊墊
metal、metalA、metalB‧‧‧金屬配線
metalC、metalH、metalJ‧‧‧金屬配線
metalV、metalG、metalX‧‧‧金屬配線
mold‧‧‧封裝體
Ntr1、Ntr2‧‧‧NMOS電晶體
PKG‧‧‧封裝
pointA、pointB、pointC‧‧‧連接點
PowArea‧‧‧電源區域
Ptr1、Ptr2、Ptr3‧‧‧PMOS電晶體
R1、R2‧‧‧電阻
Ref‧‧‧比較部
Reg‧‧‧調節器電路
Reg2‧‧‧調節器電路
Rvreg1、Rvdd‧‧‧導體電阻
RwireA、RwireB、RwireC‧‧‧配線電阻
S、V、X、BP1、BP2‧‧‧焊墊
S1、S2‧‧‧區域
secP‧‧‧第二焊墊
Sep‧‧‧分壓部
sig1、sig2、sig3、sig4‧‧‧信號端子
SigArea‧‧‧信號區域
SW‧‧‧降壓開關部
Tab‧‧‧晶座
Vback‧‧‧輸入電壓
VDD、VDD2‧‧‧引線端子
Via‧‧‧貫孔
Vmon‧‧‧監測電壓
Vref‧‧‧參考電壓
VREG2、Vcc、Vss‧‧‧引線端子
wire、wireA、wireB‧‧‧金屬線
wireC、wireD、wireE‧‧‧金屬線
wireF、wireH、wireJ‧‧‧金屬線
wireHJ、wireV、wireG‧‧‧金屬線
wireSub‧‧‧電路基板上的配線
圖1係本發明實施方式1之半導體裝置之功能框圖；圖2係本發明實施方式1之半導體裝置的封裝構造之平面圖；圖3係本發明實施方式1之半導體裝置的封裝構造之剖面圖。(a)係圖2之A-A'剖面圖。(b)係圖2之B-B'剖面圖；圖4係表示本發明實施方式1之半導體裝置的調節器電路及周邊部之詳細情形圖；圖5係表示本發明實施方式1之半導體裝置的比較部之等價電路之詳細情形圖；圖6係表示本發明實施方式1之半導體裝置之帶隙電路之一例；圖7係對圖2所示本發明實施方式1之半導體裝置的封裝構造之平面圖的比較例之詳細情形圖；圖8係表示圖2及圖7之等價電路之詳細情形圖。(a)係表示圖7之等價電路之詳細情形圖。(b)係表示圖2之等價電路之詳細情形圖；圖9係表示信號區域與電源區域並排於同一邊時之詳細情形圖；圖10係表示相對於配置有電源區域的邊，將信號區域配置於不同的邊的例之詳細情形。(a)係表示將信號區域配置於與配置有電源區域的邊交叉的邊的例子之詳細情形。(b)係表示將信號區域配置於與配置有電源區域的邊相對的邊的例子之詳細情形圖；圖11係表示相對於配置有電源區域的邊，將信號區域配置於不同的邊且與圖10不同例之詳細情形；圖12係表示調節器電路、第1-1內部電路及第1-2內部電路，分別連接於金屬配線之詳細情形。(a)係表示調節器電路、第1-1內部電路及第1-2內部電路，共同地連接於焊墊之圖。(b)係表示將連接調節器 電路之焊墊，與連接第1-1內部電路及第1-2內部電路之焊墊分開設置的圖；圖13係表示本發明實施方式2之半導體裝置之引線端子與第1金屬線、第2金屬線及第3金屬線之連接部之放大圖。(a)係表示第3金屬線與引線端子之第3連接點，比第2金屬線之第2連接點更靠近第1金屬線之第1連接點的位置之狀態圖。(b)係表示第3金屬線與引線端子之第3連接點，在於第1連接點與第2連接點之間的位置之狀態；圖14係表示在於本發明實施方式3之半導體裝置之降壓開關部的PMOS電晶體及周邊部之剖面之詳細情形圖；圖15係表示在於本發明實施方式3之半導體裝置之降壓開關部的PMOS電晶體及周邊部之佈局之詳細情形圖；圖16係表示本發明實施方式4之半導體裝置之焊墊與複數第2內部電路的連接圖。(a)係表示第2-1內部電路與第2-2內部電路連接於焊墊，且在焊墊與第2-2內部電路之間連接有焊墊X的圖。(b)係表示第2-1內部電路、第2-2內部電路、第2-3內部電路及第2-4內部電路共同地連接於焊墊的圖；圖17係本發明實施方式5之半導體裝置之引線端子與第1金屬線、第2金屬線及第3金屬線之連接部之放大圖。(a)係表示第1焊墊及第3焊墊，分別以複數第1金屬線及第3金屬線與引線端子連接之狀態圖。(b)係表示複數第1焊墊及第3焊墊分別以複數第1金屬線及第3金屬線與引線端子連接之狀態圖；圖18係表示本發明實施方式6之半導體裝置的調節器電路及周邊部之詳細情形圖；圖19係表示本發明實施方式7之半導體裝置的調節器電路及周邊部之詳細情形圖；圖20係表示本發明實施方式8之半導體裝置的調節器電路及周邊 部之詳細情形圖；圖21係表示本發明實施方式9之半導體裝置的調節器電路及周邊部之詳細情形圖；圖22係本發明實施方式10之半導體裝置的封裝構造之平面圖；圖23係本發明實施方式10之半導體裝置的封裝構造之剖面圖。(a)係圖22的A-A'剖面圖。(b)係圖22的B-B'剖面圖；圖24係表示圖22之平面圖的比較例之詳細情形圖；圖25係焊墊配置於第2半導體晶片之第1長邊時，第1焊墊、第2焊墊之周邊部分之放大圖；圖26係表示並非將調節器電路配置於第2半導體晶片之下，而配置在不與第2半導體晶片重疊之區域時的圖；圖27係在調節器電路上重疊第2半導體晶片時，重疊在降壓開關部以外的區域做層積時的圖；圖28係表示一般的輸出入電路之一例之詳細情形圖；圖29係表示本發明實施方式11之半導體裝置之封裝構造之平面圖；圖30係表示本發明實施方式12之半導體裝置之封裝構造之平面圖；圖31係表示本發明實施方式13之半導體裝置之封裝構造之平面圖；圖32係表示本發明實施方式13之半導體裝置之調節器電路及周邊部之詳細情形圖；圖33係表示AFE與MCU之電池電壓控制系統之詳細情形之電路框圖；圖34係表示本發明實施方式14之半導體裝置之封裝構造之平面圖； 圖35係表示本發明實施方式14之半導體裝置之封裝構造之剖面圖。(a)係圖34之A-A'剖面圖。(b)係圖34之B-B'剖面圖；圖36係表示本發明實施方式15之半導體裝置之封裝構造之平面圖；及圖37係表示本發明實施方式15之半導體裝置之封裝構造之剖面圖。(a)係圖36之A-A'剖面圖。(b)係圖36之B-B'剖面圖。
以下根據附圖詳細說明本發明之實施方式。為了說明實施方式之所有圖中，原則上對具有同一功能之構件採用同一符號，省略掉重複的說明。另外，在除了需要特別說明的以外，對具有同一或同樣的部分原則上不進行重複說明。
(實施方式1)
圖1係本發明實施方式1之半導體裝置之功能框圖。
如圖1所示，於第1半導體晶片chip1之上，層積第2半導體晶片chip2，上述2個晶片收容於1個封裝PKG內。
例如，第1半導體晶片chip1具有類比電路，係進行電源控制等之類比晶片，第2半導體晶片chip2係控制上述類比晶片，並進行資訊處理之微電腦晶片。
第1半導體晶片chip1具有1個或多個輸出將外部電源電壓extVcc降壓後之內部電源電壓intVcc之調節器電路Reg。
而且，第1半導體晶片chip1經由信號端子sig1與封裝PKG外部進行信號的收發，具有1個或多個處理資訊之內部電路circ1。
調節器電路Reg及內部電路circ1電性連接於供給外部電源電壓extVcc之端子。
第2半導體晶片chip2經由信號端子sig2與封裝PKG外部進行信號的收發，並具有1個或多個處理資訊之內部電路circ2。
內部電路circ2電性連接於調節器電路Reg。
內部電路circ1具有與內部電路circ2進行信號收發之信號端子sig3。
內部電路circ2具有與內部電路circ1進行信號收發之信號端子sig4。
信號端子sig3與信號端子sig4經由金屬線wire電性連接。
此時，第1半導體晶片以高的電源電壓動作，例如可以以4~25V進行動作。第2半導體晶片係以比第1半導體晶片低的電源電壓進行動作，例如可以以1.4~3.6V進行動作。
即，以半導體產品目錄所示之最大電壓值比較時，第1半導體晶片係比第2半導體晶片的最大電壓值高的半導體晶片。
調節器電路Reg、內部電路circ1及內部電路circ2，與提供接地電壓GND之端子電性連接。
圖2係本發明實施方式1之半導體裝置的封裝構造之平面圖。
圖3係本發明實施方式1之半導體裝置的封裝構造之剖面圖。
圖3(a)係圖2之A-A'剖面圖。圖3(b)係圖2之B-B'剖面圖。
如圖2及圖3所示，實施方式1之半導體裝置之封裝在本實施方式中使用QFP(Quad Flat Package：方型扁平式封裝)。
如圖2及圖3所示，封裝內有用於裝載半導體晶片之晶座tab。晶座tab係以圖中未示出的吊帶導線保持於4個角落。晶座tab上裝載有第1半導體晶片chip1。
第1半導體晶片chip1及後述的第2半導體晶片chip2係以使用半導體晶圓製程技術形成有電晶體等的電路層的面為主面。另外，以與上述主面相對的面，即相反的面為背面。
如圖3所示，第1半導體晶片chip1的背面通過與例如晶座tab的表面和以熱硬化性環氧系接著膜film1等固定。晶座tab係由構成QFP之 材料之一，在以金屬性(導電性)材料所組成之導線架的製造階段中，與吊帶導線、引線端子Lead等一起一體地成形。換言之，晶座tab係用於裝載半導體晶片之導線架的一部分。
在第1半導體晶片chip1之主面上，第2半導體晶片chip2之主面與第1半導體晶片chip1之主面朝相同的方向層積。
第1半導體晶片chip1之主面及第2半導體晶片chip2之背面亦以接著膜film2等固定。
例如第1半導體晶片chip1及第2半導體晶片chip2之晶片厚度分別是150μm左右。另外，接著膜film1及接著膜film2之接著厚度分別是25μm左右。
如圖2所示，第1半導體晶片chip1及第2半導體晶片chip2為四角形，而在本實施方式中為長方形。
再者，第2半導體晶片chip2之外形比第1半導體晶片chip1之外形小。因此，第2半導體晶片chip2的4個邊被第1半導體晶片chip1的4個邊圍繞。
另外，第2半導體晶片chip2的各邊與第1半導體晶片chip1的各邊並列地層積。
如圖2所示、第1半導體晶片chip1之主面上，內建之調節器電路Reg及內部電路circ1連接之複數個焊墊BP1沿著晶片的各邊配置。也可以說是該等複數個焊墊BP1被配置成夾在第1半導體晶片chip1的各邊與第2半導體晶片chip2的各邊之間。
另外，同樣地，第2半導體晶片chip2之主面上的連接內部電路circ2之複數個焊墊BP2沿著晶片各邊被配置。
另外，如圖2所示，第1半導體晶片chip1之複數個焊墊BP1及第2半導體晶片chip2之複數個焊墊BP2的數量，圖示中的數字只是為了方便說明而舉出的適當數，實際數量可比圖示的數多或少。
如圖2及圖3所示，複數個焊墊BP1及BP2，係由金屬線wire連接至各自對應之複數個引線(外部)端子Lead。上述金屬線wire如為金線、鋁(Al)線及銅(Cu)線等。上述金屬線wire係以併用了超音波及熱之打線接合法等來連結。
收容於封裝PKG之第1半導體晶片chip1及第2半導體晶片chip2經由以金屬線wire連接之引線端子Lead，由封裝外部賦予電源電壓、接地電壓，並且進行信號類的收發(相當於圖1所示之信號端子sig1、sig2)。
如圖2及圖3所示，第1半導體晶片chip1及第2半導體chip2係以熱硬化性環氧系樹脂等材料所構成，被傳遞模法等形成之封裝體mold覆蓋。封裝體mold的厚度，如為1.4mm左右。
封裝體mold，具有保護半導體晶片受到來自外部的電性衝擊及機械性衝擊作用。
引線端子Lead的一部分，從封裝體mold的4個邊露出。
此外，圖2所示之封裝之引線端子Lead的數量，圖示中的數字只是為了方便說明而舉出的適當數，實際數量可比圖示的數多或少。
藉此，將2個半導體晶片進行層積，並收容於1個封裝內，比起先前的將2個封裝排列構裝於電路基板上的方法相比，可減小構裝面積。
圖4係表示本發明實施方式1之半導體裝置的調節器電路Reg及周邊部之詳細情形圖。
如圖4所示，調節器電路Reg係由比較部Ref、降壓開關部SW及分壓部Sep所構成。
圖5係表示本發明實施方式1之半導體裝置的比較部Ref之等價電路之詳細情形圖。
如圖5所示，在本實施方式中，比較部Ref係由PMOS電晶體Ptr1, Ptr2、NMOS電晶體Ntr1,Ntr2及定電流源CS所構成之電流鏡型放大電路。
如圖4及圖5所示，降壓開關部SW係由PMOS電晶體Ptr3構成。
如圖4及圖5所示，分壓部Sep係由電阻R1及電阻R2構成。另外，電阻R1及電阻R2係於半導體晶片中使用多晶矽等所形成之電阻。
如圖4及圖5所示，構成調節器電路Reg之電晶體及電阻等分別用金屬配線metal連接。金屬配線metal係使用半導體晶圓製程技術等，以鋁(Al)、銅(Cu)等形成之配線。
如圖4所示，配置於第1半導體晶片chip1之主面之焊墊V，通過金屬配線metalV連接於內部電路circ1及調節器電路Reg，並輸入外部電源電壓extVcc之外部電源輸入焊墊。
焊墊V通過金屬線wireV與輸入外部電源電壓extVcc之引線端子Vcc連接。
如圖4所示，配置於第1半導體晶片chip1之主面之焊墊A，通過金屬配線metalA與調節器電路Reg之降壓開關部SW之汲極電極連接，為輸出內部電源電壓intVcc之內部電源輸出焊墊。
如圖4所示，配置於第1半導體晶片chip1之主面之焊墊B，通過金屬配線metalB與調節器電路Reg之分壓部Sep連接，係用於輸入在調節器電路Reg內用於與後述的參考電壓Vref比較之輸入電壓Vback的監測焊墊。
分壓部Sep通過金屬配線metal與具有用於輸入2個比較用電壓之比較部Ref的輸入部IN連接。
如圖4所示，配置於第2半導體晶片chip2之主面之焊墊C，通過金屬配線metalC與內部電路circ2連接，為輸入內部電源電壓intVcc之內部電源輸入焊墊。
焊墊A、B及C，分別通過金屬線wireA、B及C與輸出內部電源電 壓intVcc之引線端子VREG1連接。
如圖4所示，於引線端子VREG1與接地極GND之間，連接有補償內部電源電壓intVcc之相位補償及穩定電壓之調節器容量的電容器Cap。調節器容量之電容器，一般多為設有μF等級的大容量。因此，使用電解電容為佳。電容器Cap係於封裝PKG之外側，即與封裝PKG一起構裝於電路基板上。
如圖4所示，配置於第1半導體晶片chip1之主面之1個或複數個焊墊H，係通過金屬配線metalH與內部電路circ1連接，並與內部電路circ2進行信號收發之焊墊。另外，焊墊H相當於圖1之信號端子sig3。
如圖4所示，配置於第2半導體晶片chip2之主面之1個或複數個焊墊J，係通過金屬配線metalJ與內部電路circ2連接，並與內部電路circ1進行信號收發之焊墊。此外，焊墊J相當於圖1的信號端子sig4。
焊墊H與焊墊J通過金屬線wireHJ連接。
如圖4所示，配置於第1半導體晶片chip1及第2半導體晶片chip2之主面之1個或複數個焊墊G，通過金屬配線metalG與調節器電路Reg、內部電路circ1及內部電路circ2連接，並供給有接地電壓GND之接地極焊墊。
複數個焊墊G，通過金屬線wireG與供給有接地電壓GND之1個或複數個引線端子Vss連接。
下面說明圖4所示電路之動作。
調節器電路Reg係產生將外部電源電壓extVcc降壓之內部電源電壓intVcc之電路。
內部電源電壓intVcc由焊墊A輸出，並經由引線端子VREG1從第2半導體晶片chip2之焊墊C輸入。
由焊墊C輸入之內部電源電壓intVcc，進入第2半導體晶片chip2之內部電路circ2。藉此，內部電路circ2，即第2半導體晶片chip2為可 以動作之狀態。
調節器電路Reg之比較部Ref中，輸入對於周圍的溫度變化而電壓值變化小之帶隙電路所產生之參考電壓Vref。
圖6係表示本發明實施方式1之半導體裝置之帶隙電路之一例。
一般在通常的電路中，電壓之電壓偏差值相對於目標電壓值為±3%左右。通過使用帶隙電路產生電壓，可在對溫度變動為0~60℃的範圍內將電壓偏差值抑制在目標電壓值的±0.5%左右。
如圖4所示，由引線端子VREG1反饋之內部電源電壓intVcc，即由焊墊B輸入而進入分壓部Sep之輸入電壓Vback，通過電阻R1及電阻R2被分壓成與參考電壓Vref的電壓值相等的監測電壓Vmon。
調節器電路Reg的比較部Ref係藉由調整供給PMOS電晶體Ptr3之閘極之電壓，調整內部電源電壓intVcc的大小，以使得輸入至輸入部IN之參考電壓Vref與監測電壓Vmon相等。
以上說明了關於在層積有2個半導體晶片收容於同一封裝之半導體裝置中，由一邊的晶片向另一邊的晶片供給電源電壓，於2個半導體晶片之間進行信號的收發之構造。在其多數特徵中以例子來說明的話，例子如下。然而，並非限定於以下各例。
其中1個例為關於第1半導體晶片chip1之內部電源輸出焊墊(焊墊A)、監測器焊墊(焊墊B)及層積的第2半導體晶片chip2之內部電源輸入焊墊(焊墊C)之配置關係。
另一例為關於收發第1半導體晶片chip1與第2半導體晶片chip2之信號的焊墊之連接方法及其配置。
關於這些特徵，以下使用比較例進行詳細說明。
圖7係與圖2所示本發明實施方式1之半導體裝置之封裝構造的平面圖之比較例的詳細情形圖。
如圖7所示，焊墊A及焊墊B，係於第1半導體晶片chip1之主面 上，沿著4個邊之中的1邊配置，在本實施方式中為沿著一邊的長邊配置。
其次，焊墊C係於第2半導體晶片chip2之主面上，沿著與配置有焊墊A及焊墊B的邊相反的第2半導體晶片chip2之長邊而配置。
焊墊A及B係通過金屬線wireA及金屬線wireB分別與複數引線端子Lead之中的引線端子VREG1共同連接。
另外，引線端子VREG1與引線端子VDD通過藉由將銅(Cu)等進行蝕刻所形成之電路基板上的配線wireSub被連接，並且引線端子VDD通過金屬線wireC與焊墊C連接。
對此，圖2所示之本發明實施方式1之半導體裝置之焊墊C，係於第2半導體晶片chip2之主面上，沿著與配置有焊墊A及焊墊B的邊並排的第2半導體晶片chip2的邊配置。
另外，焊墊A、B及C分別通過金屬線wireA、B及C共通地與引線端子VREG1連接。
亦可說是焊墊A、B及C經由引線端子VREG1分別通過金屬線wireA、B及C電性連接。
如上上述，通過層積晶片使2個晶片之各邊並排，將焊墊A、B及C分別沿著2個晶片所排列的邊配置，並通過金屬線wire將該等焊墊共通地連接於引線端子VREG1，與以電路基板上的配線wireSub連接相比，可使配線長度變短。通過縮短配線長度，可使配線電阻變小，故可減少內部電源電壓intVcc之電壓降。
另外，於圖2中，由於不需要圖7所示之引線端子VDD，故亦可減少封裝PKG之接腳數。
圖8係表示圖2及圖7之等價電路之詳細情形圖。
圖8(a)係表示圖7之等價電路之詳細情形圖。圖8(b)係表示圖2之等價電路之詳細情形圖。
如圖8(a)所示，連接焊墊A與引線端子VREG1之金屬線wireA中具有配線電阻RwireA。連接焊墊B與引線端子VREG1之金屬線wireB中具有配線電阻RwireB。引線端子VREG1中具有導體電阻Rvreg1。於連接引線端子VRGE1與引線端子VDD之電路基板上的配線wireSub中具有配線電阻RwireSub。引線端子VDD中具有導體電阻Rvdd。連接焊墊C與引線端子VDD之金屬線wireC中具有配線電阻RwireC。
即，圖7所示比較例之焊墊A與焊墊C之間的合計電阻R可用R=RwireA+Rvreg1+RwireSub+Rvdd+RwireC表示。
對此，如圖8(b)所示，圖2之本發明實施方式1之半導體裝置之焊墊A與焊墊C之間的合計電阻R可用R=RwireA+Rvreg1+RwireC表示。
圖2之本發明實施方式1之半導體裝置之焊墊A係經由引線端子VREG1與焊墊C連接。因此，圖2之本發明實施方式1之半導體裝置中，由於沒有電路基板上的配線wireSub與引線端子VDD之連接，故配線長度可比圖7之比較例短。即，圖2之本發明實施方式1之半導體裝置中，可使電阻比圖7之比較例，減小電路基板上之配線wireSub之配線電阻RwireSub及引線端子VDD之導體電阻Rvdd之部分。通過減小電阻，可減少內部電源電壓intVcc之電壓降。
另外，流過的電流比金屬線wireB多的金屬線wireA之金屬線長度最好比金屬線wireB的金屬線的長度短。
藉此，可使金屬線wireA的配線電阻RwireA變小，從而可減少內部電源電壓intVcc之電壓降。
下面說明其特徵。
如圖7之比較例所示，第1半導體晶片chip1之主面中，沿著配置有焊墊A、B的邊配置有1個或複數個焊墊H。
如圖4所示，焊墊H係藉由金屬配線metalH與第1半導體晶片chip1之內部電路circ1連接。
接著，如圖7之比較例所示，第2半導體晶片chip2之主面中，沿著與配置有焊墊C的邊相反(相對)的邊配置有1個或複數個焊墊J。
如圖4所示，焊墊J係藉由金屬配線metalJ與第2半導體晶片chip2之內部電路circ2連接。
焊墊H與焊墊J係分別以金屬線wireH及金屬線wireJ，經由各自對應之引線端子Lead連接。
藉此，第1半導體晶片chip1之內部電路circ1與第2半導體晶片chip2之內部電路circ2可進行信號之收發。
對圖7之比較例，圖2所示之本發明實施方式1之半導體裝置中，焊墊H係於第1半導體晶片chip1之主面上，沿著與配置有焊墊A、B的邊不同的邊而配置。在本實施方式中，焊墊H係沿著與配置有焊墊A、B的邊交叉的邊而配置。
另外，焊墊J亦係在第2半導體晶片chip2之主面上中，沿著與配置有焊墊C的邊不同的邊配置，配置該焊墊J的邊與配置有上述焊墊H的邊並排。
再者，焊墊H與焊墊J係藉由金屬線wireHJ連接於晶片間。上述晶片間之連接係藉由打線接合法等形成。金屬線wireHJ之金屬線長度最好比金屬線wireA短。藉此，可減少信號的惡化及延遲。
另外，金屬線wireA由於會有比金屬線wireB多的電流流過，故金屬線wireA之金屬線長度最好比金屬線wireB之金屬線的長度短。由於以上原因，各金屬線長度的關係變成：金屬線wireHJ<金屬線wireA<金屬線wireB。
如圖2所示，藉由將焊墊H與焊墊J做晶片間連接，與圖7所示之比較例中經由引線連接時相比，可使配線的長度變短。藉此，與圖7所示之比例中，經由引線端子Lead之連接時相比，可減少內部電路circ1與內部電路circ2之間的信號之惡化及延遲。
另外，通過將焊墊H與焊墊J作晶片間連接，由於不需要用於連接之引線端子Lead，故可減少封裝PKG之接腳數。再者，可將來自封裝PKG外部之雜訊對信號線的影響抑制至最小。
如圖2所示之本發明實施方式1之半導體裝置中，包含焊墊H與焊墊J之信號區域SigArea，及包含焊墊A、焊墊B、焊墊C及引線端子VREG1之電源區域PowArea係配置於彼此不同的邊。下面將說明其理由。
圖9係表示信號區域SigArea與電源區域PowArea排列於同一邊時之詳細情形圖。
如圖9所示，信號區域SigArea與電源區域PowArea排列配置時，內部電路circ1與內部電路circ2經由金屬線wireHJ進行信號收發時，以信號區域SigArea與電源區域PowArea回繞形成之金屬線wire將成為天線，有可能將從信號區域SigArea向電源區域PowArea傳遞雜訊。此類雜訊，多為以超過數百MHz之信號所產生的高頻波雜訊。特別是由於電源區域PowArea中具有3條金屬線，故容易受到雜訊的影響。
因此，如圖2所示，並不是將信號區域SigArea與電源區域PowArea排列配置，而藉由互相配置於不同的邊(在本實施方式中是直角方向)，從而減少電源區域PowArea受到來自信號區域SigArea之雜訊的影響。
圖10係表示相對於配置有電源區域PowArea的邊，而將信號區域SigArea配置於不同的邊之例子之詳細情形圖。
圖10(a)係表示於與配置有電源區域PowArea的邊交叉的邊上，配置有信號區域SigArea之例子之詳細情形圖。圖10(b)係表示於與配置有電源區域PowArea的邊相對的邊上，配置信號區域SigArea之例子之詳細情形圖。
圖10(a)與圖2相同，於與配置有電源區域PowArea的邊交叉的邊 上配置信號區域SigArea。而且，上述信號區域SigArea係配置於比配置有電源區域PowArea的邊更靠近沒配置有電源區域PowArea的邊相對的邊。
圖10(b)所示的係在與配置有電源區域PowArea的邊相對的邊上配置有信號區域SigArea。換言之，亦可說是電源區域PowArea與信號區域SigArea係夾著第2半導體晶片chip2而配置。
如上述所示，圖10(a)(b)均係將信號區域SigArea配置於與配置有電源區域PowArea的邊不同的邊上。藉此，由於電源區域PowArea與信號區域SigArea並不會並排，故可減少電源區域PowArea受到來自信號區域SigArea之雜訊的影響。上述信號區域SigArea的配置方法，可減少在封裝內受限的空間中的雜訊。
圖11係表示與相對於配置有電源區域PowArea的邊上，信號區域SigArea配置在不同邊上與圖10相異的例子之詳細情形圖。
圖11與圖10之差異係焊墊C並非配置於與配置焊墊A、B的邊並排的邊上，而係沿著與配置有焊墊A、B的邊交叉的邊而配置。如上上述，也可將電源區域PowArea橫跨2個邊而配置。
對此，信號區域SigArea係使用沒配置有電源區域PowArea之對角側之2個邊而配置。換言之，即電源區域PowArea與信號區域SigArea係夾著第2半導體晶片chip2而配置於對角方向。
即使如圖11所示進行配置，亦與圖10之情形相同，由於電源區域PowArea並不會與信號區域SigArea並排，故可減少來自信號區域SigArea之雜訊。
要是對圖10及圖11中的焊墊A、B及C之配置，及焊墊H及焊墊J的配置進行總結則可作如下描述。
第1半導體晶片chip1具有4個角，將其中1個角作為角corner1時，於4個角之中焊墊A及焊墊B接近於角corner1配置。
同樣地，第2半導體晶片chip2亦具有四個角，將其中的1個角作為角corner2時，第2半導體晶片chip2係於第1半導體晶片chip1之主面上，使角corner2比第1半導體晶片之其他角更接近角corner1而層積。而且，於4個角之中接近於焊墊C角corner2配置。
接著，焊墊H係配置於與構成第1角的邊不同的邊上，焊墊J係配置於配置有焊墊H的邊並排的邊上。
另外，如圖10及圖11所示之引線端子VREG1之兩相鄰端子，分配給無連接NC或接地電壓(接地極)GND比分配給信號或時脈時更好。藉此，可減少賦予內部電源電壓intVcc之雜訊。
接著說明在信號區域SigArea中內部電路間的信號的收發對電源區域PowArea內的調節器電路Reg的動作的影響，及減少該影響的方法。
圖12係表示調節器電路Reg、內部電路circ1-1及內部電路circ1-2分別連接於金屬配線metalV與金屬配線metalG之詳細情形圖。內部電路circ1-1及內部電路circ1-2係指設有複數個圖1所示之內部電路circ1。
圖12(a)表示將調節器電路Reg、內部電路circ1-1及內部電路circ1-2分別共同連接於焊墊G。圖12(b)表示將連接有調節器電路Reg之焊墊G與連接有內部電路circ1-1及內部電路circ1-2之焊墊G分開設置時的情況。
如圖12(a)所示，調節器電路Reg、內部電路circ1-1及內部電路circ1-2係以金屬配線metalV與由封裝PKG之外部供給外部電源電壓extVcc之焊墊V連接。
另外，調節器電路Reg、內部電路circ1-1及內部電路circ1-2係以金屬配線metalG與由封裝PKG外部供給接地電壓(接地極)GND之焊墊G連接。
內部電路circ1-1及內部電路circ1-2與內部電路circ2進行信號的收發時，則由各電路流出電流i至金屬配線metalG。金屬配線metalG由於具有配線電阻R，且有來自2個電路之電流流過，故會產生2iR(=V)電壓。
此時，有可能所產生的2iR(=V)使接地極GND之電位上升(發生接地極偏移)的情況。然後，連接於相同焊墊G之調節器電路Reg之接地極GND亦因電位上升而有可能變得動作不穩定。
為了避免如上上述之調節器電路Reg之不穩定動作，如圖12(b)所示，可將連接有調節器電路Reg之焊墊G、及連接有內部電路circ1-1及內部電路circ1-2之焊墊G分開設置。
即，最好將電源區域PowArea之焊墊G及信號區域SigArea之焊墊G分開設置。
通過分開設置焊墊G，如圖12(b)所示，即使內部電路circ1-1及內部電路circ1-2與內部電路circ2進行信號收發，電流也不會流入調節器電路Reg之接地極GND，所以接地極GND之電位亦不會上升，由此可以減少調節器電路Reg之動作不穩定之情形。
以上說明了實施方式1之半導體裝置的幾個特徵。
主要的1例係將2個晶片層積，並將焊墊A、B及C分別配置於各個晶片排列的邊上，將上述焊墊分別通過金屬線wireA、B及C共通地連接。
藉此，與通過電路基板上的配線連接相比，可使配線長度變短，從而使內部電源電壓intVcc不容易接受來自配線電阻之電壓降之影響。
另一例係沿著與配置有焊墊A、B及C的邊不同的邊配置焊墊H及焊墊J，還以金屬線wireHJ做晶片間接合連接。
藉此，可使配線長度比經由引線端子Lead連接時短，故可減少 信號惡化。另外，藉由將電源區域PowArea與信號區域SigArea配置於不同的邊而非並排，故電源區域PowArea不容易接受來自信號區域SigArea之雜訊。
再者，雖已於實施方式1說明了多個特徵，但並非是說必須要全部具備這些特徵，而只要具有上述特徵中之1個即可，亦可為複數個特徵之組合。這點在以後所說明之實施方式中亦相同。
(實施方式2)
圖13係本發明實施方式之半導體裝置的引線端子VREG1與金屬 線wireA、B及C之連接部之放大圖。
圖13(a)係表示金屬線與引線端子之連接點pointC較連接點pointB更接近連接點pointA之位置之狀態圖。圖13(b)係表示金屬線與引線端子之連接點pointC在連接點pointA與連接點pointB之間之位置的狀態圖。
如圖13(a)所示，內部電源輸出焊墊之焊墊A與引線端子VREG1通過金屬線wireA連接。將該金屬線wireA與引線端子VREG1之連接部為連接點pointA。
監測器焊墊之焊墊B與引線端子VREG1通過金屬線wireB連接。將該金屬線wireB與引線端子VREG1之連接部作為連接點pointB。
內部電源輸入焊墊之焊墊C與引線端子VREG1通過金屬線wireC連接。使該金屬線wireC與引線端子VREG1之連接部作為連接點pointC。
從焊墊A輸出，經過金屬線wireA及連接點pointA輸入至引線端子VREG1之內部電源電壓intVcc，係經過從連接點pointC輸入之金屬線wireC進入焊墊C。
此時，連接點pointB由於比連接點pointC更接近連接點pointA，故由連接點pointA附近取出輸入電壓Vback的狀態。
相對於圖13(a)，圖13(b)係表示連接點pointC設於連接點pointA與連接點pointB之間的狀態。
藉由在連接點pointA與連接點pointB之間設置連接點pointC，連接點pointB可從連接點pointC附近取出輸入電壓Vback。
藉此，並非從連接點pointA附近，而是從連接點pointC附近取出輸入電壓Vback，可從更接近焊墊C之位置取出。內部電源電壓intVcc在輸入至焊墊C前之配線路徑中，會因配線電阻等影響，而逐漸地產生電壓降。因此，在接近焊墊C的位置取出輸入電壓Vback，可更好地得到高精度的電壓。
另外，為了提升精度，最好使連接點pointC接近連接點pointB。即，最好是使連接點pointB至連接點pointC之距離Lbc比從連接點pointA至連接點pointC之距離Lac短。基於與上述相同的理由，由此可獲得精度高的電壓。
(實施方式3)
圖14係表示本發明實施方式3之半導體裝置之降壓開關部SW的 PMOS電晶體Ptr3及周邊部之剖面之詳細情形圖。
如圖14所示，輸入有外部電源電壓extVcc之焊墊V通過金屬配線metalV與PMOS電晶體Ptr3之源極電極之接觸部ifS連接。
再者，輸出內部電源電壓intVcc之焊墊A通過金屬配線metalA與PMOS電晶體Ptr3之汲極電極之接觸部ifD連接。
例如，將具有4~25V電壓值之外部電源電壓extVcc，通過調節器電路Reg降壓到具有1.4~3.6V電壓值之內部電源電壓intVcc時，因圖4所示之金屬配線metalV之配線電阻造成的電壓降，在對半導體裝置之穩定動作影響方面，大多情況下並不需要考慮。
但是，在1.4-3.6V之電壓值較小之內部電源電壓intVcc中，因圖4所示之金屬配線metalV之配線電阻造成電壓降，有時會招致內部電 路circ2之不穩定動作，從而有可能引發問題。
基於如此之理由，如圖14所示從焊墊A至汲極電極之接觸部ifD之長度La最好比從焊墊V至源極電極之接觸部ifS之長度Lv短。
通過使之變短，可減少內部電源電壓intVcc因配線電阻產生的影響。
另外，最好使金屬配線metalA之配線寬度比金屬配線(閘極配線)metal之寬度寬。
通過使配線寬度變寬，可減少配線電阻。
圖15係表示本發明實施方式3之半導體裝置之降壓開關部SW的PMOS電晶體Ptr3及周邊部之佈局之詳細情形圖。
難以比較上述焊墊A至汲極電極之接觸部ifD之長度La與焊墊V至源極電極之接觸部ifS之長度Lv時，由於性質方面並沒有較大地變化，所以也可代用接觸部與焊墊之直線距離之比較。
即，最好分別將圖15所示之焊墊A至汲極電極之接觸部ifD之直線距離Lda配置為比焊墊V至源極電極之接觸部ifS之直線距離Lsv短。
另外，為使直線距離Lda比直線距離Lsv短，最好將調節器電路Reg配置於配置有焊墊A及焊墊C的邊，這比起配置於沒有焊墊A及焊墊C配置的邊更好。
(實施方式4)
圖16係表示本發明實施方式4之半導體裝置之焊墊C與複數內部 電路circ2連接圖。
圖16(a)係表示內部電路circ2-1與內部電路circ2-2連接於焊墊C且焊墊C與內部電路circ2-2之間連接有焊墊X的圖。圖16(b)係表示內部電路circ2-1、內部電路circ2-2、內部電路circ2-3、及內部電路circ2-4共通地連接於焊墊C的圖。內部電路circ2-1、內部電路circ2-2、內部電路circ2-3、及內部電路circ2-4係指設有複數個圖1所示之內部電路 circ2。
如圖16(a)所示，內部電路circ2-2係與內部電路circ2-1比較時，例如比CPU等其他電路流過更多電流之電路。為更好地把握輸入至如此有較多電流流過的內部電路circ2-2之電壓精度，最好焊墊X通過金屬配線metalX與連接焊墊C及內部電路circ2-2之金屬配線metalC連接。
藉此，通過金屬配線metalX連接焊墊X，將從焊墊X取出的反饋至調節器電路Reg的輸入電壓Vback反饋至調節器電路Reg，與圖4所示的通過引線端子VREG1取出相比，可取出精度較高的電壓。
另外，此時，如圖4所示之第1半導體晶片chip1之焊墊B並不是連接於引線端子VREG1，而最好是使用圖16(a)所示之焊墊X與金屬線wireB連接。
其次，有許多內部電路circ2、且在第2半導體晶片chip2動作並有使電源ON或OFF之電路混在一起時，在各個電路上，因為需要許多的焊墊而較難於將各個電路連接到上述焊墊X而進行個別監測。
對此，最好如圖16(b)所示，使金屬配線metalC由焊墊C分歧，分別連接至內部電路circ2-1、內部電路circ2-2、內部電路circ2-3及內部電路circ2-4。
藉此，經由引線端子VREG1監測焊墊C之電壓的焊墊B，即使有ON的電路與OFF的電路混在一起，亦可對輸入至內部電路circ2之電壓整體作最低限度的監測。
(實施方式5)
圖17係本發明實施方式5之半導體裝置之引線端子VREG1與金屬 線wireA、B及C的連接部之放大圖。
圖17(a)係表示焊墊A及焊墊C分別通過以複數條金屬線wireA及金屬線wireC與引線端子VREG1連接之狀態圖。圖17(b)係表示複數個焊墊A及焊墊C分別通過複數條金屬線wireA及金屬線wireC與引線端 子VREG1連接之狀態圖。
如圖17(a)所示，最好是使焊墊A及焊墊C之焊墊面積擴大到可連接複數條金屬線的程度，並使連接焊墊A與引線端子VREG1之金屬線wireA及連接焊墊C與引線端子VREG1之金屬線wireC為複數條。
藉由將金屬線wireA與金屬線wireC為複數條，可降低2個焊墊(焊墊A、焊墊C)與引線端子VREG1之間的配線電阻，從而減少內部電源電壓intVcc之電壓降。
另外，亦可如圖17(b)所示，藉由使焊墊A及焊墊C複數焊墊化，從而將金屬線wireA及金屬線wireC複數條化。
在本實施方式中，亦可降低2個焊墊(焊墊A、焊墊C)與引線端子VREG1間的配線電阻，從而減少內部電源電壓intVcc之電壓降。
(實施方式6)
圖18係表示本發明實施方式6之半導體裝置之調節器電路及周邊 部之詳細情形圖。
如圖18所示，本發明實施方式6之半導體裝置與實施方式1之主要差異，係金屬線wireA與引線端子VREG1之外的引線端子VREG0連接。
另外，引線端子VREG1與其他的引線端子VREG0，係通過構裝有封裝PKG之電路基板上之配線wireSub連接。
引線端子的寬度狹窄時，造成使用的打線接合裝置等的性能較低，而無法將3條金屬線wireA、B及C一起連接於引線端子VREG1時，若引線端子容許，最好如圖18所示地分成2個引線端子進行連接。
藉由使上述2個引線端子在封裝PKG之外側連接，可得到與實施 方式1之半導體裝置同等的效果。
(實施方式7)
圖19係表示本發明實施方式7之半導體裝置之調節器電路及周邊部之詳細情形圖。
如圖19所示，本發明實施方式7之半導體裝置與實施方式1的主要差異，係金屬線wireC並非連接於引線端子VREG1，而是連接於作為內部電源輸出焊墊之焊墊A。
通過使金屬線wireC與焊墊A連接，因不經由引線端子VREG1而可使配線長度變短。因此，可對焊墊C輸入比實施方式1之半導體裝置電壓降少的內部電源電壓intVcc。
但是，由於焊墊C與引線端子VREG1並沒有連接，從封裝PKG外側經由引線端子VREG1可監測之電壓並不是焊墊C之電壓，而是焊墊A之電壓。
(實施方式8)
圖20係表示本發明實施方式8之半導體裝置之調節器電路及周邊 部之詳細情形圖。
如圖20所示，本發明實施方式8之半導體裝置與實施方式1的主要差異，係金屬線wireB並不是連接於引線端子VREG1，而是連接於作為內部電源輸入焊墊之焊墊C。
藉由使金屬線wireB與焊墊C連接，可不經由引線端子VREG1從焊墊C取出輸入電壓Vback。藉此，可使引線端子VREG1所產生電壓降部分消失，所以比起實施方式1之半導體裝置，可取出精度高的輸入電壓Vback，並反饋至調節器電路Reg。
(實施方式9)
圖21係表示本發明實施方式9之半導體裝置之調節器電路及周邊 部之詳細情形圖。
如圖21所示，本發明實施方式9之半導體裝置與實施方式8之主要差異係金屬線wireA並不是連接於引線端子VREG1，而是連接於作 為內部電源輸入焊墊之焊墊C。
通過使金屬線wireA與焊墊C連接，因不經由引線端子而可使配線長度變短。因此，可對焊墊C輸入比實施方式8之半導體裝置精度高的內部電源電壓intVcc。
另外，由於焊墊B經由金屬線wireB與焊墊C連接，所以比起與實施方式8之半導體裝置，可取出輸入電壓精度提高部分之高精度的輸入電壓Vback，並反饋至調節器電路上。
以上，說明了實施方式1、6、7、8、9之半導體裝置。關於上述作為監測器焊墊之焊墊B之連接，可大致分為二種。
於實施方式1、6、7之半導體裝置中，焊墊B由引線端子VREG1取出輸入電壓Vback。
即，可說是監測器焊墊之焊墊B，電性連接於內部電源輸出焊墊之焊墊A與內部電源輸入焊墊之焊墊C之連接路徑間。
另外，實施方式8、9之半導體裝置中，焊墊B從焊墊C取出輸入電壓Vback。
即，可說是監測器焊墊之焊墊B，經由內部電源輸入焊墊之焊墊C電性連接於內部電源輸出焊墊之焊墊A。
(實施方式10)
圖22係本發明實施方式10之半導體裝置的封裝構造之平面圖。
圖23係本發明實施方式10之半導體裝置的封裝構造之剖面圖。
圖23(a)係圖22之A-A'剖面圖。圖23(b)係圖22之B-B'剖面圖。
如圖22及圖23所示，本發明實施方式10之半導體裝置與實施方式1之主要差異，係第2半導體晶片chip2於第1半導體晶片chip1之主面上呈十字平面形狀層積。另外，在沒有第2半導體晶片chip2重疊之第1半導體晶片chip1之主面上所露出的區域集中配置有複數個焊墊BP1。
下面說明如此層積之理由。
圖24係表示相對於圖22的平面圖之比較例之詳細情形圖。
如圖24所示，在本實施方式中，第1半導體晶片chip1與第2半導體晶片chip2的外形是大致同等。此時在第1半導體晶片chip1之主面上，如果將第2半導體晶片chip2以各個長邊相互並排地層積，則配置於第1半導體晶片chip1之主面上的複數個焊墊BP1及焊墊H將被第2半導體晶片chip2掩蓋。
將2個晶片層積時，上段晶片會覆蓋下層晶片之主面時，如圖22所示，為了確保用於配置下層晶片之焊墊的區域，最好考慮好上段晶片之裝載方向再做層積。
藉由確保用於配置下層晶片之焊墊之區域，可容易進行全體焊墊之配置。
另外，如圖22所示有幾個藉由層積2個晶片而得的情形。以下說明上述例。
最初的例子係關於第1半導體晶片chip1之內部電源輸出焊墊(焊墊A)、監測器焊墊(焊墊B)及第2半導體晶片chip2之內部電源輸入焊墊(焊墊C)之配置關係。
如圖22所示，第1半導體晶片chip1具有第1長邊1L1、第2長邊1L2、第1短邊1S1、第2短邊1S2。
第2半導體晶片chip2具有第1長邊2L1、第2長邊2L2、第1短邊2S1、第2短邊2S2。
如圖22所示，焊墊A與焊墊B係配置於第1半導體晶片chip1與第2半導體晶片chip2沒有重疊之第1半導體晶片chip1的主面上之區域S1。
該區域S1係以第1半導體晶片chip1之第1短邊1S1與第2半導體晶片之第1長邊2L1所夾的區域。
而且，焊墊A與焊墊B係於區域S1上，沿著第1長邊1L1配置。
焊墊C係於第2半導體晶片chip2之主面上，沿著第1短邊2S1配置。
第1半導體晶片chip1之第1長邊1L1，與第2半導體晶片chip2之第1短邊2S1是並排的邊。因此，沿著上述的邊配置之焊墊A、B及C均並排配置於同一側。
另外，焊墊A、B及C係分別通過金屬線wireA、B及C共通地連接於引線端子VREG1。
換言之，就是焊墊A、B及C係經由引線端子VREG1，分別以金屬線wireA、B及C電性連接。
如圖22所示，即使是使2個晶片以十字平面形狀層積時，可將焊墊A、B及C沿著各個晶片所並排的邊配置，以金屬線wireA、B及C分別共通地連接於引線端子VREG1。藉此，與實施方式1之半導體裝置同樣地，可使配線長度比以構裝有封裝PKG之電路基板上之配線連接時短。
下面說明下一個例子。
如圖22所示，於第1半導體晶片chip1之第2短邊1S2與第2半導體晶片chip2之第2長邊2L2所夾之第1半導體晶片chip之主面上設有區域S2。
於該區域S2上面，配置有1個或複數個焊墊H。
而且，於第2半導體晶片chip2之主面，沿著第2半導體晶片chip2之第2長邊2L2配置有1個或複數個焊墊J。
焊墊H與焊墊J，與實施方式1之半導體裝置同樣，通過金屬線wireHJ進行晶片間連接。
藉此，與實施方式1之半導體裝置同樣地，第1半導體晶片chip1之內部電路circ1，及連接於焊墊J之第2半導體晶片chip2之內部電路circ2，可進行信號之收發。
而且，關於本實施方式10之半導體裝置，亦與實施方式1之半導體裝置同樣地，晶片間連接有焊墊H、J之信號區域SigArea配置的邊，與焊墊A、B及C與引線端子VREG1共通地連接之電源區域PowAre配置的邊，係不同的邊。
藉此，與實施方式1之半導體裝置同樣地，金屬線wire成為天線，從而可減少從信號區域SigArea對電源區域PowArea所造成之雜訊。
下面說明下一個例子。
如圖22所示，於第2半導體晶片chip2之主面，沿著第2長邊2L2、第1短邊2S1及第2短邊2S2配置有複數個焊墊BP2。但是，並沒有沿著第1長邊2L1配置焊墊BP2。
對沿著第2半導體晶片chip2之第1長邊2L1配置有焊墊BP2時之不良狀況事項加以說明。
圖25係於第2半導體晶片chip2之第1長邊2L1配置有焊墊BP2時，焊墊A、B之周邊部分之放大圖。
如圖25所示，沿著第2半導體晶片chip2之第1長邊2L1配置複數個焊墊BP2，並且連接有金屬線wire。另外，在區域S1上配置有焊墊A、焊墊B及複數個焊墊BP1，同樣地，與金屬線wire連接。連接於焊墊BP2之金屬線wire，係呈覆蓋連接於焊墊A、焊墊B及複數個焊墊BP1之金屬線wire上。
此時，若連接於焊墊BP2之金屬線，與連接於焊墊A、焊墊B及複數個焊墊BP1之金屬線之距離(間隙)並不充分時，對形成封裝PKG之封裝體mold之成形模具注入熔融樹脂時，因該注入壓而發生使金屬線倒塌現象之導線流，而會使金屬線wire之間短路(短路)之情形變多。
另一個是例如通上內部電源電壓intVcc之金屬線wireA，或通上 輸入電壓Vback之金屬線wireB上，有收發超過數百MHz之信號的金屬線wire時，會以金屬線wire作為天線而將雜訊傳播，有可能使內部電源電壓intVcc受到雜訊影響。
基於以上之理由，並不沿著第2半導體晶片chip2之第1長邊2L1配置焊墊BP2。
下面說明下一個例子。
於層積於上段之第2半導體晶片chip2之下配置有調節器電路Reg時，調節器電路Reg於動作時所產生的熱有可能對第2半導體晶片chip2之動作帶來影響。
如圖22所示的本發明實施方式10之半導體裝置中，例如假設將供給的最大25V之外部電源電壓extVcc，產生降壓至1.5V之內部電源電壓intVcc。此時，調節器電路Reg中，流過最大20mA左右之電流*。
另外，假設QFP之熱電阻，如為51℃/W。
藉此調節器電路Reg在動作時，(25-1.5)(V)*0.020(A)*51(℃/W)=23.97(℃)、即，溫度上升最大為大約24℃。
假設周圍環境溫度為85℃，則調節器電路Reg上升24℃為109℃。
構成半導體晶片之材料，例如有矽(Si)。上述矽之熱傳導率是168W/(m‧K)。
另外，構成封裝體mold之環氧樹脂之熱傳導率是0.21W/(m‧K)。
矽的熱傳導率比環氧樹脂大。即，半導體晶片比封裝體容易傳導熱。
第2半導體晶片chip2經由接著膜film2層積於第1半導體晶片chip1之上。
接著膜film2一般係由環氧樹脂構成，由於膜厚度較薄(25μm左 右)，在此可以忽略其阻礙熱傳導。
調節器電路Reg配置在第2半導體晶片chip2下時，其熱量(在此是109℃)將被傳至第2半導體晶片chip2。
一般而言，半導體晶片之接面溫度為150℃左右，在該溫度時則接面漏電流會增大，可能造成晶片之動作不穩定。實際上亦有從超過120℃，即漏電流以μA的羃次急劇地變大之情形。
來自調節器電路Reg的熱量(在此是109℃)傳入第2半導體晶片chip2，例如在該溫度前後飽和時，晶片對接面溫度之容許範圍會變小。
而且，第2半導體晶片chip2係流過比在本實施方式中所計算之20mA更大的電流之晶片時，供給內部電源電壓intVcc之調節器電路Reg之發熱量也會變大，容許範圍將變得更小。
因此，對於晶片之接面溫度，為了確保容許範圍，如圖26所示，並不是將調節器電路Reg配置於第2半導體晶片chip2下，而最好是配置於區域S1。
藉此，可使第2半導體晶片chip2不容易受到熱的影響。
例如在佈局上，第2半導體晶片chip2與調節器電路Reg重疊時，最好使調節器電路Reg由第2半導體晶片chip2露出於第1長邊2L1外的部分的面積，比沒有露出的部分的面積大。
一般地，用於產生外部電源電壓extVcc降壓後的內部電源電壓intVcc之降壓開關部SW，係於調節器電路Reg之中產生熱最多之部分。因此，於調節器電路Reg上層積第2半導體晶片chip2時，如圖27所示，最好在降壓開關部SW之外的區域重疊層積。
如上上述，藉由至少使調節器電路Reg之降壓開關部SW不與第2半導體晶片chip2重疊，可減少傳入第2半導體晶片chip2的熱量，從而可減少第2半導體晶片chip2之動作變得不穩定。
以下說明下一個例子。
於上段晶片之位於調節器電路Reg之上方之區域，最好不要配置進行信號之輸出入之焊墊。
圖28係表示一般的輸出入電路之一例之詳細情形圖。
如圖28所示，內部電路circ2-1係以金屬配線metal與輸出電路outcirc之輸入部OI連接。
另外，內部電路circ2-2係以金屬配線metal與輸入電路incirc之輸出部IO連接。
焊墊S係以金屬配線metal與輸出電路outcirc之輸出部OO及輸入電路incirc之輸入部II連接。藉此，內部電路circ2-1及內部電路circ2-2經由焊墊S與其他電路進行信號之收發。
內部電路circ2-1、內部電路circ2-2及內部電路circ2-3係以金屬配線metalG分別與接地極GND連接。
從內部電路circ2-1經由輸出電路outcirc對焊墊S輸出信號時，由於輸出電路outcirc之電晶體尺寸大多比輸入電路incirc大(閘極寬度大)，故會流過比輸入電路incirc更大的電流。
此時，在連接輸出電路outcirc與接地極GND之金屬配線metalG中會有電流i流過。
金屬配線metalG具有配線電阻R，而在此將產生iR(=V)之電壓。
此時，因產生的iR(=V)使接地極GND之電位上升(接地偏移)，連接於金屬配線metalG之內部電路circ2-3有可能受其影響而動作變得不安定。
特別是內部電路circ2-3為以微小電流動作之類比電路時，更容易受到此類影響。
例如，電壓的限值在電源附近或在接地極附近之類比電路，或如檢測用於測定功率電晶體之ON電阻之嚴格的檢測限值之電路等。
如上上述，於進行信號之輸出入之焊墊S中連接有輸入電路incirc或輸出電路outcirc，該等輸出入電路，如上述所說明地，信號收發時容易使接地極GND電位上升(接地偏移)。
因此，將焊墊S配置於調節器電路Reg之附近時，連接於焊墊S之輸入電路incirc或輸出電路outcirc，將受到來自調節器電路Reg的熱的影響，而出現接地極GND之限值進一步發生變化的情形。此時，連接於該接地極GND之其他的電路亦會隨著該限值之變化而變得更加不安定的狀態。
基於上述原因，上段晶片的位於調節器電路Reg上的部分，最好不要配置進行信號之輸出入之焊墊。
而且，將複數晶片層積收容於1個封裝時，層積晶片之順序最好考慮以下幾點。
有會發熱之晶片，且其會對其他的晶片的動作帶來影響時，最好將發熱之晶片置於最下段。
最下段晶片如圖22及圖23所示，於封裝(QFP)內與晶座tab接著。
QFP係使用將引線端子Lead、晶座吊掛導線及晶座tab一體成形之導線架組裝而成的封裝。該導線架之材質以銅(Cu)系為多。
銅(Cu)的熱傳導率為398W/(mK)，比168W/(mK)的矽熱傳導率高，故較容易將熱傳導。
因此，藉由將發熱之晶片配置於最下段，晶座起到散熱片(heatsink)之作用，由此可減少熱傳至上段晶片。
另外，為有焊墊數較多的晶片時，最好將該晶片層積於最上段。
藉由層積於最上段，可於4邊全部配置焊墊，由此可容易以金屬線連接焊墊與引線端子(使打線接合變得容易)。
如圖22所示，為了使區域S1之面積較區域S2之面積大，最好在 第1半導體晶片chip1之上層積第2半導體晶片chip2(S1>S2)。即，使第1半導體晶片chip1之第1短邊1S1至第2半導體晶片chip2之第1長邊2L1之距離t1大於第1半導體晶片chip1之第2短邊1S2至第2半導體晶片chip2之第2長邊2L2之距離t2長(t1>t2)。
藉此，比起於距離t1與距離t2成t1≦t2之關係時，可收發內部電路circ1與內部電路circ2之信號的金屬線wireHJ之金屬線長度變短，由此可減少信號的惡化及延遲。另外，還可增加配置於區域S1之焊墊數。
以上，說明了實施方式10之半導體裝置之幾個特徵。並不需要全部具備上述特徵，可為具有上述特徵之中的1個特徵，或為複數個特徵之組合。
(實施方式11)
圖29係本發明實施方式11之半導體裝置之封裝構造之平面圖。
如圖29所示，本發明實施方式11之半導體裝置與實施方式10之差異，係焊墊A及焊墊B並不是配置於第1半導體晶片chip1之第1長邊1L1，而是沿著與配置有焊墊C的邊交叉之方向上的第1半導體晶片chip1之第1短邊1S1配置。
即使如此地配置焊墊A、B及C，亦與實施方式10之半導體裝置相同，可使配線長度比通過電路基板上之配線連接時短，可減少內部電源電壓intVcc因配線電阻導致的電壓降。
以上，至此於本發明實施方式10及11所說明之主要內容，亦可如下進行說明。
第2半導體晶片chip2具有：以其第1長邊2L1與第1半導體晶片chip1之第1短邊1S1所夾之區域S1；及以第2長邊2L2與第1半導體晶片chip1之第2短邊1S2所夾之區域S2。而且，在區域S1中，將第2半導體晶片chip2層積於第1半導體晶片chip1之主面以使得第1半導體晶片 chip1之焊墊BP1露出且覆蓋第1半導體晶片chip1之第1長邊1L1及第2長邊1L2。
第1半導體晶片chip1具有包含以其第1短邊1S1與第1長邊1L1所構成之角corner1之四個角，焊墊A及焊墊B係於區域S1上配置在比其他的角更接近角corner1之處。
另外，第2半導體晶片chip2具有包含以其第1短邊2S1與第1長邊2L1所構成之角corner2之四個角，焊墊C係於第2半導體晶片chip2的主面上配置在比其他的角更接近角corner2之處。
而且，焊墊H係配置於區域S2上，與焊墊H電性連接之焊墊J係於第2半導體晶片chip2之主面上沿著第2長邊2L2配置。
(實施方式12)
圖30係本發明實施方式12之半導體裝置之封裝構造之平面圖。
如圖30所示，本發明實施方式12之半導體裝置與實施方式10之差異，係第1半導體晶片chip1之焊墊數比第2半導體晶片chip2之焊墊數多，而且，第1半導體晶片chip1層積於第2半導體晶片chip2之主面上。
如調節器電路Reg的發熱小，而無需經由晶座tab放熱時，可於第2半導體晶片chip2之上層積具有調節器電路Reg之第1半導體晶片chip1。即使是如此地將上下層之晶片交換時，最好將焊墊A、B及C分別以金屬線wireA、B及C連接於引線端子VREG1。
2個晶片之中，藉由使焊墊數較多的晶片在上段，可使焊墊全部 露出，可對焊墊連接金屬線wire。
(實施方式13)
本發明實施方式13之半導體裝置與實施方式10之差異，係其構成為第1半導體晶片chip1具有2個調節器電路，而對第2半導體晶片chip2供給電壓值不同的2種電源電壓。
圖31係本發明實施方式13之半導體裝置的封裝構造之平面圖。
圖32係表示本發明實施方式13之半導體裝置的調節器電路及周邊部之詳細情形圖。
如圖32所示，本發明實施方式13之半導體裝置中，係於調節器電路Reg上追加設置調節器電路Reg2。
調節器電路Reg2產生將外部電源電壓extVcc降壓之內部電源電壓intVcc2。
內部電源電壓intVcc2從焊墊D輸出，並經由引線端子VREG2、電路基板上的配線wireSub及引線端子VDD2而輸入焊墊F。
又，調節器電路Reg從調節器電路Reg2供給內部電源電壓intVcc2，並產生將內部電源電壓intVcc2降壓之內部電源電壓intVcc。
因此，內部電源電壓intVcc2之電壓值，比內部電源電壓intVcc的電壓值高。
如圖32表示，焊墊F連接有內部電路circ2-2。連接於焊墊F之內部電路circ2-2，係以比連接於焊墊C之內部電路circ2-1高的電壓動作之電路。
例如，內部電源電壓intVcc2之電壓值為3.45V左右，而內部電源電壓intVcc之電壓值為1.5V左右。
如上上述，藉由以圖32所示之電路構成，可將通過複數半導體晶片之任一個所產生之電壓值不同的複數種類的電壓，作為電源電壓穩定地供給其他的半導體晶片。
而且在本實施方式中，內部電源電壓intVcc2為從引線端子VREG2輸出，經由電路基板上的配線wireSub，供給引線端子VDD2的結構。即，相對於內部電源電壓intVcc在封裝PKG內部供給第2半導體晶片chip2之內部電路circ2-1，內部電源電壓intVcc2係經過封裝 PKG外部供給內部電路circ2-2。
如上上述，因配置焊墊等之限制事項，而無法經由封裝PKG內之金屬線wire由一邊的晶片向另一邊的晶片供給內部電源電壓時，最好是將一般地對配線電阻之影響少，且並不是那麼需要精度之電壓值較高的電源電壓，經由封裝PKG外部之電路基板上之配線wireSub供給其他的晶片。
藉此，即使對焊墊的配置等的有所限制時，也不會對需要精度之電壓值低之內部電源電壓帶來影響，由此可穩定地將複數種類不同的電壓值之內部電源電壓安定供給其他的半導體晶片。
另外，本發明實施方式13之半導體裝置可用於各式各樣的應用。
例如，本發明實施方式13之半導體裝置，可使用於行動電話或筆記型電腦等數位機器的電源所用的鋰離子電池(以下，稱為「Li電池」)之電池電壓控制系統等。
以下，說明關於Li電池之電池電壓控制系統之應用例。
在Li電池之電池電壓控制系統中，第1半導體晶片chip1具有類比電路，係進行電源控制等之類比晶片。該類比晶片從連接的Li電池輸入電壓等資訊，並進行處理。常被稱為類比前端IC(以下，稱為「AFE」)。
第2半導體晶片chip2係控制AFE，並處理資訊之微電腦晶片(以下，稱為「MCU」)。
在Li電池之電池電壓控制系統中，將AFE與MCU收容於一個封裝之半導體裝置，多被搭載於筆記型電腦等之電池包內。
圖33係表示AFE與MCU之電池電壓控制系統之詳細情形的電路框圖。
如圖33所示，AFE監視例如4支串聯之Li電池Li之電壓等。各個 Li電池之+端子及-端子連接於AFE。於終端的+端子與-端子之間連接有負荷或充電器。
AFE按照來自MCU的命令，將各個Li電池電壓以既定的倍率(例如0.3倍左右)放大，作為GND基準之類比資料輸出至MCU。
MCU根據從AFE所輸入之類比資料算出Li電池之電壓。MCU除了上述檢測電池電壓之手段以外，還具有檢測充放電電流和溫度之手段。
而且，MCU將根據該等檢測結果與電池電壓檢測結果，判斷過充電狀態、過放電狀態等之電池狀態。
MCU之判定結果將輸出到AFE。AFE按照MCU的判定結果，將外接之功率MOSFET進行ON/OFF。AFE係於內部具有FET控制部，輸出功率MOSFET之控制信號。
功率MOSFET係串聯於充電及放電路徑，作為充放電開關動作。如上上述，藉由本半導體裝置，可將Li電池之電壓控制於既定的電壓範圍內。
另外，此時的AFE具有高耐壓部(35V)及低耐壓部(5V)。高耐壓部設有連接4個Li電池(單電池胞的Max電壓為4.2V左右)或16~18V左右之充電器之端子等。
低耐壓部設有如與MCU之序列資料I/O部等。這相當於圖31所示之焊墊H及焊墊J經由金屬線Wire連接晶片間連接之部分。
另一方面，MCU僅由低耐壓部構成。
MCU係由AFE之調節器電路供給內部電源電壓而動作。圖33所示之引線端子VREG1及引線端子VREG2相當於其供應端子。由引線端子VREG1供給內部電源電壓intVcc，由引線端子VREG2供給內部電源電壓intVcc2。另外，內部電源電壓intVcc之電壓值為1.5V左右，內部電源電壓intVcc2之電壓值為3.45V左右。MCU係將內部電源電 壓intVcc作為MCU電源，將內部電源電壓intVcc2作為MCU電源及LED用電源使用。
(實施方式14)
圖34係本發明實施方式14之半導體裝置的封裝構造之平面圖。
圖35係本發明實施方式14之半導體裝置的封裝構造之剖面圖。
圖35(a)係圖34之A-A'剖面圖。圖35(b)係圖34之B-B'剖面圖。
如圖34及圖35所示，本發明實施方式14之半導體裝置與實施方式10之主要差異，係將作為內部電源電壓intVcc之相位補償及對電壓穩定化之調節器容量之電容器Cap組裝入封裝PKG內部。
於晶座tab上，經由接著膜film1搭載內插器基板inter。內插器基板inter係以減去法等所形成之單層或2層左右的樹脂基板等或陶瓷基板等。另外，亦可為薄膜基板。可有效地使基板厚度變薄。
第1半導體晶片chip1及第2半導體晶片chip2分別經由接著膜film2、3層積於內插器基板inter上。
如圖34所示，以第1半導體晶片chip1之第1長邊1L1、第2半導體晶片chip2之第1長邊2L1及內插器基板inter之外周所圍之內插器基板inter之主面，設有觸點LD1及觸點LD2。而且，於該等觸點LD1及觸點LD2上，搭載有電容器Cap。
電容器Cap最好使用可收納入封裝PKG(QFP)中的程度的小面構裝型。在本實施方式中，圖示使用以層積介電體片所形成之積層陶瓷晶片電容的例。另外，電容器Cap亦可為燒結金屬鉭粉所形成之鉭質電解電容器。鉭質電解電容器可得到比積層陶瓷電容器更大的容量。
電容器Cap之2個電極係分別以銲錫或導電性糊料等電性連接於觸點LD1及觸點LD2。
焊墊A、B及C係分別以金屬線wireA、B及C與觸點LD1連接。另外，觸點LD2以金屬線wireG連接於供給接地電壓(接地極)GND之引線 端子Vss。
如上上述，藉由於封裝內組裝入電容器Cap，可減少電路基板上的零件數。另外，由於焊墊A、B及C分別以金屬線wireA、B及C共同地連接於觸點LD1，故無需如圖22所示之引線端子VREG1。因此，可減少封裝PKG之接腳數。
另外，將2個晶片以十字平面形狀層積所獲得的區域，即，於第1半導體晶片chip1之第1長邊1L1、第2半導體晶片chip2之第1長邊2L1及內插器基板inter之外周所圍之內插器基板inter之主面上的區域配置電容器Cap，由此，無需擴大封裝尺寸，便可使尺寸與實施方式10之半導體裝置之封裝PKG尺寸同等。
再者，將電容器Cap連接於觸點LD1及觸點LD2之銲錫，最好使用鉛(Pb)含有率為90%以上的高熔點銲錫。通過使用高熔點銲錫，可使銲錫熔點比在電路基板上構裝封裝PKG時之回焊溫度高。藉此，可防止銲錫在封裝PKG內再溶融而造成電容器Cap電極間的短路(short)或封裝龜裂。
封裝PKG需要對應無鉛(Pb)時，最好使用有廣用性、容易購得之Sn-Ag系或Sn-Ag-Cu系之銲錫作為無鉛(Pb)銲錫。組成比為Ag1.0~3.5%，Cu0~0.5%，其他的是Sn。但是，無法避免在將封裝PKG構裝在電路基板上之回焊時發生銲錫再溶融。因此，封裝體mold可吸收(緩和)，在銲錫發生溶融而體積膨脹時的其體積膨脹部分，最好事先採用樹脂材料降低彈性率而使封裝不會發生龜裂。
(實施方式15)
圖36係本發明實施方式15之半導體裝置的封裝構造之平面圖。
圖37係本發明實施方式15之半導體裝置的封裝構造之剖面圖。
圖37(a)係圖36之A-A'剖面圖。圖37(b)係圖36之B-B'剖面圖。
如圖36及圖37所示，本發明實施方式15之半導體裝置與實施方 式14之主要差異在於封裝PKG係BGA(Ball Grid Array)封裝。
第1半導體晶片chip1及第2半導體晶片chip2分別經由接著膜film1、2層積於內插器基板inter上。
內插器基板inter係以建構法等形成之多層配線樹脂基板等。配線多以銅(Cu)等形成。
第1半導體晶片chip1及第2半導體晶片chip2分別經由接著膜film1、2層積於內插器基板inter上。
另外，於內插器基板inter的主面配置有複數第二焊墊secP。第1半導體晶片chip1之複數接合焊墊BP1及第2半導體晶片chip2之複數接合焊墊BP2分別以金屬線wire連接對應之複數第二焊墊secP。
另外，如圖36及圖37所示，第二焊墊secP的數量，圖字中的數字只是為了方便說明而舉出的適當數，實際數量可比圖字的數多或少。
複數第二焊墊secP係經由貫孔via連接於封裝PKG背面之觸點焊墊LP。此外觸點焊墊LP上連接有銲錫球ball。銲錫球ball的銲錫，多為Sn-Pb之共晶銲錫。封裝PKG需要對應無鉛(Pb)時，最好使用廣用性、容易購得之Sn-Ag系或Sn-Ag-Cu系之銲錫作為無鉛(Pb)銲錫。組成比為Ag 1.0~3.5%，Cu 0~0.5%，其他的是Sn。
另外，如圖36及圖37所示，觸點焊墊LP與銲錫球ball的數量，圖字中的數字只是為了方便說明而舉出的適當數，實際數量可比圖字的數多或少。
上述實施方式14之半導體裝置中，搭載有電容器Cap之觸點LD2，通過金屬線wireG與引線端子Vss連接。本實施方式15的半導體裝置中，觸點LD2經由貫孔via與供給有接地電壓(接地極)GND之銲錫球ball連接。
如上上述，通過將封裝PKG由QFP改成BGA，由於無需引線端子Lead，可使封裝尺寸變小。而且，QFP時所得之效果，於將封裝形態 改為BGA之本實施方式15之半導體裝置時亦可同樣地獲得。
以上，說明了本發明實施方式1至15的半導體裝置。至此上述之任何發明，均係提供在將複數半導體晶片層積於同一封裝的半導體裝置中，將複數半導體晶片之任何一個所產生的電壓，作為電源電壓供給其他的半導體晶片，從而可實現該半導體裝置穩定地動作之技術。
於至此說明之各實施方式之半導體裝置之封裝雖為QFP及BGA，同時亦可為同是面構裝封裝之CSP(Chip Size Package：晶片尺寸封裝)或在封裝的背面沒有設置銲錫球之LGA(Land Grid Array：柵格陣列)封裝，並非限定於在本實施方式中所記載之封裝種類。
QFP引線端子(導線架)可為金屬性(導電性)材料之銅(Cu)系，亦可為鐵(Fe)系與鎳(Ni)的合金之合金42。
引線端子係以封裝體為邊界露出於封裝外部，以構裝時與電路基板銲接之外引線，及以金屬線wire於封裝內部與半導體晶片連接之內引線所構成。
外引線之表面施有外層鍍敷。外層鍍敷係Sn-Pb銲錫鍍敷等。封裝需要對應無鉛時為無鉛銲錫鍍敷。
雖然圖中所示為晶座的外形(尺寸)比搭載於QFP的晶座上的晶片外形(尺寸)大，相反地，為小亦可。
晶座的外形(尺寸)比搭載於晶座上的晶片外形(尺寸)小時，晶片的背面會與封裝體之樹脂接著。由於半導體晶片(矽)與樹脂之界面接著力比晶座(金屬)與樹脂之界面接著力大，故可防止水分滲入晶座與樹脂之界面。結果，通過銲錫回焊將封裝構裝於基板時可抑制滲入水分因回焊之熱產生膨脹而造成封裝龜裂。
另外，以上就使用接著膜層積半導體晶片之構造進行了說明。亦可用接著塗料來代替接著膜塗料。
但是，比起接著塗料，接著膜在製造時的管理更容易。接著膜 由於膜厚的偏差比接著塗料之供應量的偏差小，故晶片構裝後之完成品偏差較少。因此，容易管理接著後之膜(接著膜)之厚度。
另外，對於接著後接著材料從晶片的溢出，接著膜比接著塗料少。溢出較少者可避免在下層晶片之焊墊沾到接合劑，從而可避免無法連接到金屬線等不良。
以上按照實施方式具體地說明了本案發明人所作的發明，但是本發明並不受到上述實施方式之限定，在不超出其要旨的範圍下能夠進行種種變更，在此無需贅言。另外，可將實施方式1至15進行適當的組合，亦可僅利用各實施方式之一部分進行適當的組合。
[產業上的可利性]
本發明可廣泛地用於製造半導體裝置之製造業。
A、B、C、H、J、V、BP1、BP2‧‧‧焊墊
Cap‧‧‧電容器
chip1‧‧‧第1半導體晶片
chip2‧‧‧第2半導體晶片
circ1、circ2‧‧‧內部電路
extVcc‧‧‧外部電源電壓
GND‧‧‧接地電壓(接地極)
IntVcc‧‧‧內部電源電壓
Lead、VREG1‧‧‧引線端子
Mold‧‧‧封裝體
NC‧‧‧無連接
PKG‧‧‧封裝
PowArea‧‧‧電源區域
Reg‧‧‧調節器電路
SigArea‧‧‧信號區域
tab‧‧‧晶座
Vback‧‧‧輸入電壓
Vcc‧‧‧引線端子
wire、wireA、wireB、wireC、wireHJ‧‧‧金屬線

Claims (9)

  1. 一種半導體裝置，其包含：第1半導體晶片，其包含配置有複數電極焊墊之第1主面；第2半導體晶片，其包含配置有複數電極焊墊之第2主面；複數外部端子；及封裝體，其封裝上述第1半導體晶片及上述第2半導體晶片；其中上述第1半導體晶片包含上述第1主面，該第1主面配置有：第1電極焊墊，其係從第1外部端子供給外部電源電壓者；調節器電路，其係與上述第1電極焊墊電性連接，按照參考電壓及與上述參考電壓比較之輸入電壓產生將上述外部電源電壓降壓之內部電源電壓者；及第2電極焊墊，其係電性連接於上述調節器電路，輸出上述內部電源電壓者；上述第2半導體晶片包含上述第2主面，該第2主面配置有第3電極焊墊，該第3電極焊墊係從上述第1半導體晶片之上述第2電極焊墊輸入上述內部電源電壓者；上述第2電極焊墊及上述第3電極焊墊之各者係經由第1金屬線及第2金屬線與第2外部端子電性連接；上述第1金屬線之一端部係與上述第2電極焊墊電性連接；上述第2金屬線之一端部係與上述第3電極焊墊電性連接；且上述第1金屬線及上述第2金屬線之各者之他端部係與上述第2外部端子電性連接。
  2. 如請求項1之半導體裝置，其中上述第1半導體晶片之上述第1主面係配置有第4電極焊墊，該 第4電極焊墊係與輸入上述輸入電壓的上述調節器電路之輸入部電性連接；上述第4電極焊墊係經由第3金屬線與上述第2外部端子電性連接；上述第3金屬線之一端部係與上述第4電極焊墊電性連接；上述第3金屬線之他端部係與上述第2外部端子電性連接。
  3. 如請求項2之半導體裝置，其中於將上述第1金屬線之上述他端部與上述第2外部端子之連接點設為第1連接點、上述第2金屬線之上述他端部與上述第2外部端子之連接點設為第2連接點、上述第3金屬線之上述他端部與上述第2外部端子之連接點設為第3連接點時，上述第3連接點係以相較上述第2連接點較靠近上述第1連接點之方式配置。
  4. 如請求項2之半導體裝置，其中於將上述第1金屬線之上述他端部與上述第2外部端子之連接點設為第1連接點、上述第2金屬線之上述他端部與上述第2外部端子之連接點設為第2連接點、上述第3金屬線之上述他端部與上述第2外部端子之連接點設為第3連接點時，上述第3連接點係以相較上述第1連接點較靠近上述第2連接點之方式配置。
  5. 如請求項2之半導體裝置，其中上述第1金屬線之長度較上述第3金屬線之長度短。
  6. 如請求項1之半導體裝置，其中上述第2外部端子係經由電容器而可與接地極電性連接之端子。
  7. 如請求項2之半導體裝置，其中上述第1半導體晶片之上述第1主面包含第1邊及與上述第1邊對向之第2邊； 上述第2半導體晶片之上述第2主面包含第3邊及與上述第3邊對向之第4邊；上述第1半導體晶片之上述第2電極焊墊及上述第4電極焊墊係以相較上述第2邊較靠近上述第1邊之方式配置；上述第2半導體晶片之上述第3電極焊墊係以相較上述第4邊較靠近上述第3邊之方式配置；上述第1半導體晶片之上述第1邊係以相較上述第2邊較靠近上述第2外部端子之方式配置；上述第2半導體晶片之上述第3邊係以相較上述第4邊較靠近上述第2外部端子之方式配置。
  8. 如請求項7之半導體裝置，其中上述第1半導體晶片之上述第1主面的平面形狀係上述第1邊及上述第2邊為長邊的長方形之形狀；上述第2半導體晶片之上述第2主面的平面形狀係上述第3邊及上述第4邊為長邊的長方形之形狀。
  9. 如請求項1之半導體裝置，其中上述第1半導體晶片係包含類比電路，而進行電源控制之類比晶片；上述第2半導體晶片係控制上述第1半導體晶片，並處理資訊之微電腦晶片。
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CN101677096A (zh) 2010-03-24
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CN101677096B (zh) 2013-09-11
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TW201013890A (en) 2010-04-01
US20120146245A1 (en) 2012-06-14

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