TWI778382B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI778382B
TWI778382B TW109123557A TW109123557A TWI778382B TW I778382 B TWI778382 B TW I778382B TW 109123557 A TW109123557 A TW 109123557A TW 109123557 A TW109123557 A TW 109123557A TW I778382 B TWI778382 B TW I778382B
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Taiwan
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wiring
layer
mentioned
thick
wiring board
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TW109123557A
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TW202137502A (zh
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佐野雄一
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日商鎧俠股份有限公司
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Abstract

本實施型態之半導體裝置具備：擁有複數配線層之多層配線基板，和被搭載於上述配線基板之第1半導體晶片，和將上述第1半導體晶片接著於上述配線基板之接著層，被形成在上述配線基板之配線具有使線寬部分性地變粗的粗寬部。

Description

半導體裝置
本發明之實施型態係關於半導體裝置。 關連申請案的引用 本申請係以2020年3月17日申請在先的日本專利申請第2020-046190號的優先權的權利為基準，且要求該權利，其整體內容通過引用而包含於此。
為了實現半導體裝置之小型化、高速化、高機能化等，在一個封裝體內疊層複數半導體晶片且予以密封之構造的半導體記憶裝置等之半導體裝置被實用化。半導體記憶裝置具備藉由FOD(Film On Device)材在例如配線基板上埋入控制器晶片並予以接著，且在FOD材上以多層之方式疊層記憶體晶片的構造。
在如此之半導體裝置中，記憶體晶片之疊層數增加。在具備被疊層多層的FOD材之半導體裝置中，有由於熱應力等使得在應力集中於FOD材的部分產生龜裂的可能性。
另一方面，在例如PCIe(Peripheral Component Interconnect Express)等之高速配線之情況，因流通頻率為例如1GHz以上之訊號，故需要阻抗控制，為了不易受到其龜裂的影響而使寬線變粗則有困難。
一個實施型態係提供即使在需要阻抗控制之高速配線之情況，亦可縮小因將半導體晶片接著於配線基板的接著層之龜裂所引起之影響的半導體裝置。
實施型態之半導體裝置具備：擁有複數配線層之多層配線基板，和被搭載於上述配線基板之第1半導體晶片；和將上述第1半導體晶片接著於上述配線基板之接著層，被形成在上述配線基板的配線具有線寬部分性地變粗的粗寬部。
若藉由上述構成時，可以提供即使在需要阻抗控制之高速配線之情況，亦可縮小因將半導體晶片接著於配線基板的接著層之龜裂所引起之影響的半導體裝置。
以下，參照實施型態所涉及的圖面而予以說明。另外，在各圖面中，有對實質相同的構成部位賦予相同的符號，省略一部分其說明之情況。圖面為示意性表示，有厚度和平面尺寸之關係、各部之厚度的比率等與現實上不同之情況。說明中表示上下等之方向的用語在無特別明確記載之情況，表示將後述的基板之半導體晶片搭載面設為上之情況的相對性方向，有與將重力加速度方向當作基準的現實方向不同之情況。
圖1係表示實施型態所涉及之半導體裝置(半導體封裝體)的剖面圖。圖1所示之半導體封裝體1具備：配線基板2；被搭載於配線基板2上之第1半導體晶片3；埋入第1半導體晶片3且接著於配線基板2之第1接著層(FOD) 4；與第1接著層4接著的被固定於不具備電極的第2半導體晶片5上的複數第3半導體晶片6之疊層體7；及以密封第1半導體晶片3或第3半導體晶片6之疊層體7等之方式被設置在配線基板2上之密封樹脂層8，第2半導體晶片5為間隔基板，雖然使用矽晶圓，但即使使用聚醯亞胺等之樹脂或玻璃等之板當作間隔基板亦可。
配線基板2係具有配線網，該配線網係由被設置在例如絕緣性樹脂基板或絕緣性陶瓷基板等之表面的配線層9或被設置在內部之配線層10等所構成，具體而言，可舉出如使用玻璃環氧樹脂般之絕緣樹脂的印刷配線板等。配線層9、10係藉由例如銅或銅合金、金或金合金等之金屬材料而被構成。配線基板2具有成為外部端子之形成面等的第1面2a，和成為半導體晶片3、5、6之搭載面的第2面2b。
在配線基板2之第2面2b上，搭載第1半導體晶片3，第1半導體晶片3被埋入至第1接著層(FOD)4內，且被接著於配線基板2之晶片搭載區域。作為第1半導體晶片3，雖然可舉出在作為例如第3半導體晶片6被使用的半導體記憶體晶片和外部機器之間進行訊號發送接收的控制器晶片或介面晶片、邏輯晶片、RF晶片等之系統LSI晶片，但是並不限定於此。
第1半導體晶片3之電極(無圖示)係經由接著引線11而與配線基板2之配線層9電性連接。藉由將控制器晶片等之第1半導體晶片3直接搭載於配線基板2上，可以縮短第1半導體晶片3和配線基板2之間的配線長。依此，能謀求提升第1半導體晶片3和配線基板2之間之訊號傳送速度等，對應半導體封裝體1之高速化。並且，因第1半導體晶片3被埋入至第1接著層4內，故不會有降低第3半導體晶片6對配線基板2之搭載性，再者妨礙封裝體尺寸之小型化等之情形。因此，能提供以小型對應於高速裝置之半導體封裝體1。
一般而言控制器晶片等之第1半導體晶片3之外形形狀小於半導體記憶體晶片等之第3半導體晶片6之外形形狀。於是，將被搭載於配線基板2上之第1半導體晶片3埋入至第1接著層4內之後，在第1接著層4上疊層且搭載複數第3半導體晶片6。作為第3半導體晶片6之具體例，雖可舉出NAND型快閃記憶體般之半導體記憶晶片，但不限定於此。在本實施型態中，4個半導體記憶晶片作為第3半導體晶片6被疊層且搭載。另外，第3半導體晶片6之疊層數不限定於4層。
被搭載於第1接著層4上之複數第2半導體晶片6之中，從第1層至第4層的第2半導體晶片6係以各者的電極露出之方式，使在第1方向(圖中，紙張右方向)配列有電極之端部錯開而被疊層階梯狀。
複數第3半導體晶片6之中，第1層之第3半導體晶片6經由不具備電極的第2半導體晶片5而被固定在第1接著層4上。第3半導體晶片6使用一般的DAF(Die Attach Film)等之接著劑，在圖1中，藉由省略圖示的DAF等之接著劑，被固定於位於下側的第3半導體晶片6。第3半導體晶片6之電極(無圖示)係經由接合引線12而與配線基板2之配線層9電性連接。關於電特性或訊號特性相等的電極墊，可以以接合引線12依順序連接配線基板2之配線層9和複數第3半導體晶片6之電極墊。即是，從第1層至第4層的第3半導體晶片6之電極係以接合引線12依順序連接，以接合引線12連接第1層之第3半導體晶片6之電極和配線基板2之配線層9。第3半導體晶片6之厚度例如30μm至100μm。
在配線基板2之第2面2b上，以將第1半導體晶片3或第3半導體晶片6之疊層體7與接合引線11、12一起密封之方式，例如模封成形使用環氧樹脂等之絕緣樹脂的密封樹脂層8。藉由該些構成要素，構成實施型態之半導體封裝體1。
接著，參照圖2針對半導體封裝體1之配線基板2之構成予以說明。圖2表示配線基板2及第1接著層4之端部附近之剖面構成。如圖2所示般，配線基板2被設為具有第1層L1、第2層L2、第3層L3、第4層L4之4層配線層的多層配線基板2。
在第1層L1形成由金屬例如銅所構成的配線21。同樣，在第2層L2形成配線22，在第3層L3形成配線23，在第4層L4形成配線24。在此，雖然在圖中符號C所示的第1接著層4之端部附近之區域，於第1層L1形成配線21，但是在第2層L2、第3層L3、第4層L4不形成配線。另外，在第1接著層4之端部附近的區域，比起端部附近以外之區域，即是第1接著層4之中央的區域等，在第1接著層4更容易產生龜裂。
圖3為表示配線基板2之配線構成的示意俯視圖。當假設重疊第1層L1至第4層L4全部的層之時，有任何金屬之配線圖案的部分以縱線表示。另外，在圖3中，為了簡化配線21，雖然僅表示兩條，但實際上設置多數。在第1層L1設置配線21和連接盤拉出部21c。配線21被連接於連接盤21b之連接盤拉出部21c。再者，在朝配線21之連接盤拉出部21c的連接端部側，設置較其他部分使線寬變粗的粗寬部21a。
針對第2層L2、第3層L3之連接盤，設置有沿著垂直方向朝連接盤拉出部21c連接的導孔24。第4層L4之連接盤21b以虛線表示。以虛線表示第1接著層4之端部的位置。以虛線為境界分為第1接著層4之內部和外部。在本實施型態中，配線21之線寬被設為例如30μm，粗寬部21a之線寬被設為例如50μm。另外，即使粗寬部21a之線寬設為例如40μm至60μm等亦可。粗寬部21a之粗寬係指考慮到使成為粗寬而進行設計者，不含由於製造上之誤差，成為例如數微米程度粗寬者。在第4層L4之連接盤21b設置用以與外部連接的焊球等。
再者，被形成在第1層L1之配線21係例如PCIe(Peripheral Component Interconnect Express)等之高速配線，流通頻率為例如1GHz以上之訊號的配線，被設為需要阻抗控制的配線。因此，配線21之線寬為了取得所需的電性能而被限制。在本實施例之情況，例如當配線21之線寬設為例如35μm時，因無法滿足所需之電性能之一部分，故如同上述，將配線21之線寬設為例如30μm。僅為一例，高速配線之線寬不限定於此。高速配線與第1半導體晶片3連接。在第1層L1另外也設置無圖示的訊號線等。在訊號線流通之訊號的頻率低於在高速配線流通之訊號的頻率。
在圖2以C表示的區域，於第2層L2、第3層L3、第4層L4不形成金屬的配線。如此一來，在圖3中以空白區域表示在第1層L1、第2層L2、第3層L3、第4層L4中之任一者中皆不形成金屬配線的區域。如圖3所示般，以包圍形成第4層L4之連接盤21b之區域之方式，在第1層L1(除了配線21之外)、第2層L2、第3層L3、第4層L4形成無配線的區域。此係依據為了抑制與連接盤21b之電容耦合等的理由。
如此一來，當注目於某一個層之時，在上下層(其他層)不形成由金屬構成的配線之部分，作為配線基板2的強度變低。因此，在被接著於配線基板2之第1接著層4產生龜裂而在此施加應力之情況等，有龜裂延伸至該部分之情況。尤其，因在第1層L1中，位於最接近第1接著層4之端部，容易直接施加其龜裂之產生所致的應力。
因此，在本實施型態中，將從在第1層L1、第2層L2、第3層、第4層L4中之任一者皆不形成配線的圖3之空白的區域內，及與在第1層L1、第2層L2、第3層L3、第4層L4之至少一層具有配線之部分重疊的部位(圖3所示之點A)起半徑200μm以內之範圍(至圖3所示之點B為止的範圍)之配線21當作粗寬部21a。另外，半徑200μm以內之範圍係表示最大之時的範圍，將彼此更窄的範圍，例如半徑100μm以內之範圍設為粗寬部21a。尤其，即使在第1接著層4容易產生龜裂之第1接著層4之端部附近以外之部位，縮窄成為粗寬部21a之範圍亦可。例如，在第1接著層4之端部附近，成為粗寬部21a的範圍為半徑200μm，即使在第1接著層4之端部附近以外之部位，例如在第1接著層4之中心部附近，為半徑100μm亦可。或是，即使在第1接著層4之端部附近以外之部位，形成粗寬部21a亦可。
換言之，配線基板2之從被形成在於上下層無配線之區域的連接盤21b之連接盤拉出部21c被拉出的配線21，成為從與在上下層具有配線之部分重疊的部位A起半徑200μm以內之範圍，設置粗寬部21a的構成。依此，在配線基板2之強度變低的部分，可以藉由粗寬部21a強化配線基板2。
另外，在與於上述上下層具有配線之部分重疊之部位A中之上下層的配線，係以在各層間之雜訊屏蔽而發揮作用的接地配線之情況為多，也包含電源配線、其他層之訊號配線等。但是，不包含被形成圓形之島狀等，而不與其他配線電性連接的浮動之金屬圖案。
即使如上述般，需要藉由在配線21之一部分設置粗寬部21a，進行PCIe等之阻抗控制的配線，亦可以確保電性能。如同上述般，在本實施型態中，當將配線21之線寬全體變粗時，則無法滿足所需的電性能之一部分。因此，無法將配線21之線寬整體變粗而強化配線基板2，基本上如同上述將配線21之線寬設為30μm。
例如，在頻率4GHz中之差動回送損失( Differential Return Loss)等，例如當配線21之線寬為30μm之時，即使在上述範圍內設置50μm之粗寬部21a亦可以確保所需的電性能。
如上述般，在本實施型態之半導體封裝體1中，即使在需要阻抗控制之高速的配線21之情況，亦可以強化配線基板2，以使將第1半導體晶片3接著於配線基板2之第1接著層(FOD)4之龜裂不伸展至配線基板2。
另外，在上述說明中，雖然針對配線基板2之第1層L1，但是即使針對第1層L1以外之層，例如第2層L2、第3層L3、第4層L4等，也同樣適用。
接著，參照圖4、圖5，說明被形成上述圓形之島狀等，而不與其他配線電性連接的浮動之金屬圖案30b、30c。如同上述般，圖3所示的空白區域內成為在其他層(圖3之情況，第1層L1(除了配線21之外)、第2層L2、第3層L3、第4層L4)不形成配線之區域。如此一來，當在一個層內具有未形成配線之比較寬的區域之時，則有在其部分產生凹部之情況。因此，有在未形成配線之其他層，例如圖4所示般，以位於空白區域內之方式，設置浮動之金屬圖案30b之情形。另外，金屬圖案30a係從第4層L4導通至第1層L1之拉出部21c。
作為一個比較例而說明的浮動之金屬圖案係以各層皆相同的圖案配置及大小被設置。對此，在本實施型態中，例如，在第2層L2配置圖4所示之圖案配列及大小的浮動之金屬圖案30b，在第2層L2以外之層，例如第3層L3或第1層L1，設置圖5所示之圖案配列及大小之浮動的金屬圖案30c。
如上述般，藉由配線基板2之不同層設置不同的圖案配列及大小之浮動的金屬圖案30b及浮動之金屬圖案30c，可以減少該些重疊之時，空白的區域內無金屬圖案的區域。藉由設為如此的構成，可以抑制在配線基板2產生強度局部性地變弱之部位之情形，可以強化配線基板2，以使將第1半導體晶片3接著於配線基板2之第1接著層(FOD)4之龜裂伸展至配線基板2。
再者，作為一個比較例，在圖6表示從不具有浮動圖案之情況之第1層L1至第4層L4之連接盤部的實施型態。斜線或縱線表示金屬之配線圖案。在第4層L4之連接盤之周圍無法設置金屬圖案。從第4層L4至第1層L1經由導孔被連接。在第1層L1、第2層L2、第3層L3中，無法設置金屬之配線的部分大。若為如此之構成時，則有配線基板2之強度變弱之情形。
以上，雖然說明本發明之幾個實施型態，但是該些實施型態透過舉例之方式來表呈現，並無限定發明之範圍的意圖。該些新增實施型態可以其他各種型態來實施，只要在不脫離發明之要旨的範圍下，可做各種省略、置換及變更。該些實施型態或其變形當然也包含在發明範圍或主旨中，並且包含於申請專利範圍所記載之發明和其均等之範圍中。
1:半導體封裝體 2:配線基板 2a:第1面 2b:第2面 3:第1半導體晶片 4:第1接著層 5:第2半導體晶片 6:第3半導體晶片 7:疊層體 8:密封樹脂層 9:配線層 10:配線層 11:接合引線 12:接合引線 21:配線 21a:粗寬部 21b:連接盤 21c:連接盤拉出部 22:配線 23:配線 24:配線 30a:金屬圖案 30b:金屬圖案 30c:金屬圖案 L1:第1層 L2:第2層 L3:第3層 L4:第4層
[圖1] 係表示實施型態所涉及的半導體裝置之構成的剖面圖。 [圖2] 係表示實施型態所涉及的配線基板之重要部位構成的剖面圖。 [圖3] 係表示實施型態所涉及的配線基板之重要部位構成的俯視圖。 [圖4] 係表示實施型態所涉及的配線基板之重要部位構成的俯視圖。 [圖5] 係表示實施型態所涉及的配線基板之重要部位構成的俯視圖。 [圖6] 係表示不具有浮動圖案之情況的連接盤部之構成例的圖。
1:半導體封裝體
2:配線基板
2a:第1面
2b:第2面
3:第1半導體晶片
4:第1接著層
5:第2半導體晶片
6:第3半導體晶片
7:疊層體
8:密封樹脂層
9:配線層
10:配線層
11:接合引線
12:接合引線

Claims (8)

  1. 一種半導體裝置，其具備：多層的配線基板，其具有複數配線層；第1半導體晶片，其係被搭載在上述配線基板；及接著層，其係將上述第1半導體晶片接著於上述配線基板，被形成在上述配線基板之配線具有使線寬部分性地變粗的粗寬部，從與連接於外部之連接盤連接的連接盤拉出部被拉出的上述配線，在上述配線層之全層通過不存在上述配線以外之金屬配線的區域，將與在上述配線層之至少1層存在上述配線以外之金屬配線之部分重疊的部位設為重疊部之時，在從上述重疊部起半徑200μm以內之範圍，設置上述粗寬部。
  2. 如請求項1之半導體裝置，其中從與連接於外部之連接盤連接的連接盤拉出部被拉出的上述配線，在上述配線層之全層通過不存在上述配線以外之金屬配線的區域，將與在上述配線層之至少1層存在上述配線以外之金屬配線之部分重疊的部位設為重疊部之時，將在上述接著層之端部附近從上述重疊部起設置上述粗寬部的範圍設為第1範圍，將在上述接著層之中心部從上述重疊部設置上述粗寬部的範圍設為第2範圍之時，上述第1範圍大於上述第2範圍。
  3. 如請求項1之半導體裝置，其中 上述粗寬部從垂直於上述配線基板之表面的方向觀看，僅被設置在上述接著層之端部附近。
  4. 一種半導體裝置，其具備：多層的配線基板，其具有複數配線層；第1半導體晶片，其係被搭載在上述配線基板；及接著層，其係將上述第1半導體晶片接著於上述配線基板，被形成在上述配線基板之配線具有使線寬部分性地變粗的粗寬部，從與連接於外部之連接盤連接的連接盤拉出部被拉出的上述配線，在上述配線層之全層通過不存在上述配線以外之金屬配線的區域，將與在上述配線層之至少1層存在上述配線以外之金屬配線之部分重疊的部位設為重疊部之時，在從上述重疊部起半徑200μm以內之範圍，設置上述粗寬部，從與連接於外部之連接盤連接的連接盤拉出部被拉出的上述配線，在上述配線層之全層通過不存在上述配線以外之金屬配線的區域，將與在上述配線層之至少1層存在上述配線以外之金屬配線之部分重疊的部位設為重疊部之時，將在上述接著層之端部附近從上述重疊部起設置上述粗寬部的範圍設為第1範圍，將在上述接著層之中心部從上述重疊部設置上述粗寬部的範圍設為第2範圍之時，上述第1範圍大於上述第2範圍，上述粗寬部從垂直於上述配線基板之表面的方向觀 看，僅被設置在上述接著層之端部附近。
  5. 如請求項1至4中之任一項之半導體裝置，其中具有上述粗寬部的上述配線係需要流通1GHz以上之訊號的阻抗控制的高速配線。
  6. 如請求項1至4中之任一項之半導體裝置，其中具備浮動之金屬圖案，其係被設置在較上述配線基板之形成有連接盤的層更上層，從垂直於上述配線基板之表面的方向觀看與上述連接盤重疊，上述金屬圖案具有在至少兩層不同的圖案。
  7. 如請求項1至4中之任一項之半導體裝置，其中上述粗寬部之線寬係40μm以上60μm以下。
  8. 如請求項1至4中之任一項之半導體裝置，其中上述配線之線寬係30μm以上35μm未滿。
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