CN116613133A - 电子封装件及其基板结构 - Google Patents
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Abstract
本发明涉及一种电子封装件及其基板结构,包括基板结构以及设于该基板结构上的电子元件,该基板结构于其基板本体表面上布设有多个线路及未电性导通该多个线路的强化部,以令该电子元件电性连接该多个线路而未电性连接该强化部,且该强化部包含虚垫与连接该虚垫的迹线,以增加该强化部于该基板本体的布设面积,故不仅可提升该强化部的附着度,且可避免该电子元件碎裂。
Description
技术领域
本发明有关一种半导体装置,尤指一种可提高生产良率的电子封装件及其基板结构。
背景技术
于半导体封装发展中,早期多使用导线架(lead frame)作为承载主动元件的承载件,其主要原因在于其具有较低制造成本与较高可靠度的优点。然而,随着电子产业的蓬勃发展,电子产品在型态上趋于轻薄短小,在功能上则朝高性能、高功能、高速化的研发方向。因此,为满足半导体装置的高集成度(Integration)及微型化(Miniaturization)需求,现阶段封装制程渐以具有高密度及细间距的线路的封装基板取代导线架。
如图1所示,传统封装基板1包括一基板本体10及多个设于该基板本体10上的强化部11,且经由该强化部11增加该封装基板1的整体结构强度。所述的基板本体10具有多个布线层(图略),且各层布线层之间经由多个导电盲孔(图略)相互电性连接。所述的强化部11为不具电性功能的虚垫(dummy pad)结构,即其并未电性连接该布线层。
然而,现有封装基板1中,由于该强化部11仅为虚垫结构,致使其与该基板本体10最外层表面的接触面积极小,导致该强化部11与该基板本体10的附着度不佳,因而容易造成该强化部11脱落。
再者,由于该强化部11与该基板本体10最外层表面的接触面积有限,故于后续该封装基板1于置晶区A上承载半导体芯片时,该封装基板1难以分散该半导体芯片的应力,因而容易造成该半导体芯片碎裂。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷,本发明提供一种电子封装件及其基板结构,不仅可提升该强化部的附着度,且可避免该电子元件碎裂。
本发明的基板结构,包括:基板本体,其于表面上布设有多个线路;以及强化部,其设于该基板本体的表面上且未电性导通该多个线路,且该强化部包含至少一虚垫与连接该至少一虚垫的至少一迹线。
本发明还提供一种电子封装件,包括:前述的基板结构;以及电子元件,其设于该基板本体的表面上且电性连接该多个线路而未电性连接该强化部。
前述的电子封装件中,该电子元件为半导体芯片。
前述的电子封装件及其基板结构中,该基板本体的表面定义有一置晶区及一环绕于该置晶区周围的布设区,以令该电子元件设于该置晶区上。例如,该至少一虚垫配置于该置晶区的角落处。或者,该强化部布设于该基板本体的表面的置晶区上的面积大于3500平方微米。
前述的电子封装件及其基板结构中,该强化部为金属材料。
前述的电子封装件及其基板结构中,该至少一迹线为直线状。
前述的电子封装件及其基板结构中,该至少一迹线具有至少一弯曲线段。例如,该至少一弯曲线段为弧形或波浪形;或者,该至少一弯曲线段的相对两端的直线距离为15微米;亦或,该至少一弯曲线段为直线夹角弯折状。
前述的电子封装件及其基板结构中,该强化部布设于该基板本体的表面上的面积大于3500平方微米。
由上可知,本发明的电子封装件及其基板结构中,主要经由该迹线的设计,以增加该强化部的布设面积,不仅可提升该强化部的附着度,且可避免该电子元件碎裂,故相比于现有技术,本发明的电子封装件及其基板结构能有效提高生产良率。
附图说明
图1为现有封装基板的上视示意图。
图2A为本发明的基板结构的上视示意图。
图2B为图2A的另一实施例的上视示意图。
图3为图2A的另一实施例的局部上视示意图。
图4为本发明的电子封装件的剖面示意图。
附图标记说明
1:封装基板
10,20:基板本体
11,2a:强化部
2:基板结构
20a:表面
200:线路
201:电性接触垫
202:导电盲孔
21:虚垫
22,32:迹线
220,320:弯曲线段
23:绝缘保护层
230:开口
4:电子封装件
40:电子元件
400:导电凸块
A:置晶区
B:布设区
L:直线距离。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、及“一”等的用语,亦仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2A为本发明的基板结构2的上视示意图。如图2A所示,该基板结构2例如为用以承载半导体芯片的封装基板(substrate),其包括一基板本体20、以及至少一设于该基板本体20上的强化部2a,其中,该强化部2a包含至少一虚垫(dummy pad)21与至少一连接该虚垫21的迹线22。
所述的基板本体20例如为具有核心层(core)的线路结构或无核心层(coreless)的线路结构,其于至少一绝缘层上形成至少一布线层,如扇出(fan out)型重布布线层(redistribution layer,简称RDL),并于最外层的布线层包含有多个线路200及结合于该线路200端处的电性接触垫201,且各层布线层之间经由多个导电盲孔202相互电性连接。
于本实施例中,该基板本体20于最外层的表面20a上定义有一置晶区A及一环绕于该置晶区A周围的布设区B,以令该布线层配置于该置晶区A与该布设区B上,且该置晶区A用以配置如半导体芯片或被动元件的电子元件40,以形成如图4所示的电子封装件4。于本实施例中,该基板本体20为矩形体,且该置晶区A为矩形区域。
再者,该电子元件40若为半导体芯片,其可经由多个如焊锡材料的导电凸块400以覆晶方式设于该电性接触垫201上并电性连接该线路200;或者,可经由多个焊线(图略)以打线方式电性连接该线路200。然而,有关该电子元件40电性连接该布线层的方式不限于上述。
另外,形成各该布线层的材料为铜,且各该绝缘层为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材、或如绿漆、油墨等的防焊材。
所述的强化部2a配置于该置晶区A上且未电性导通该基板本体20的布线层,故于该基板结构2的后续应用中,该电子元件40未电性连接该强化部2a。
于本实施例中,该虚垫21为如铜垫的金属垫,其配置于该置晶区A上,较佳为配置于该置晶区A的角落处(可对应到芯片应力最大的四个角落),并可经由与该迹线22的连接,以防止应力过大而造成该虚垫21脱落。
再者,该迹线22为如铜线的金属线,其配置于该置晶区A上并可依需求延伸至该布设区B。例如,该迹线22可具有至少一弯曲线段220,且该弯曲线段220可为弧形或波浪形,以令该弯曲线段220的相对两端的直线距离L为15微米(um)。较佳地,单一迹线22具有两个弯曲线段220。应可理解地,如图3所示,连接虚垫21的迹线32亦可为直线状,且弯曲线段320亦可为直线夹角弯折状,最佳夹角角度为小于45度,可避免断线问题。
另外,该强化部2a(该虚垫21与该迹线22)布设于该基板本体20的最外层的表面20a上的面积大于等于3500平方微米(um2),且若使单一迹线22具有两个弯曲线段220,则该强化部2a布设于该基板本体20的最外层的表面20a上的面积易于大于等于3500平方微米(um2)。应可理解地,该面积并不包含最外层的布线层的金属面积。
另外,若该基板本体20的最外层的表面20a上形成有一绝缘保护层23,如图2B所示的防焊层,且该绝缘保护层23具有一外露该置晶区A的开口230,则该强化部2a(该虚垫21与该迹线22)布设于该基板本体20的最外层的表面20a的置晶区A上的面积大于等于3500平方微米,即该强化部2a外露于该开口230的面积(并不包含该强化部2a于该布设区B或绝缘保护层23处的面积)大于等于3500平方微米且若使单一迹线22具有两个弯曲线段220,则该强化部2a布设于该基板本体20的最外层的表面20a的置晶区A上的面积易于大于等于3500平方微米(um2)。
因此,本发明的基板结构2主要经由该迹线22连接该虚垫21的设计,以增加该强化部2a与该基板本体20的绝缘层的接触面积,故相比于现有技术,本发明的基板结构2能提升该强化部2a与该基板本体20的附着度,以避免该虚垫21脱层。
再者,经由该迹线22的设计,以增加该基板本体20的绝缘层上的金属面积,因而能分散该电子元件40的应力,故相比于现有技术,本发明的基板结构2于承载该电子元件40后能避免该电子元件40碎裂。
综上所述,本发明的电子封装件及其基板结构,经由该迹线的设计,以增加该强化部的布设面积,不仅能提升该强化部的附着度,且能避免该电子元件碎裂,故本发明的电子封装件及其基板结构能有效提高生产良率。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (20)
1.一种基板结构,包括:
基板本体,其于表面上布设有多个线路;以及
强化部,其设于该基板本体的表面上且未电性导通该多个线路,其中,该强化部包含至少一虚垫与连接该至少一虚垫的至少一迹线。
2.如权利要求1所述的基板结构,其中,该基板本体的表面定义有一置晶区及一环绕于该置晶区周围的布设区。
3.如权利要求2所述的基板结构,其中,该至少一虚垫配置于该置晶区的角落处。
4.如权利要求2所述的基板结构,其中,该强化部布设于该基板本体的表面的置晶区上的面积大于等于3500平方微米。
5.如权利要求1所述的基板结构,其中,该强化部为金属材料。
6.如权利要求1所述的基板结构,其中,该至少一迹线为直线状。
7.如权利要求1所述的基板结构,其中,该至少一迹线具有至少一弯曲线段。
8.如权利要求7所述的基板结构,其中,该至少一弯曲线段为弧形、波浪形或直线夹角弯折状。
9.如权利要求7所述的基板结构,其中,该至少一弯曲线段的相对两端的直线距离为15微米。
10.如权利要求1所述的基板结构,其中,该强化部布设于该基板本体的表面上的面积大于等于3500平方微米。
11.一种电子封装件,包括:
如权利要求1所述的基板结构;以及
电子元件,其设于该基板本体的表面上且电性连接该多个线路而未电性连接该强化部。
12.如权利要求11所述的电子封装件,其中,该基板本体的表面定义有一置晶区及一环绕于该置晶区周围的布设区,以令该电子元件设于该置晶区上。
13.如权利要求12所述的电子封装件,其中,该至少一虚垫配置于该置晶区的角落处。
14.如权利要求12所述的电子封装件,其中,该强化部布设于该基板本体的表面的置晶区上的面积大于等于3500平方微米。
15.如权利要求11所述的电子封装件,其中,该强化部为金属材料。
16.如权利要求11所述的电子封装件,其中,该至少一迹线为直线状。
17.如权利要求11所述的电子封装件,其中,该至少一迹线具有至少一弯曲线段。
18.如权利要求17所述的电子封装件,其中,该至少一弯曲线段为弧形、波浪形或直线夹角弯折状。
19.如权利要求17所述的电子封装件,其中,该至少一弯曲线段的相对两端的直线距离为15微米。
20.如权利要求11所述的电子封装件,其中,该强化部布设于该基板本体的表面上的面积大于等于3500平方微米。
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