JP2008109094A - 素子搭載用基板および半導体モジュール - Google Patents
素子搭載用基板および半導体モジュール Download PDFInfo
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Abstract
【解決手段】素子搭載用基板は、配線層8と、導電層2と導電層3に設けられ、互いに対向して平行に配置された信号配線2a,3aと、配線層8の上面側に設けられた一対のパッド電極5a,5bと、配線層8の下面側に設けられた一対のパッド電極7a,7bと、各絶縁層を貫通して設けられ、上下の導電層間を電気的に接続する導体部1b,4b,6bと、配線層8の上面側に搭載された回路素子9と、この回路素子9に設けられ、一対のパッド電極5a,5bと導電部材10a,10bを介して接続された一対の信号電極9a,9bと、を備え、パッド電極5aから信号配線2aを介したパッド電極7aまでの線路と、パッド電極5bから信号配線3aを介したパッド電極7bまでの線路とにより等長な一対の差動伝送線路が構成される。
【選択図】図2
Description
図1は本発明の第1の実施形態に係る素子搭載用基板および半導体モジュールの構成を示す平面図である。図2(A)は図1中のX−X線に沿った素子搭載用基板および半導体モジュールの断面図であり、図2(B)は図1中のY−Y線に沿った素子搭載用基板および半導体モジュールの断面図である。
(1)配線層8内において信号配線2a,3aを互いに対向して平行に積層配置した状態で、素子搭載用基板のパッド電極5a,5bとパッド電極7a,7bとの間におけるこうした信号配線2a,3aを介した2つの線路を、一対の等長な差動伝送線路とすることが可能となる。これは、パッド電極5aから信号配線2aに至る線路長とパッド電極5bから信号配線3aに至る線路長との差(導体部1bの深さに相当)が、信号配線2aからパッド電極7aに至る線路と信号配線3aからパッド電極7bに至る線路長との差によって相殺されることによる。このため、差動インピーダンスの不整合を抑制することができるので、所定の信号を正確に伝送させ、搭載される回路素子を正常に作動させることが可能な素子搭載用基板とすることができる。
(2)信号配線2a,3aを互いに対向して平行に積層配置したことで、信号配線を同一平面で平行に配置する場合に比べて信号配線の占有面積を削減できるので、こうした信号配線を有する素子搭載用基板の小型化を実現することが可能となる。
(3)回路素子9の一対の信号電極9a,9bを一対のパッド電極5a,5bにそれぞれ電気的に接続し、一対のパッド電極7a,7bを回路素子9の信号を外部に伝送するための外部引出電極として機能させたことで、素子搭載用基板に搭載された回路素子9からの所定の信号を外部に正確に、且つ、高速に伝送させることができる。
図3は本発明の第2の実施形態に係る素子搭載用基板および半導体モジュールの構成を示す平面図である。図4(A)は図3中のX−X線に沿った素子搭載用基板および半導体モジュールの断面図であり、図4(B)は図3中のY−Y線に沿った素子搭載用基板および半導体モジュールの断面図である。
図5は本発明の第3の実施形態に係る素子搭載用基板および半導体モジュールの構成を示す平面図である。図6(A)は図5中のX−X線に沿った素子搭載用基板および半導体モジュールの断面図であり、図6(B)は図5中のY−Y線に沿った素子搭載用基板および半導体モジュールの断面図である。
本実施形態では、上述の各実施形態で説明した半導体モジュールをマザーボードにはめ込んで実装する方法について説明する。図7は、第4の実施形態に係るマザーボードへの半導体モジュールの実装状態を示した模式図である。マザーボード440は、電子装置を構成するための複数の部品を積載可能に構成されている電子回路基板である。本実施形態に係るマザーボード440は、積載される半導体モジュール450が備える素子搭載用基板400の一方の面に設けられている回路素子411と干渉しないように貫通孔420が形成されている。
本実施形態では、上述の各実施形態で説明した半導体モジュールをマザーボードに垂直に実装する方法について説明する。図8は、第5の実施形態に係るマザーボードへの半導体モジュールの実装状態を示した模式図である。本実施形態に係るマザーボード540は、実装される半導体モジュール550の端部が挿入され固定されるように構成されている挿入口520が形成されている。半導体モジュール550は、挿入口520に挿入された状態で端部に設けられている外部接続端子522がマザーボード540に形成されている不図示の電極と接触し、固定される。
Claims (5)
- 導電層と絶縁層とが交互に複数積層された配線層と、
前記配線層の一方の主面に設けられた一対の第1の電極と、
前記配線層内の異なる導電層に設けられ、互いに対向して平行に配置された信号配線と、
前記配線層の他方の主面に設けられた一対の第2の電極と、
前記絶縁層を貫通して設けられ、前記第1の電極と前記信号配線との間および前記信号配線と前記第2の電極との間をそれぞれ電気的に接続する導体部と、
を備え、
前記第1の電極の一方から前記第2の電極の一方までの第1の線路と、前記第1の電極の他方から前記第2の電極の他方までの第2の線路とにより、等長な一対の差動伝送線路が構成されている素子搭載用基板。 - 前記第1の線路における前記導体部は、一方の主面から他方の主面に向かって絶縁層に一つずつ設けられており、前記第2の線路における前記導体部は、一方の主面から他方の主面に向かって絶縁層に一つずつ設けられていることを特徴とする請求項1に記載の素子搭載用基板。
- 導電層と絶縁層とが交互に複数積層された配線層と、
前記配線層の一方の主面に設けられた一対の第1の電極と、
前記配線層内の異なる導電層に設けられ、互いに対向して平行に配置された一対の信号配線と、
前記配線層の他方の主面に設けられた一対の第2の電極と、
前記絶縁層を貫通して設けられ、前記一対の第1の電極の一方と前記一対の信号配線の一方との間を電気的に接続する第1の導体部と、
前記絶縁層を貫通して設けられ、前記一対の信号配線の一方と前記一対の第2の電極の一方との間を電気的に接続する第2の導体部と、
前記絶縁層を貫通して設けられ、前記一対の第1の電極の他方と前記一対の信号配線の他方との間を電気的に接続する第3の導体部と、
前記絶縁層を貫通して設けられ、前記一対の信号配線の他方と前記一対の第2の電極の他方との間を電気的に接続する第4の導体部と、
を備え、
前記一対の信号配線の一方が配置された導電層における前記一対の信号配線の一方を含む配線長と、前記一対の信号配線の他方が配置された導電層における前記一対の信号配線の他方を含む配線長とが等しく、
配線層の主面と垂直な方向における前記第1の導体部と前記第2の導体部との長さの和が、配線層の主面と垂直な方向における前記第3の導体部と前記第4の導体部との長さの和と等しく、
前記第1の電極の一方から前記第2の電極の一方までの第1の線路と、前記第1の電極の他方から前記第2の電極の他方までの第2の線路とにより、等長な一対の差動伝送線路が構成されている素子搭載用基板。 - 請求項1乃至3のいずれかに記載の素子搭載用基板と、
前記素子搭載用基板の前記配線層の一方の主面に設けられた回路素子とを備え、
前記一対の第1の電極に前記回路素子の一対の信号電極がそれぞれ電気的に接続され、前記一対の第2の電極が外部引出電極として機能することを特徴とする半導体モジュール。 - 請求項1乃至3のいずれかに記載の素子搭載用基板と、
前記素子搭載用基板の前記配線層の一方の主面に設けられた第1の回路素子と、
前記素子搭載用基板の前記配線層の他方の主面に設けられた第2の回路素子を備え、
前記一対の第1の電極に前記第1の回路素子の一対の信号電極がそれぞれ電気的に接続され、前記一対の第2の電極に前記第2の回路素子の一対の信号電極がそれぞれ電気的に接続されていることを特徴とする半導体モジュール。
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