JP6325605B2 - 電子部品内蔵基板 - Google Patents
電子部品内蔵基板 Download PDFInfo
- Publication number
- JP6325605B2 JP6325605B2 JP2016128797A JP2016128797A JP6325605B2 JP 6325605 B2 JP6325605 B2 JP 6325605B2 JP 2016128797 A JP2016128797 A JP 2016128797A JP 2016128797 A JP2016128797 A JP 2016128797A JP 6325605 B2 JP6325605 B2 JP 6325605B2
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- electronic component
- wiring
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- insulating
- layer
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- 229910000679 solder Inorganic materials 0.000 claims description 43
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- 239000011810 insulating material Substances 0.000 description 7
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- 230000008054 signal transmission Effects 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- 229910052802 copper Inorganic materials 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
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- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
Description
第1の配線層L1は、電子部品10を基準に第1の外部端子11の各々から遠くなる方向に設けられ、第1の配線及び第1の絶縁部を有する。第1の配線層L1は、第1の外部端子11を基板の内部、または外部の他のデバイスと電気的に接続される。
10 電子部品
11 第1の外部端子
12 第2の外部端子
20、21、22 チップ部品
110 絶縁基板
111 接着部材
112 第1の金属パターン
120 第1の絶縁層
122 キャビティ
125 第5の絶縁層
132 第2の絶縁層
133 第3の絶縁層
134 第4の絶縁層
WP1 第1の配線パターン
WP2 第2の配線パターン
WP3 第3の配線パターン
WP4 第4の配線パターン
CP1 第1の接触パッド
CP2 第2の接触パッド
SR1 第1のソルダレジスト
SR2 第2のソルダレジスト
SB1 第1のソルダボール
SB2 第2のソルダボール
SB3 第3のソルダボール
O1 第1の開口部
O2 第2の開口部
L1 第1の配線層
L2 第2の配線層
VT スルービア
DC ディタッチコア
TSV スルーシリコーンビア
Claims (7)
- 第1の絶縁層と、
前記第1の絶縁層の一面に形成された第5の絶縁層と、
前記第1の絶縁層及び前記第5絶縁層を貫いて形成されたキャビティに内蔵され、外部端子が設けられた第1の面と対向する第2の面を備える電子部品と、
前記第1の絶縁層と前記第5の絶縁層との間に形成され、前記電子部品の前記第1の面から延長した面と前記第2の面から延長した面との間に配置される第4の配線パターンと、
前記第1の絶縁層の他面に積層され、第1の配線及び第1の絶縁部を備える第1の配線層と、を含み、
前記外部端子は、前記第1の配線層に向き、
前記外部端子と前記第4の配線パターンは、前記第1の配線に接続され、
前記電子部品の前記第2の面に形成された接着部材と、
前記接着部材及び第5の絶縁層上に積層される絶縁基板とをさらに含み、
前記絶縁基板に第1の開口部が形成され、
前記接着部材と前記絶縁基板との間に第1の金属パターンが設けられ、
前記第1の開口部は、第1の金属パターンを前記絶縁基板の外部に露出させる電子部品内蔵基板。 - 前記電子部品の前記第2の面上に形成され、第2の配線及び第2の絶縁部を含む第2の配線層をさらに含む請求項1に記載の電子部品内蔵基板。
- 前記第1の配線層の層数は、前記第2の配線層の層数より大きく、
前記第1の配線層の配線密度は、前記第2の配線層の配線密度より高い請求項2に記載の電子部品内蔵基板。 - 前記第2の配線層上に設けられ、前記第2の配線層と接続されるチップ部品をさらに含む請求項2に記載の電子部品内蔵基板。
- 前記第2の配線層の外層には、前記チップ部品が設けられ、
前記第2の配線と前記チップ部品とを電気的に接続させる第2の接触パッドが設けられる請求項4に記載の電子部品内蔵基板。 - 前記第1の絶縁層は、コア基板であることを特徴とする請求項1から請求項5のいずれか1項に記載の電子部品内蔵基板。
- 前記第2の接触パッドと前記チップ部品とを電気的に接続するソルダボールをさらに含む請求項5に記載の電子部品内蔵基板。
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