CN113410212B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113410212B
CN113410212B CN202010771722.2A CN202010771722A CN113410212B CN 113410212 B CN113410212 B CN 113410212B CN 202010771722 A CN202010771722 A CN 202010771722A CN 113410212 B CN113410212 B CN 113410212B
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wiring
layer
wiring board
semiconductor device
semiconductor
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CN113410212A (zh
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佐野雄一
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Kioxia Corp
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Kioxia Corp
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Abstract

本实施方式的半导体装置具备：多层的配线基板，具有多个配线层；第一半导体芯片，安装于所述配线基板；以及粘接层，将所述第一半导体芯片粘接于所述配线基板，在所述配线基板形成的配线具有部分地加粗线宽的宽幅部。

Description

半导体装置
本申请以在2020年03月17日提出申请的第2020－046190号在先日本专利申请为基础并对其主张优先权，并且引用该原专利申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
为了实现半导体装置的小型化、高速化、高功能化等，将多个半导体芯片层叠并密封在一个封装体内的构造的半导体存储装置等半导体装置得到实际应用。半导体存储装置具有这样的构造，例如在配线基板上通过FOD(Film On Device，设备上薄膜)材料埋设控制器芯片并粘接，在FOD材料上层叠多段存储器芯片。
对于这样的半导体装置，存储器芯片的层叠数量增加。具备层叠有多段的FOD材料的半导体装置有可能由于热应力等而在FOD材料的应力集中的部分产生龟裂。
另一方面，例如对于PCIe(Peripheral Component Interconnect Express，周边装置互连高速)等高速配线的情况，为了对频率例如1GHz以上的信号进行传输而需要阻抗控制，难以为了使其不易受到该龟裂的影响而加粗线宽。
发明内容
一个实施方式提供一种半导体装置，即使是需要阻抗控制的高速配线的情况，也能够减小因将半导体芯片粘接于配线基板的粘接层的龟裂导致的影响。
实施方式的半导体装置具备：多层的配线基板，具有多个配线层；第一半导体芯片，安装于所述配线基板；以及粘接层，将所述第一半导体芯片粘接于所述配线基板，在所述配线基板形成的配线具有部分地加粗线宽的宽幅部。
根据上述的结构，能够提供一种半导体装置，即使是需要阻抗控制的高速配线的情况，也能够减小因将半导体芯片粘接于配线基板的粘接层的龟裂导致的影响。
附图说明
图1是表示有关实施方式的半导体装置的结构的剖面图。
图2是表示有关实施方式的配线基板的主要部分结构的剖面图。
图3是表示有关实施方式的配线基板的主要部分结构的俯视图。
图4是表示有关实施方式的配线基板的主要部分结构的俯视图。
图5是表示有关实施方式的配线基板的主要部分结构的俯视图。
图6是表示不具有浮置图案的情况下的焊盘部的结构例的图。
具体实施方式
下面，参照有关实施方式的附图进行说明。另外，在各附图中对实质上相同的结构部位标注相同的标号，有时省略部分说明。附图是示意性的图，有时厚度和平面尺寸的关系、各部分的厚度的比率等与实际状况不同。说明中的上下等表示方向的用语，在没有特别说明的情况下，表示将后述的基板的半导体芯片安装面作为上的相对方向，存在与以重力加速度方向为基准的现实方向不同的情况。
图1是表示有关实施方式的半导体装置(半导体封装体)的剖面图。图1所示的半导体封装体1具备：配线基板2；第一半导体芯片3，安装于配线基板2上；第一粘接层(FOD)4，埋设第一半导体芯片3，并粘接于配线基板2；多个第三半导体芯片6构成的层叠体7，与第一粘接层4粘接，并固定于不具备电极的第二半导体芯片5上；以及密封树脂层8，设置于配线基板2上，将第一半导体芯片3和第三半导体芯片6构成的层叠体7等密封。第二半导体芯片5是垫片基板，使用硅晶片，另外也可以使用聚酰亚胺等树脂和玻璃等的板作为垫片基板。
配线基板2具有配线网，配线网由在例如绝缘性树脂基板或绝缘性陶瓷基板等的表面设置的配线层9和在内部设置的配线层10等构成，具体地，可以举出使用诸如玻璃环氧树脂那样的绝缘树脂的印刷配线板等。配线层9、10例如由铜或铜合金、金或金合金等金属材料构成。配线基板2具有成为外部端子的形成面等的第一面2a、和成为半导体芯片3、5、6的安装面的第二面2b。
在配线基板2的第二面2b上安装有第一半导体芯片3，第一半导体芯片3埋设在第一粘接层(FOD)4内，并且粘接于配线基板2的芯片安装区域。作为第一半导体芯片3，例如可以举出在作为第三半导体芯片6使用的半导体存储器芯片和外部设备之间发送及接收数字信号的控制器芯片和接口芯片、逻辑芯片、RF芯片等系统LSI芯片，但不限于此。
第一半导体芯片3的电极(未图示)经由键合线11与配线基板2的配线层9电连接。通过将控制器芯片等第一半导体芯片3直接安装于配线基板2上，能够缩短第一半导体芯片3和配线基板2之间的配线长度。由此，实现第一半导体芯片3和配线基板2之间的信号传输速度的提高等，能够对应半导体封装体1的高速化。另外，第一半导体芯片3埋设在第一粘接层4内，因而不会降低第三半导体芯片6对于配线基板2的安装性，而且不会妨碍封装体尺寸的小型化等。因此，能够提供小型且对应高速装置的半导体封装体1。
控制器芯片等第一半导体芯片3的外形形状通常比半导体存储器芯片等第三半导体芯片6的外形形状小。因此，在将安装于配线基板2上的第一半导体芯片3埋设在第一粘接层4内后，在第一粘接层4上层叠安装多个第三半导体芯片6。作为第三半导体芯片6的具体例，可以举出诸如NAND型闪存那样的半导体存储器芯片，但不限于此。在本实施方式中，层叠安装有4个半导体存储器芯片作为第三半导体芯片6。另外，第三半导体芯片6的层叠数量不限于4段。
安装于第一粘接层4上的多个第三半导体芯片6中第一段到第四段的第三半导体芯片6，分别以露出电极的方式将沿第一方向(在图中指纸面右侧方向)排列有电极的端部错开地层叠成阶梯状。
多个第三半导体芯片6中第一段的第三半导体芯片6，经由不具备电极的第二半导体芯片5固定于第一粘接层4上。第三半导体芯片6使用普通的DAF(Die Attach Film，芯片粘接膜)等粘接剂，通过在图1中省略图示的DAF等粘接剂固定于位于下侧的第三半导体芯片6。第三半导体芯片6的电极(未图示)经由键合线12与配线基板2的配线层9电连接。关于电气特性和信号特性相同的电极焊盘，能够用键合线12按顺序连接配线基板2的配线层9和多个第三半导体芯片6的电极焊盘。即，从第一段到第四段的第三半导体芯片6的电极用键合线12按顺序连接，用键合线12将第一段的第三半导体芯片6的电极和配线基板2的配线层9连接。第三半导体芯片6的厚度例如是30μm～100μm。
在配线基板2的第二面2b上，例如使用环氧树脂等绝缘树脂模塑成型有密封树脂层8，将第一半导体芯片3、第三半导体芯片6构成的层叠体7与键合线11、12共同密封。通过这些结构要素构成实施方式的半导体封装体1。
下面，参照图2对半导体封装体1的配线基板2的结构进行说明。图2表示配线基板2及第一粘接层4的端部附近的截面结构。如图2所示，配线基板2形成为具有第一层L1、第二层L2、第三层L3、第四层L4的四层配线层的多层配线基板2。
在第一层L1形成有由金属例如铜构成的配线21。同样地，在第二层L2形成有配线22，在第三层L3形成有配线23，在第四层L4形成有配线24。其中，在图中用符号C表示的第一粘接层4的端部附近的区域中，在第一层L1形成有配线21，但在第二层L2、第三层L3、第四层L4没有形成配线。另外，在第一粘接层4的端部附近的区域中，与端部附近以外的区域即第一粘接层4的中央的区域等相比，在第一粘接层4容易产生龟裂。
图3是表示配线基板2的配线结构的示意俯视图。在假设已将第一层L1～第四层L4为止的层全部重叠时，存在某种金属的配线图案的部分用纵线表示。另外，在图3中为了简化仅示出了两条配线21，但实际上设置有多条。在第一层L1设置有配线21和焊盘引出部21c。配线21与焊盘21b的焊盘引出部21c连接。并且，在配线21的与焊盘引出部21c的连接端部侧设置有相比其他部分加粗线宽的宽幅部21a。
关于第二层L2、第三层L3的焊盘，设置有与焊盘引出部21c沿着垂直方向连接的通孔24。第四层L4的焊盘21b用虚线表示。第一粘接层4的端部的位置用虚线表示。以虚线为边界，划分为第一粘接层4的内部和外部。在本实施方式中，配线21的线宽设为例如30μm，宽幅部21a的线宽设为例如50μm。另外，宽幅部21a的线宽还可以设为例如40μm至60μm等。宽幅部21a的宽幅是指有意识地设计成宽幅，不包括由于制造上的误差等而形成为例如约数微米的宽幅。在第四层L4的焊盘21b设置有与外部进行连接用的焊锡珠等。
另外，在第一层L1形成的配线21例如是PCIe(Peripheral ComponentInterconnect Express，周边装置互连高速)等高速配线，是对频率例如1GHz以上的信号进行传输的配线，是需要阻抗控制的配线。因此，为了获得所需要的电气性能而限制配线21的线宽。在本实施例中，例如在配线21的线宽为例如35μm时，不能满足所需要的电气性能的一部分，因而如上所述将配线21的线宽设为例如30μm。这是一例，高速配线的线宽不限于此。高速配线与第一半导体芯片3连接。在第一层L1还设置有其他未图示的信号线等。在信号线中传输的信号的频率比在高速配线中传输的信号的频率低。
在图2中用C表示的区域中，在第二层L2、第三层L3、第四层L4没有形成金属的配线。这样，在图3中，将在第一层L1、第二层L2、第三层L3、第四层L4中的任一个都没有形成金属的配线的区域表示为白色区域。如图3所示，以包围第四层L4的形成有焊盘21b的区域的方式，在第一层L1(配线21除外)、第二层L2、第三层L3、第四层L4形成有没有配线的区域。这是基于抑制与焊盘21b的电容耦合等理由。
这样，在着眼于某一个层时，在上下层(其他层)未形成由金属构成的配线的部分作为配线基板2的强度降低。因此，在与配线基板2粘接的第一粘接层4产生龟裂、应力施加于此的情况下等，龟裂有可能延伸到该部分。特别是在第一层L1，由于位于第一粘接层4的端部的附近，所以容易直接被施加由于该龟裂的产生导致的应力。
因此，在本实施方式中，将在第一层L1、第二层L2、第三层L3、第四层L4中的任一个都没有形成配线的图3的白色区域内、以及从与在第一层L1、第二层L2、第三层L3、第四层L4的至少一层存在配线的部分重叠的部位(图3所示的点A)起半径200μm以内的范围(图3所示的点B为止的范围)内的配线21设为宽幅部21a。另外，半径200μm以内的范围是指最大时的范围，还可以将比此狭小的范围例如半径100μm以内的范围设为宽幅部21a。特别是在第一粘接层4容易产生龟裂的第一粘接层4的端部附近以外的部位，可以缩窄作为宽幅部21a的范围。例如，可以是，在第一粘接层4的端部附近设为宽幅部21a的范围是半径200μm，在第一粘接层4的端部附近以外的部位例如第一粘接层4的中心部附近半径是100μm。或者，还可以是，在第一粘接层4的端部附近以外的部位不形成宽幅部21a。
换言之，成为在配线基板2的从部位A起半径200μm以内的范围设置有宽幅部21a的结构，该部位A是配线基板2的从形成于在上下层没有配线的区域的焊盘21b的焊盘引出部21c引出的配线21与在上下层存在配线的部位重叠的部位。由此，在配线基板2的强度降低的部分，能够通过宽幅部21a加强配线基板2。
另外，上述的与在上下层存在配线的部分重叠的部位A处的上下层的配线，往往是指作为各层间的噪声屏蔽发挥作用的接地配线，但也包含电源配线、其他的层的信号配线等。但是，不包括形成为圆形的岛状等而不与其他配线电连接的浮置的金属图案。
如上所述，通过在配线21的一部分设置宽幅部21a，即使是PCIe等需要阻抗控制的配线，也能够确保电气性能。如上所述，在本实施方式中，如果将配线21的线宽整体加粗，则不能满足所需要的电气性能的一部分。因此，不能将配线21的线宽整体加粗而对配线基板2进行加强，如上所述，将配线21的线宽基本上设为30μm。
例如，在频率4GHz的差分回馈损耗(Differential Return Loss)等中，例如在配线21的线宽为30μm时，即使在上述的范围内设置线宽为50μm的宽幅部21a，也能够确保所需要的电气性能。
如上所述，对于本实施方式的半导体封装体1，即使是需要阻抗控制的高速的配线21的情况，也能够对配线基板2进行加强，使得将第一半导体芯片3粘接于配线基板2的第一粘接层(FOD)4的龟裂不会一直延伸到配线基板2。
另外，在以上的说明中，对配线基板2的第一层L1进行了说明，但对于第一层L1以外的层例如第二层L2、第三层L3、第四层L4等，同样也能够适用。
下面，参照图4、图5对前述的形成为圆形的岛状等、不与其他配线电连接的浮置的金属图案30b、30c进行说明。如前面所述，图3所示的白色的区域内是在其他的层(在图3中指第一层L1(配线21除外)、第二层L2、第三层L3、第四层L4)没有形成配线的区域。这样，在一个层内存在没有形成配线的比较大的区域时，有时在该部分产生凹坑等。因此，有时在没有形成配线的其他的层如图4所示，设置位于白色区域内的浮置的金属图案30b。另外，金属图案30a从第四层L4一直导通到第一层L1的引出部21c。
作为一个比较例进行说明的浮置的金属图案，在各层都设置成相同的图案排列及尺寸。与此相对，在本实施方式中，例如在第二层L2设置图4所示的图案排列及尺寸的浮置的金属图案30b，在第二层L2以外的层例如第三层L3和第一层L1，设置图5所示的图案排列及尺寸的浮置的金属图案30c。
如上所述，通过在配线基板2的不同的层设置不同的图案排列及尺寸的浮置的金属图案30b及浮置的金属图案30c，在它们重叠时，能够减少白色区域内没有金属图案的区域。通过设为这样的结构，能够抑制在配线基板2产生局部强度减弱的部位，能够对配线基板2进行加强，使得将第一半导体芯片3粘接于配线基板2的第一粘接层(FOD)4的龟裂不会一直延伸到配线基板2。
另外，作为一个比较例，图6表示在不具有浮置图案时从第一层L1到第四层L4的焊盘部的实施方式。斜线或者纵线表示存在金属的配线图案。在第四层L4的焊盘的周围没有设置金属的图案。从第四层L4到第一层L1经由通孔连接。在第一层L1、第二层L2、第三层L3，没有设置金属的配线的部分很大。如果是这种结构，则有时导致配线基板2的强度减弱。
以上对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提示的，并非意图限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种各样的省略、替换、变更等。这些实施方式及其变形被包含在发明的范围或主旨中，并且被包含在权利要求书所记载的发明和其等价的范围中。

Claims (6)

1.一种半导体装置，其具备：
多层的配线基板，具有多个配线层；
第一半导体芯片，安装于所述配线基板；以及
粘接层，将所述第一半导体芯片粘接于所述配线基板，
在所述配线基板形成的配线具有部分地加粗线宽的宽幅部，其中该配线是传输1GHz以上的信号的需要阻抗控制的高速配线，并且从与连接外部的焊盘相连接的焊盘引出部引出，
在从所述配线中的重叠部起半径200μm以内的范围中设置有所述宽幅部，其中所述重叠部是从与所述配线基板的表面垂直的方向观察时，所述配线穿过在所述配线层的所有层都不存在所述配线以外的金属配线的区域之后，与在所述配线层的至少一层存在所述配线以外的金属配线的部分相交的部位。
2.根据权利要求1所述的半导体装置，其特征在于，
将在所述粘接层的端部附近从所述重叠部起设置有所述宽幅部的范围作为第一范围，将在所述粘接层的中心部从所述重叠部起设置有所述宽幅部的范围作为第二范围，所述第一范围大于所述第二范围。
3.根据权利要求1所述的半导体装置，其中，
所述宽幅部从与所述配线基板的表面垂直的方向观察时只设置于所述粘接层的端部附近。
4.根据权利要求1所述的半导体装置，其中，
所述半导体装置具有浮置的金属图案，所述金属图案设置于所述配线基板的比形成有所述焊盘的层靠上层，从与所述配线基板的表面垂直的方向观察时，与所述焊盘重叠，
所述金属图案具有至少在两个层中不同的图案。
5.根据权利要求1～4中任一项所述的半导体装置，其中，
所述宽幅部的线宽为40μm以上60μm以下。
6.根据权利要求1～4中任一项所述的半导体装置，其中，
所述配线的线宽为30μm以上且小于35μm。
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